File: H:\EECS_461\project\Final_Project_rappid_rtw\mpc5643l.h

    1   /****************************************************************************\
    2    * PROJECT       : MPC5643L
    3    * FILE          : mpc5643l.h
    4    *
    5    * DESCRIPTION   : This is the header file describing the register
    6    *                 set for the named projects.
    7    *
    8    * COPYRIGHT     : (c) 2009,2010, Freescale Semiconductor & ST Microelectronics
    9    *
   10    * VERSION       : 2.00
   11    * RELEASE DATE  : -not released-
   12    * CREATION DATE : Mon Dec  6 19:30:32 CET 2010
   13    * AUTHOR        : generated from IP-XACT database
   14    * HISTORY       : Preliminary release.
   15    *				 For eTimer, added ETIMER_2 (against mcTIMER2) as a module name
   16    *				 -By RAppID Team(Feb 7, 2011)
   17    *				 : TEST_MC (0x0024) register is added and ME.MER register Test bit (bit 30) added.
   18    *				 -By RAppID Team(Feb 17, 2011)
   19    *				 :Following union added for flexRay module:F_HEADER_t,S_STATUS_t,MB_HEADER_t
   20    *               -By RAppID Team(March 31, 2011)
   21      \****************************************************************************/
   22   
   23   /*   >>>>  NOTE! this file is auto-generated please do not edit it!  <<<<   */
   24   
   25   /****************************************************************************\
   26    * Example instantiation and use:
   27    *
   28    *  <MODULE>.<REGISTER>.B.<BIT> = 1;
   29    *  <MODULE>.<REGISTER>.R       = 0x10000000;
   30    *
   31      \****************************************************************************/
   32   
   33   /*
   34    *  LICENSE:
   35    *  Copyright (c) 2006 Freescale Semiconductor
   36    *
   37    *  Permission is hereby granted, free of charge, to any person
   38    *  obtaining a copy of this software and associated documentation
   39    *  files (the "Software"), to deal in the Software without
   40    *  restriction, including without limitation the rights to use,
   41    *  copy, modify, merge, publish, distribute, sublicense, and/or
   42    *  sell copies of the Software, and to permit persons to whom the
   43    *  Software is furnished to do so, subject to the following
   44    *  conditions:
   45    *
   46    *  The above copyright notice and this permission notice
   47    *  shall be included in all copies or substantial portions
   48    *  of the Software.
   49    *
   50    *  THIS SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
   51    *  EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
   52    *  OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
   53    *  NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
   54    *  HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
   55    *  WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
   56    *  OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
   57    *  DEALINGS IN THE SOFTWARE.
   58    *
   59    */
   60   
   61   /* MJR 02-Dec-2010:
   62      Changes between the last version for the cut-1 device and this version:
   63   
   64    * Added entries for the DCF clients to the Shadow Flash Area
   65    * Fixed field sizes for the block selections in the Flash controller
   66    * Modified WKPU, now have the correctly parameterized block instead generic
   67    * Complete rehaul of the SSCM register structure, specific special test regs
   68    * Fixed some fields in the ME structure, remove of non-existing MC_STANDBY
   69    * Parameterized PLL, now PLL_ON bit is gone (parameter dependent)
   70    * Complete rehaul of the RGM, not have an exact match with parameterization
   71    * Fixed CDATA field in ADC
   72    * Corrected number of FIFO's in LINFlex
   73    * CRC modules allows now one more polynom, adjusted field size of POLYG
   74    * Some FCCU registers have been renamed to use a consistent naming scheme
   75      that avoid naming collisions in the #define based header
   76    * Field corrections in the Sine Wave Generator block
   77    * Added entries for the PFlash Controller
   78    * Fixed MPROT register in the PBRIGDE
   79    * Reflected the DSI functionality in the DSPI, corrected parameterization
   80    * Fixed SMBA in FlexRay
   81    * Many other minor fixes
   82   
   83      KNOWN ISSUES:
   84    * Register map of CGM is still not correctly parameterized, removed
   85    * Incorrect modeling of register arrays that have multiple access sizes
   86    * Incorrect modeling of replicated bits with different access types
   87    */
   88   #ifndef _leopard_H_                    /* prevents multiple inclusions of this file */
   89   #define _leopard_H_
   90   #include "typedefs.h"
   91   #ifdef __cplusplus
   92   
   93   extern "C" {
   94   
   95   #endif
   96   
   97   #ifdef __MWERKS__
   98   
   99   #pragma push
  100   #pragma ANSI_strict off
  101   
  102   #endif
  103   
  104     // #define USE_FIELD_ALIASES_CFLASH
  105     // #define USE_FIELD_ALIASES_SIUL
  106     // #define USE_FIELD_ALIASES_ME
  107     // #define USE_FIELD_ALIASES_PLLD
  108     // #define USE_FIELD_ALIASES_CMU
  109     // #define USE_FIELD_ALIASES_RGM
  110     // #define USE_FIELD_ALIASES_ADC
  111     // #define USE_FIELD_ALIASES_CTU
  112     // #define USE_FIELD_ALIASES_mcTIMER
  113     // #define USE_FIELD_ALIASES_mcPWM
  114     // #define USE_FIELD_ALIASES_LINFLEX
  115     // #define USE_FIELD_ALIASES_SPP_MCM
  116     // #define USE_FIELD_ALIASES_SPP_DMA2
  117     // #define USE_FIELD_ALIASES_INTC
  118     // #define USE_FIELD_ALIASES_DSPI
  119     // #define USE_FIELD_ALIASES_FLEXCAN
  120     // #define USE_FIELD_ALIASES_FR
  121     /****************************************************************/
  122     /*                                                              */
  123     /* Global definitions and aliases */
  124     /*                                                              */
  125     /****************************************************************/
  126   
  127     /*
  128        Platform blocks that are only accessible by the second core (core 1) when
  129        the device is in DPM mode. The block definition is equivalent to the one
  130        for the first core (core 0) and reuses the related block structure.
  131   
  132        NOTE: the <block_name>_1 defines are the preferred method for programming
  133      */
  134   #define PBRIDGE_1                      (*(volatile PBRIDGE_tag*) 0x8FF00000UL)
  135   #define MAX_1                          (*(volatile MAX_tag*) 0x8FF04000UL)
  136   #define MPU_1                          (*(volatile MPU_tag*) 0x8FF10000UL)
  137   #define SEMA4_1                        (*(volatile SEMA4_tag*) 0x8FF24000UL)
  138   #define SWT_1                          (*(volatile SWT_tag*) 0x8FF38000UL)
  139   #define STM_1                          (*(volatile STM_tag*) 0x8FF3C000UL)
  140   #define SPP_MCM_1                      (*(volatile SPP_MCM_tag*) 0x8FF40000UL)
  141   #define SPP_DMA2_1                     (*(volatile SPP_DMA2_tag*) 0x8FF44000UL)
  142   #define INTC_1                         (*(volatile INTC_tag*) 0x8FF48000UL)
  143   
  144     /*
  145        Platform blocks that are only accessible by the second core (core 1) when
  146        the device is in DPM mode. The block definition is equivalent to the one
  147        for the first core (core 0) and reuses the related block structure.
  148   
  149        NOTE: the <block_name>_DPM defines are deprecated, use <block_name>_1 for
  150        programming the corresponding blocks for new code instead.
  151      */
  152   #define PBRIDGE_DPM                    PBRIDGE_1
  153   #define MAX_DPM                        MAX_1
  154   #define MPU_DPM                        MPU_1
  155   #define SEMA4_DPM                      SEMA4_1
  156   #define SWT_DPM                        SWT_1
  157   #define STM_DPM                        STM_1
  158   #define SPP_MCM_DPM                    SPP_MCM_1
  159   #define SPP_DMA2_DPM                   SPP_DMA2_1
  160   #define INTC_DPM                       INTC_1
  161   
  162     /* Aliases for Pictus Module names */
  163   #define CAN_0                          FLEXCAN_A
  164   #define CAN_1                          FLEXCAN_B
  165   #define CTU_0                          CTU
  166   #define DFLASH                         CRC
  167   #define DMAMUX                         DMA_CH_MUX
  168   #define DSPI_0                         DSPI_A
  169   #define DSPI_1                         DSPI_B
  170   #define DSPI_2                         DSPI_C
  171   #define EDMA                           SPP_DMA2
  172   #define ETIMER_0                       mcTIMER0
  173   #define ETIMER_1                       mcTIMER1
  174   #define ETIMER_2                       mcTIMER2
  175   #define FLEXPWM_0                      mcPWM_A
  176   #define FLEXPWM_1                      mcPWM_B
  177   #define LINFLEX_0                      LINFLEX0
  178   #define LINFLEX_1                      LINFLEX1
  179   #define MCM_                           SPP_MCM
  180   #define PIT                            PIT_RTI
  181   #define SIU                            SIUL
  182   #define WKUP                           WKPU
  183   #define ADC_0                          ADC0
  184   #define ADC_1                          ADC1
  185   
  186     /* Other Aliases */
  187   #define AIPS_DPM                       PBRIDGE_1
  188   #define AIPS_1                         PBRIDGE_1
  189   #define AIPS                           PBRIDGE
  190   
  191     /****************************************************************/
  192     /*                                                              */
  193     /* Module: CFLASH_SHADOW  */
  194     /*                                                              */
  195     /****************************************************************/
  196   
  197     /* Register layout for all registers DCF_RECORDx ... */
  198     typedef union {                      /* First portion of a DCF record - do not use */
  199       vuint32_t R;
  200     } CFLASH_SHADOW_DCF_RECORDx_32B_tag;
  201   
  202     /* Register layout for all registers DCF_RECORDy ... */
  203     typedef union {                      /* Second portion of a DCF record - do not use */
  204       vuint32_t R;
  205     } CFLASH_SHADOW_DCF_RECORDy_32B_tag;
  206   
  207     /* Register layout for all registers NVPWD ... */
  208     typedef union {                      /* NVPWD0-1 - Non Volatile Private Censorship PassWorD Register */
  209       vuint32_t R;
  210       struct {
  211         vuint32_t PWD:32;                /* PassWorD */
  212       } B;
  213     } CFLASH_SHADOW_NVPWD_32B_tag;
  214   
  215     /* Register layout for all registers NVSCI ... */
  216     typedef union {                      /* NVSCI - Non Volatile System Censoring Information Register */
  217       vuint32_t R;
  218       struct {
  219         vuint32_t SC:16;                 /* Serial Censorship Control Word */
  220         vuint32_t CW:16;                 /* Censorship Control Word */
  221       } B;
  222     } CFLASH_SHADOW_NVSCI_32B_tag;
  223   
  224     typedef union {                      /* Non Volatile LML Default Value */
  225       vuint32_t R;
  226     } CFLASH_SHADOW_NVLML_32B_tag;
  227   
  228     typedef union {                      /* Non Volatile HBL Default Value */
  229       vuint32_t R;
  230     } CFLASH_SHADOW_NVHBL_32B_tag;
  231   
  232     typedef union {                      /* Non Volatile SLL Default Value */
  233       vuint32_t R;
  234     } CFLASH_SHADOW_NVSLL_32B_tag;
  235   
  236     /* Register layout for all registers NVBIU ... */
  237     typedef union {                      /* Non Volatile Bus Interface Unit Register */
  238       vuint32_t R;
  239       struct {
  240         vuint32_t BI:32;                 /* Bus interface Unit */
  241       } B;
  242     } CFLASH_SHADOW_NVBIU_32B_tag;
  243   
  244     typedef union {                      /* NVUSRO - Non Volatile USeR Options Register */
  245       vuint32_t R;
  246       struct {
  247         vuint32_t UO:32;                 /* User Options */
  248       } B;
  249     } CFLASH_SHADOW_NVUSRO_32B_tag;
  250   
  251     typedef struct CFLASH_SHADOW_DCF_AREA_struct_tag {
  252       /* First portion of a DCF record - do not use */
  253       CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORDx;/* relative offset: 0x0000 */
  254   
  255       /* Second portion of a DCF record - do not use */
  256       CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORDy;/* relative offset: 0x0004 */
  257       int8_t CFLASH_SHADOW_DCF_AREA_reserved_0008[8];
  258     } CFLASH_SHADOW_DCF_AREA_tag;
  259   
  260     typedef struct CFLASH_SHADOW_BIU_DEFAULTS_struct_tag {
  261       /* Non Volatile Bus Interface Unit Register */
  262       CFLASH_SHADOW_NVBIU_32B_tag NVBIU; /* relative offset: 0x0000 */
  263       int8_t CFLASH_SHADOW_BIU_DEFAULTS_reserved_0004[4];
  264     } CFLASH_SHADOW_BIU_DEFAULTS_tag;
  265   
  266     typedef struct CFLASH_SHADOW_struct_tag {
  267       int8_t CFLASH_SHADOW_reserved_0000[16];
  268       union {
  269         /*  Register set DCF_AREA */
  270         CFLASH_SHADOW_DCF_AREA_tag DCF_AREA[128];/* offset: 0x0010  (0x0010 x 128) */
  271         struct {
  272           /* First portion of a DCF record - do not use */
  273           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD0x;/* offset: 0x0010 size: 32 bit */
  274   
  275           /* Second portion of a DCF record - do not use */
  276           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD0y;/* offset: 0x0014 size: 32 bit */
  277           int8_t CFLASH_SHADOW_reserved_0018_I1[8];
  278   
  279           /* First portion of a DCF record - do not use */
  280           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD1x;/* offset: 0x0020 size: 32 bit */
  281   
  282           /* Second portion of a DCF record - do not use */
  283           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD1y;/* offset: 0x0024 size: 32 bit */
  284           int8_t CFLASH_SHADOW_reserved_0028_I1[8];
  285   
  286           /* First portion of a DCF record - do not use */
  287           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD2x;/* offset: 0x0030 size: 32 bit */
  288   
  289           /* Second portion of a DCF record - do not use */
  290           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD2y;/* offset: 0x0034 size: 32 bit */
  291           int8_t CFLASH_SHADOW_reserved_0038_I1[8];
  292   
  293           /* First portion of a DCF record - do not use */
  294           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD3x;/* offset: 0x0040 size: 32 bit */
  295   
  296           /* Second portion of a DCF record - do not use */
  297           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD3y;/* offset: 0x0044 size: 32 bit */
  298           int8_t CFLASH_SHADOW_reserved_0048_I1[8];
  299   
  300           /* First portion of a DCF record - do not use */
  301           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD4x;/* offset: 0x0050 size: 32 bit */
  302   
  303           /* Second portion of a DCF record - do not use */
  304           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD4y;/* offset: 0x0054 size: 32 bit */
  305           int8_t CFLASH_SHADOW_reserved_0058_I1[8];
  306   
  307           /* First portion of a DCF record - do not use */
  308           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD5x;/* offset: 0x0060 size: 32 bit */
  309   
  310           /* Second portion of a DCF record - do not use */
  311           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD5y;/* offset: 0x0064 size: 32 bit */
  312           int8_t CFLASH_SHADOW_reserved_0068_I1[8];
  313   
  314           /* First portion of a DCF record - do not use */
  315           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD6x;/* offset: 0x0070 size: 32 bit */
  316   
  317           /* Second portion of a DCF record - do not use */
  318           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD6y;/* offset: 0x0074 size: 32 bit */
  319           int8_t CFLASH_SHADOW_reserved_0078_I1[8];
  320   
  321           /* First portion of a DCF record - do not use */
  322           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD7x;/* offset: 0x0080 size: 32 bit */
  323   
  324           /* Second portion of a DCF record - do not use */
  325           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD7y;/* offset: 0x0084 size: 32 bit */
  326           int8_t CFLASH_SHADOW_reserved_0088_I1[8];
  327   
  328           /* First portion of a DCF record - do not use */
  329           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD8x;/* offset: 0x0090 size: 32 bit */
  330   
  331           /* Second portion of a DCF record - do not use */
  332           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD8y;/* offset: 0x0094 size: 32 bit */
  333           int8_t CFLASH_SHADOW_reserved_0098_I1[8];
  334   
  335           /* First portion of a DCF record - do not use */
  336           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD9x;/* offset: 0x00A0 size: 32 bit */
  337   
  338           /* Second portion of a DCF record - do not use */
  339           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD9y;/* offset: 0x00A4 size: 32 bit */
  340           int8_t CFLASH_SHADOW_reserved_00A8_I1[8];
  341   
  342           /* First portion of a DCF record - do not use */
  343           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD10x;/* offset: 0x00B0 size: 32 bit */
  344   
  345           /* Second portion of a DCF record - do not use */
  346           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD10y;/* offset: 0x00B4 size: 32 bit */
  347           int8_t CFLASH_SHADOW_reserved_00B8_I1[8];
  348   
  349           /* First portion of a DCF record - do not use */
  350           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD11x;/* offset: 0x00C0 size: 32 bit */
  351   
  352           /* Second portion of a DCF record - do not use */
  353           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD11y;/* offset: 0x00C4 size: 32 bit */
  354           int8_t CFLASH_SHADOW_reserved_00C8_I1[8];
  355   
  356           /* First portion of a DCF record - do not use */
  357           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD12x;/* offset: 0x00D0 size: 32 bit */
  358   
  359           /* Second portion of a DCF record - do not use */
  360           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD12y;/* offset: 0x00D4 size: 32 bit */
  361           int8_t CFLASH_SHADOW_reserved_00D8_I1[8];
  362   
  363           /* First portion of a DCF record - do not use */
  364           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD13x;/* offset: 0x00E0 size: 32 bit */
  365   
  366           /* Second portion of a DCF record - do not use */
  367           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD13y;/* offset: 0x00E4 size: 32 bit */
  368           int8_t CFLASH_SHADOW_reserved_00E8_I1[8];
  369   
  370           /* First portion of a DCF record - do not use */
  371           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD14x;/* offset: 0x00F0 size: 32 bit */
  372   
  373           /* Second portion of a DCF record - do not use */
  374           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD14y;/* offset: 0x00F4 size: 32 bit */
  375           int8_t CFLASH_SHADOW_reserved_00F8_I1[8];
  376   
  377           /* First portion of a DCF record - do not use */
  378           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD15x;/* offset: 0x0100 size: 32 bit */
  379   
  380           /* Second portion of a DCF record - do not use */
  381           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD15y;/* offset: 0x0104 size: 32 bit */
  382           int8_t CFLASH_SHADOW_reserved_0108_I1[8];
  383   
  384           /* First portion of a DCF record - do not use */
  385           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD16x;/* offset: 0x0110 size: 32 bit */
  386   
  387           /* Second portion of a DCF record - do not use */
  388           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD16y;/* offset: 0x0114 size: 32 bit */
  389           int8_t CFLASH_SHADOW_reserved_0118_I1[8];
  390   
  391           /* First portion of a DCF record - do not use */
  392           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD17x;/* offset: 0x0120 size: 32 bit */
  393   
  394           /* Second portion of a DCF record - do not use */
  395           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD17y;/* offset: 0x0124 size: 32 bit */
  396           int8_t CFLASH_SHADOW_reserved_0128_I1[8];
  397   
  398           /* First portion of a DCF record - do not use */
  399           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD18x;/* offset: 0x0130 size: 32 bit */
  400   
  401           /* Second portion of a DCF record - do not use */
  402           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD18y;/* offset: 0x0134 size: 32 bit */
  403           int8_t CFLASH_SHADOW_reserved_0138_I1[8];
  404   
  405           /* First portion of a DCF record - do not use */
  406           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD19x;/* offset: 0x0140 size: 32 bit */
  407   
  408           /* Second portion of a DCF record - do not use */
  409           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD19y;/* offset: 0x0144 size: 32 bit */
  410           int8_t CFLASH_SHADOW_reserved_0148_I1[8];
  411   
  412           /* First portion of a DCF record - do not use */
  413           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD20x;/* offset: 0x0150 size: 32 bit */
  414   
  415           /* Second portion of a DCF record - do not use */
  416           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD20y;/* offset: 0x0154 size: 32 bit */
  417           int8_t CFLASH_SHADOW_reserved_0158_I1[8];
  418   
  419           /* First portion of a DCF record - do not use */
  420           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD21x;/* offset: 0x0160 size: 32 bit */
  421   
  422           /* Second portion of a DCF record - do not use */
  423           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD21y;/* offset: 0x0164 size: 32 bit */
  424           int8_t CFLASH_SHADOW_reserved_0168_I1[8];
  425   
  426           /* First portion of a DCF record - do not use */
  427           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD22x;/* offset: 0x0170 size: 32 bit */
  428   
  429           /* Second portion of a DCF record - do not use */
  430           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD22y;/* offset: 0x0174 size: 32 bit */
  431           int8_t CFLASH_SHADOW_reserved_0178_I1[8];
  432   
  433           /* First portion of a DCF record - do not use */
  434           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD23x;/* offset: 0x0180 size: 32 bit */
  435   
  436           /* Second portion of a DCF record - do not use */
  437           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD23y;/* offset: 0x0184 size: 32 bit */
  438           int8_t CFLASH_SHADOW_reserved_0188_I1[8];
  439   
  440           /* First portion of a DCF record - do not use */
  441           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD24x;/* offset: 0x0190 size: 32 bit */
  442   
  443           /* Second portion of a DCF record - do not use */
  444           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD24y;/* offset: 0x0194 size: 32 bit */
  445           int8_t CFLASH_SHADOW_reserved_0198_I1[8];
  446   
  447           /* First portion of a DCF record - do not use */
  448           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD25x;/* offset: 0x01A0 size: 32 bit */
  449   
  450           /* Second portion of a DCF record - do not use */
  451           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD25y;/* offset: 0x01A4 size: 32 bit */
  452           int8_t CFLASH_SHADOW_reserved_01A8_I1[8];
  453   
  454           /* First portion of a DCF record - do not use */
  455           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD26x;/* offset: 0x01B0 size: 32 bit */
  456   
  457           /* Second portion of a DCF record - do not use */
  458           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD26y;/* offset: 0x01B4 size: 32 bit */
  459           int8_t CFLASH_SHADOW_reserved_01B8_I1[8];
  460   
  461           /* First portion of a DCF record - do not use */
  462           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD27x;/* offset: 0x01C0 size: 32 bit */
  463   
  464           /* Second portion of a DCF record - do not use */
  465           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD27y;/* offset: 0x01C4 size: 32 bit */
  466           int8_t CFLASH_SHADOW_reserved_01C8_I1[8];
  467   
  468           /* First portion of a DCF record - do not use */
  469           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD28x;/* offset: 0x01D0 size: 32 bit */
  470   
  471           /* Second portion of a DCF record - do not use */
  472           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD28y;/* offset: 0x01D4 size: 32 bit */
  473           int8_t CFLASH_SHADOW_reserved_01D8_I1[8];
  474   
  475           /* First portion of a DCF record - do not use */
  476           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD29x;/* offset: 0x01E0 size: 32 bit */
  477   
  478           /* Second portion of a DCF record - do not use */
  479           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD29y;/* offset: 0x01E4 size: 32 bit */
  480           int8_t CFLASH_SHADOW_reserved_01E8_I1[8];
  481   
  482           /* First portion of a DCF record - do not use */
  483           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD30x;/* offset: 0x01F0 size: 32 bit */
  484   
  485           /* Second portion of a DCF record - do not use */
  486           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD30y;/* offset: 0x01F4 size: 32 bit */
  487           int8_t CFLASH_SHADOW_reserved_01F8_I1[8];
  488   
  489           /* First portion of a DCF record - do not use */
  490           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD31x;/* offset: 0x0200 size: 32 bit */
  491   
  492           /* Second portion of a DCF record - do not use */
  493           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD31y;/* offset: 0x0204 size: 32 bit */
  494           int8_t CFLASH_SHADOW_reserved_0208_I1[8];
  495   
  496           /* First portion of a DCF record - do not use */
  497           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD32x;/* offset: 0x0210 size: 32 bit */
  498   
  499           /* Second portion of a DCF record - do not use */
  500           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD32y;/* offset: 0x0214 size: 32 bit */
  501           int8_t CFLASH_SHADOW_reserved_0218_I1[8];
  502   
  503           /* First portion of a DCF record - do not use */
  504           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD33x;/* offset: 0x0220 size: 32 bit */
  505   
  506           /* Second portion of a DCF record - do not use */
  507           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD33y;/* offset: 0x0224 size: 32 bit */
  508           int8_t CFLASH_SHADOW_reserved_0228_I1[8];
  509   
  510           /* First portion of a DCF record - do not use */
  511           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD34x;/* offset: 0x0230 size: 32 bit */
  512   
  513           /* Second portion of a DCF record - do not use */
  514           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD34y;/* offset: 0x0234 size: 32 bit */
  515           int8_t CFLASH_SHADOW_reserved_0238_I1[8];
  516   
  517           /* First portion of a DCF record - do not use */
  518           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD35x;/* offset: 0x0240 size: 32 bit */
  519   
  520           /* Second portion of a DCF record - do not use */
  521           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD35y;/* offset: 0x0244 size: 32 bit */
  522           int8_t CFLASH_SHADOW_reserved_0248_I1[8];
  523   
  524           /* First portion of a DCF record - do not use */
  525           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD36x;/* offset: 0x0250 size: 32 bit */
  526   
  527           /* Second portion of a DCF record - do not use */
  528           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD36y;/* offset: 0x0254 size: 32 bit */
  529           int8_t CFLASH_SHADOW_reserved_0258_I1[8];
  530   
  531           /* First portion of a DCF record - do not use */
  532           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD37x;/* offset: 0x0260 size: 32 bit */
  533   
  534           /* Second portion of a DCF record - do not use */
  535           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD37y;/* offset: 0x0264 size: 32 bit */
  536           int8_t CFLASH_SHADOW_reserved_0268_I1[8];
  537   
  538           /* First portion of a DCF record - do not use */
  539           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD38x;/* offset: 0x0270 size: 32 bit */
  540   
  541           /* Second portion of a DCF record - do not use */
  542           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD38y;/* offset: 0x0274 size: 32 bit */
  543           int8_t CFLASH_SHADOW_reserved_0278_I1[8];
  544   
  545           /* First portion of a DCF record - do not use */
  546           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD39x;/* offset: 0x0280 size: 32 bit */
  547   
  548           /* Second portion of a DCF record - do not use */
  549           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD39y;/* offset: 0x0284 size: 32 bit */
  550           int8_t CFLASH_SHADOW_reserved_0288_I1[8];
  551   
  552           /* First portion of a DCF record - do not use */
  553           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD40x;/* offset: 0x0290 size: 32 bit */
  554   
  555           /* Second portion of a DCF record - do not use */
  556           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD40y;/* offset: 0x0294 size: 32 bit */
  557           int8_t CFLASH_SHADOW_reserved_0298_I1[8];
  558   
  559           /* First portion of a DCF record - do not use */
  560           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD41x;/* offset: 0x02A0 size: 32 bit */
  561   
  562           /* Second portion of a DCF record - do not use */
  563           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD41y;/* offset: 0x02A4 size: 32 bit */
  564           int8_t CFLASH_SHADOW_reserved_02A8_I1[8];
  565   
  566           /* First portion of a DCF record - do not use */
  567           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD42x;/* offset: 0x02B0 size: 32 bit */
  568   
  569           /* Second portion of a DCF record - do not use */
  570           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD42y;/* offset: 0x02B4 size: 32 bit */
  571           int8_t CFLASH_SHADOW_reserved_02B8_I1[8];
  572   
  573           /* First portion of a DCF record - do not use */
  574           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD43x;/* offset: 0x02C0 size: 32 bit */
  575   
  576           /* Second portion of a DCF record - do not use */
  577           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD43y;/* offset: 0x02C4 size: 32 bit */
  578           int8_t CFLASH_SHADOW_reserved_02C8_I1[8];
  579   
  580           /* First portion of a DCF record - do not use */
  581           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD44x;/* offset: 0x02D0 size: 32 bit */
  582   
  583           /* Second portion of a DCF record - do not use */
  584           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD44y;/* offset: 0x02D4 size: 32 bit */
  585           int8_t CFLASH_SHADOW_reserved_02D8_I1[8];
  586   
  587           /* First portion of a DCF record - do not use */
  588           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD45x;/* offset: 0x02E0 size: 32 bit */
  589   
  590           /* Second portion of a DCF record - do not use */
  591           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD45y;/* offset: 0x02E4 size: 32 bit */
  592           int8_t CFLASH_SHADOW_reserved_02E8_I1[8];
  593   
  594           /* First portion of a DCF record - do not use */
  595           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD46x;/* offset: 0x02F0 size: 32 bit */
  596   
  597           /* Second portion of a DCF record - do not use */
  598           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD46y;/* offset: 0x02F4 size: 32 bit */
  599           int8_t CFLASH_SHADOW_reserved_02F8_I1[8];
  600   
  601           /* First portion of a DCF record - do not use */
  602           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD47x;/* offset: 0x0300 size: 32 bit */
  603   
  604           /* Second portion of a DCF record - do not use */
  605           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD47y;/* offset: 0x0304 size: 32 bit */
  606           int8_t CFLASH_SHADOW_reserved_0308_I1[8];
  607   
  608           /* First portion of a DCF record - do not use */
  609           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD48x;/* offset: 0x0310 size: 32 bit */
  610   
  611           /* Second portion of a DCF record - do not use */
  612           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD48y;/* offset: 0x0314 size: 32 bit */
  613           int8_t CFLASH_SHADOW_reserved_0318_I1[8];
  614   
  615           /* First portion of a DCF record - do not use */
  616           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD49x;/* offset: 0x0320 size: 32 bit */
  617   
  618           /* Second portion of a DCF record - do not use */
  619           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD49y;/* offset: 0x0324 size: 32 bit */
  620           int8_t CFLASH_SHADOW_reserved_0328_I1[8];
  621   
  622           /* First portion of a DCF record - do not use */
  623           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD50x;/* offset: 0x0330 size: 32 bit */
  624   
  625           /* Second portion of a DCF record - do not use */
  626           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD50y;/* offset: 0x0334 size: 32 bit */
  627           int8_t CFLASH_SHADOW_reserved_0338_I1[8];
  628   
  629           /* First portion of a DCF record - do not use */
  630           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD51x;/* offset: 0x0340 size: 32 bit */
  631   
  632           /* Second portion of a DCF record - do not use */
  633           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD51y;/* offset: 0x0344 size: 32 bit */
  634           int8_t CFLASH_SHADOW_reserved_0348_I1[8];
  635   
  636           /* First portion of a DCF record - do not use */
  637           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD52x;/* offset: 0x0350 size: 32 bit */
  638   
  639           /* Second portion of a DCF record - do not use */
  640           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD52y;/* offset: 0x0354 size: 32 bit */
  641           int8_t CFLASH_SHADOW_reserved_0358_I1[8];
  642   
  643           /* First portion of a DCF record - do not use */
  644           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD53x;/* offset: 0x0360 size: 32 bit */
  645   
  646           /* Second portion of a DCF record - do not use */
  647           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD53y;/* offset: 0x0364 size: 32 bit */
  648           int8_t CFLASH_SHADOW_reserved_0368_I1[8];
  649   
  650           /* First portion of a DCF record - do not use */
  651           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD54x;/* offset: 0x0370 size: 32 bit */
  652   
  653           /* Second portion of a DCF record - do not use */
  654           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD54y;/* offset: 0x0374 size: 32 bit */
  655           int8_t CFLASH_SHADOW_reserved_0378_I1[8];
  656   
  657           /* First portion of a DCF record - do not use */
  658           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD55x;/* offset: 0x0380 size: 32 bit */
  659   
  660           /* Second portion of a DCF record - do not use */
  661           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD55y;/* offset: 0x0384 size: 32 bit */
  662           int8_t CFLASH_SHADOW_reserved_0388_I1[8];
  663   
  664           /* First portion of a DCF record - do not use */
  665           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD56x;/* offset: 0x0390 size: 32 bit */
  666   
  667           /* Second portion of a DCF record - do not use */
  668           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD56y;/* offset: 0x0394 size: 32 bit */
  669           int8_t CFLASH_SHADOW_reserved_0398_I1[8];
  670   
  671           /* First portion of a DCF record - do not use */
  672           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD57x;/* offset: 0x03A0 size: 32 bit */
  673   
  674           /* Second portion of a DCF record - do not use */
  675           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD57y;/* offset: 0x03A4 size: 32 bit */
  676           int8_t CFLASH_SHADOW_reserved_03A8_I1[8];
  677   
  678           /* First portion of a DCF record - do not use */
  679           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD58x;/* offset: 0x03B0 size: 32 bit */
  680   
  681           /* Second portion of a DCF record - do not use */
  682           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD58y;/* offset: 0x03B4 size: 32 bit */
  683           int8_t CFLASH_SHADOW_reserved_03B8_I1[8];
  684   
  685           /* First portion of a DCF record - do not use */
  686           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD59x;/* offset: 0x03C0 size: 32 bit */
  687   
  688           /* Second portion of a DCF record - do not use */
  689           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD59y;/* offset: 0x03C4 size: 32 bit */
  690           int8_t CFLASH_SHADOW_reserved_03C8_I1[8];
  691   
  692           /* First portion of a DCF record - do not use */
  693           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD60x;/* offset: 0x03D0 size: 32 bit */
  694   
  695           /* Second portion of a DCF record - do not use */
  696           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD60y;/* offset: 0x03D4 size: 32 bit */
  697           int8_t CFLASH_SHADOW_reserved_03D8_I1[8];
  698   
  699           /* First portion of a DCF record - do not use */
  700           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD61x;/* offset: 0x03E0 size: 32 bit */
  701   
  702           /* Second portion of a DCF record - do not use */
  703           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD61y;/* offset: 0x03E4 size: 32 bit */
  704           int8_t CFLASH_SHADOW_reserved_03E8_I1[8];
  705   
  706           /* First portion of a DCF record - do not use */
  707           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD62x;/* offset: 0x03F0 size: 32 bit */
  708   
  709           /* Second portion of a DCF record - do not use */
  710           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD62y;/* offset: 0x03F4 size: 32 bit */
  711           int8_t CFLASH_SHADOW_reserved_03F8_I1[8];
  712   
  713           /* First portion of a DCF record - do not use */
  714           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD63x;/* offset: 0x0400 size: 32 bit */
  715   
  716           /* Second portion of a DCF record - do not use */
  717           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD63y;/* offset: 0x0404 size: 32 bit */
  718           int8_t CFLASH_SHADOW_reserved_0408_I1[8];
  719   
  720           /* First portion of a DCF record - do not use */
  721           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD64x;/* offset: 0x0410 size: 32 bit */
  722   
  723           /* Second portion of a DCF record - do not use */
  724           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD64y;/* offset: 0x0414 size: 32 bit */
  725           int8_t CFLASH_SHADOW_reserved_0418_I1[8];
  726   
  727           /* First portion of a DCF record - do not use */
  728           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD65x;/* offset: 0x0420 size: 32 bit */
  729   
  730           /* Second portion of a DCF record - do not use */
  731           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD65y;/* offset: 0x0424 size: 32 bit */
  732           int8_t CFLASH_SHADOW_reserved_0428_I1[8];
  733   
  734           /* First portion of a DCF record - do not use */
  735           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD66x;/* offset: 0x0430 size: 32 bit */
  736   
  737           /* Second portion of a DCF record - do not use */
  738           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD66y;/* offset: 0x0434 size: 32 bit */
  739           int8_t CFLASH_SHADOW_reserved_0438_I1[8];
  740   
  741           /* First portion of a DCF record - do not use */
  742           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD67x;/* offset: 0x0440 size: 32 bit */
  743   
  744           /* Second portion of a DCF record - do not use */
  745           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD67y;/* offset: 0x0444 size: 32 bit */
  746           int8_t CFLASH_SHADOW_reserved_0448_I1[8];
  747   
  748           /* First portion of a DCF record - do not use */
  749           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD68x;/* offset: 0x0450 size: 32 bit */
  750   
  751           /* Second portion of a DCF record - do not use */
  752           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD68y;/* offset: 0x0454 size: 32 bit */
  753           int8_t CFLASH_SHADOW_reserved_0458_I1[8];
  754   
  755           /* First portion of a DCF record - do not use */
  756           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD69x;/* offset: 0x0460 size: 32 bit */
  757   
  758           /* Second portion of a DCF record - do not use */
  759           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD69y;/* offset: 0x0464 size: 32 bit */
  760           int8_t CFLASH_SHADOW_reserved_0468_I1[8];
  761   
  762           /* First portion of a DCF record - do not use */
  763           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD70x;/* offset: 0x0470 size: 32 bit */
  764   
  765           /* Second portion of a DCF record - do not use */
  766           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD70y;/* offset: 0x0474 size: 32 bit */
  767           int8_t CFLASH_SHADOW_reserved_0478_I1[8];
  768   
  769           /* First portion of a DCF record - do not use */
  770           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD71x;/* offset: 0x0480 size: 32 bit */
  771   
  772           /* Second portion of a DCF record - do not use */
  773           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD71y;/* offset: 0x0484 size: 32 bit */
  774           int8_t CFLASH_SHADOW_reserved_0488_I1[8];
  775   
  776           /* First portion of a DCF record - do not use */
  777           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD72x;/* offset: 0x0490 size: 32 bit */
  778   
  779           /* Second portion of a DCF record - do not use */
  780           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD72y;/* offset: 0x0494 size: 32 bit */
  781           int8_t CFLASH_SHADOW_reserved_0498_I1[8];
  782   
  783           /* First portion of a DCF record - do not use */
  784           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD73x;/* offset: 0x04A0 size: 32 bit */
  785   
  786           /* Second portion of a DCF record - do not use */
  787           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD73y;/* offset: 0x04A4 size: 32 bit */
  788           int8_t CFLASH_SHADOW_reserved_04A8_I1[8];
  789   
  790           /* First portion of a DCF record - do not use */
  791           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD74x;/* offset: 0x04B0 size: 32 bit */
  792   
  793           /* Second portion of a DCF record - do not use */
  794           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD74y;/* offset: 0x04B4 size: 32 bit */
  795           int8_t CFLASH_SHADOW_reserved_04B8_I1[8];
  796   
  797           /* First portion of a DCF record - do not use */
  798           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD75x;/* offset: 0x04C0 size: 32 bit */
  799   
  800           /* Second portion of a DCF record - do not use */
  801           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD75y;/* offset: 0x04C4 size: 32 bit */
  802           int8_t CFLASH_SHADOW_reserved_04C8_I1[8];
  803   
  804           /* First portion of a DCF record - do not use */
  805           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD76x;/* offset: 0x04D0 size: 32 bit */
  806   
  807           /* Second portion of a DCF record - do not use */
  808           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD76y;/* offset: 0x04D4 size: 32 bit */
  809           int8_t CFLASH_SHADOW_reserved_04D8_I1[8];
  810   
  811           /* First portion of a DCF record - do not use */
  812           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD77x;/* offset: 0x04E0 size: 32 bit */
  813   
  814           /* Second portion of a DCF record - do not use */
  815           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD77y;/* offset: 0x04E4 size: 32 bit */
  816           int8_t CFLASH_SHADOW_reserved_04E8_I1[8];
  817   
  818           /* First portion of a DCF record - do not use */
  819           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD78x;/* offset: 0x04F0 size: 32 bit */
  820   
  821           /* Second portion of a DCF record - do not use */
  822           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD78y;/* offset: 0x04F4 size: 32 bit */
  823           int8_t CFLASH_SHADOW_reserved_04F8_I1[8];
  824   
  825           /* First portion of a DCF record - do not use */
  826           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD79x;/* offset: 0x0500 size: 32 bit */
  827   
  828           /* Second portion of a DCF record - do not use */
  829           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD79y;/* offset: 0x0504 size: 32 bit */
  830           int8_t CFLASH_SHADOW_reserved_0508_I1[8];
  831   
  832           /* First portion of a DCF record - do not use */
  833           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD80x;/* offset: 0x0510 size: 32 bit */
  834   
  835           /* Second portion of a DCF record - do not use */
  836           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD80y;/* offset: 0x0514 size: 32 bit */
  837           int8_t CFLASH_SHADOW_reserved_0518_I1[8];
  838   
  839           /* First portion of a DCF record - do not use */
  840           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD81x;/* offset: 0x0520 size: 32 bit */
  841   
  842           /* Second portion of a DCF record - do not use */
  843           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD81y;/* offset: 0x0524 size: 32 bit */
  844           int8_t CFLASH_SHADOW_reserved_0528_I1[8];
  845   
  846           /* First portion of a DCF record - do not use */
  847           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD82x;/* offset: 0x0530 size: 32 bit */
  848   
  849           /* Second portion of a DCF record - do not use */
  850           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD82y;/* offset: 0x0534 size: 32 bit */
  851           int8_t CFLASH_SHADOW_reserved_0538_I1[8];
  852   
  853           /* First portion of a DCF record - do not use */
  854           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD83x;/* offset: 0x0540 size: 32 bit */
  855   
  856           /* Second portion of a DCF record - do not use */
  857           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD83y;/* offset: 0x0544 size: 32 bit */
  858           int8_t CFLASH_SHADOW_reserved_0548_I1[8];
  859   
  860           /* First portion of a DCF record - do not use */
  861           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD84x;/* offset: 0x0550 size: 32 bit */
  862   
  863           /* Second portion of a DCF record - do not use */
  864           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD84y;/* offset: 0x0554 size: 32 bit */
  865           int8_t CFLASH_SHADOW_reserved_0558_I1[8];
  866   
  867           /* First portion of a DCF record - do not use */
  868           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD85x;/* offset: 0x0560 size: 32 bit */
  869   
  870           /* Second portion of a DCF record - do not use */
  871           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD85y;/* offset: 0x0564 size: 32 bit */
  872           int8_t CFLASH_SHADOW_reserved_0568_I1[8];
  873   
  874           /* First portion of a DCF record - do not use */
  875           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD86x;/* offset: 0x0570 size: 32 bit */
  876   
  877           /* Second portion of a DCF record - do not use */
  878           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD86y;/* offset: 0x0574 size: 32 bit */
  879           int8_t CFLASH_SHADOW_reserved_0578_I1[8];
  880   
  881           /* First portion of a DCF record - do not use */
  882           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD87x;/* offset: 0x0580 size: 32 bit */
  883   
  884           /* Second portion of a DCF record - do not use */
  885           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD87y;/* offset: 0x0584 size: 32 bit */
  886           int8_t CFLASH_SHADOW_reserved_0588_I1[8];
  887   
  888           /* First portion of a DCF record - do not use */
  889           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD88x;/* offset: 0x0590 size: 32 bit */
  890   
  891           /* Second portion of a DCF record - do not use */
  892           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD88y;/* offset: 0x0594 size: 32 bit */
  893           int8_t CFLASH_SHADOW_reserved_0598_I1[8];
  894   
  895           /* First portion of a DCF record - do not use */
  896           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD89x;/* offset: 0x05A0 size: 32 bit */
  897   
  898           /* Second portion of a DCF record - do not use */
  899           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD89y;/* offset: 0x05A4 size: 32 bit */
  900           int8_t CFLASH_SHADOW_reserved_05A8_I1[8];
  901   
  902           /* First portion of a DCF record - do not use */
  903           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD90x;/* offset: 0x05B0 size: 32 bit */
  904   
  905           /* Second portion of a DCF record - do not use */
  906           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD90y;/* offset: 0x05B4 size: 32 bit */
  907           int8_t CFLASH_SHADOW_reserved_05B8_I1[8];
  908   
  909           /* First portion of a DCF record - do not use */
  910           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD91x;/* offset: 0x05C0 size: 32 bit */
  911   
  912           /* Second portion of a DCF record - do not use */
  913           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD91y;/* offset: 0x05C4 size: 32 bit */
  914           int8_t CFLASH_SHADOW_reserved_05C8_I1[8];
  915   
  916           /* First portion of a DCF record - do not use */
  917           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD92x;/* offset: 0x05D0 size: 32 bit */
  918   
  919           /* Second portion of a DCF record - do not use */
  920           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD92y;/* offset: 0x05D4 size: 32 bit */
  921           int8_t CFLASH_SHADOW_reserved_05D8_I1[8];
  922   
  923           /* First portion of a DCF record - do not use */
  924           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD93x;/* offset: 0x05E0 size: 32 bit */
  925   
  926           /* Second portion of a DCF record - do not use */
  927           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD93y;/* offset: 0x05E4 size: 32 bit */
  928           int8_t CFLASH_SHADOW_reserved_05E8_I1[8];
  929   
  930           /* First portion of a DCF record - do not use */
  931           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD94x;/* offset: 0x05F0 size: 32 bit */
  932   
  933           /* Second portion of a DCF record - do not use */
  934           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD94y;/* offset: 0x05F4 size: 32 bit */
  935           int8_t CFLASH_SHADOW_reserved_05F8_I1[8];
  936   
  937           /* First portion of a DCF record - do not use */
  938           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD95x;/* offset: 0x0600 size: 32 bit */
  939   
  940           /* Second portion of a DCF record - do not use */
  941           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD95y;/* offset: 0x0604 size: 32 bit */
  942           int8_t CFLASH_SHADOW_reserved_0608_I1[8];
  943   
  944           /* First portion of a DCF record - do not use */
  945           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD96x;/* offset: 0x0610 size: 32 bit */
  946   
  947           /* Second portion of a DCF record - do not use */
  948           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD96y;/* offset: 0x0614 size: 32 bit */
  949           int8_t CFLASH_SHADOW_reserved_0618_I1[8];
  950   
  951           /* First portion of a DCF record - do not use */
  952           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD97x;/* offset: 0x0620 size: 32 bit */
  953   
  954           /* Second portion of a DCF record - do not use */
  955           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD97y;/* offset: 0x0624 size: 32 bit */
  956           int8_t CFLASH_SHADOW_reserved_0628_I1[8];
  957   
  958           /* First portion of a DCF record - do not use */
  959           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD98x;/* offset: 0x0630 size: 32 bit */
  960   
  961           /* Second portion of a DCF record - do not use */
  962           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD98y;/* offset: 0x0634 size: 32 bit */
  963           int8_t CFLASH_SHADOW_reserved_0638_I1[8];
  964   
  965           /* First portion of a DCF record - do not use */
  966           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD99x;/* offset: 0x0640 size: 32 bit */
  967   
  968           /* Second portion of a DCF record - do not use */
  969           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD99y;/* offset: 0x0644 size: 32 bit */
  970           int8_t CFLASH_SHADOW_reserved_0648_I1[8];
  971   
  972           /* First portion of a DCF record - do not use */
  973           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD100x;/* offset: 0x0650 size: 32 bit */
  974   
  975           /* Second portion of a DCF record - do not use */
  976           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD100y;/* offset: 0x0654 size: 32 bit */
  977           int8_t CFLASH_SHADOW_reserved_0658_I1[8];
  978   
  979           /* First portion of a DCF record - do not use */
  980           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD101x;/* offset: 0x0660 size: 32 bit */
  981   
  982           /* Second portion of a DCF record - do not use */
  983           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD101y;/* offset: 0x0664 size: 32 bit */
  984           int8_t CFLASH_SHADOW_reserved_0668_I1[8];
  985   
  986           /* First portion of a DCF record - do not use */
  987           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD102x;/* offset: 0x0670 size: 32 bit */
  988   
  989           /* Second portion of a DCF record - do not use */
  990           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD102y;/* offset: 0x0674 size: 32 bit */
  991           int8_t CFLASH_SHADOW_reserved_0678_I1[8];
  992   
  993           /* First portion of a DCF record - do not use */
  994           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD103x;/* offset: 0x0680 size: 32 bit */
  995   
  996           /* Second portion of a DCF record - do not use */
  997           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD103y;/* offset: 0x0684 size: 32 bit */
  998           int8_t CFLASH_SHADOW_reserved_0688_I1[8];
  999   
 1000           /* First portion of a DCF record - do not use */
 1001           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD104x;/* offset: 0x0690 size: 32 bit */
 1002   
 1003           /* Second portion of a DCF record - do not use */
 1004           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD104y;/* offset: 0x0694 size: 32 bit */
 1005           int8_t CFLASH_SHADOW_reserved_0698_I1[8];
 1006   
 1007           /* First portion of a DCF record - do not use */
 1008           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD105x;/* offset: 0x06A0 size: 32 bit */
 1009   
 1010           /* Second portion of a DCF record - do not use */
 1011           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD105y;/* offset: 0x06A4 size: 32 bit */
 1012           int8_t CFLASH_SHADOW_reserved_06A8_I1[8];
 1013   
 1014           /* First portion of a DCF record - do not use */
 1015           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD106x;/* offset: 0x06B0 size: 32 bit */
 1016   
 1017           /* Second portion of a DCF record - do not use */
 1018           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD106y;/* offset: 0x06B4 size: 32 bit */
 1019           int8_t CFLASH_SHADOW_reserved_06B8_I1[8];
 1020   
 1021           /* First portion of a DCF record - do not use */
 1022           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD107x;/* offset: 0x06C0 size: 32 bit */
 1023   
 1024           /* Second portion of a DCF record - do not use */
 1025           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD107y;/* offset: 0x06C4 size: 32 bit */
 1026           int8_t CFLASH_SHADOW_reserved_06C8_I1[8];
 1027   
 1028           /* First portion of a DCF record - do not use */
 1029           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD108x;/* offset: 0x06D0 size: 32 bit */
 1030   
 1031           /* Second portion of a DCF record - do not use */
 1032           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD108y;/* offset: 0x06D4 size: 32 bit */
 1033           int8_t CFLASH_SHADOW_reserved_06D8_I1[8];
 1034   
 1035           /* First portion of a DCF record - do not use */
 1036           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD109x;/* offset: 0x06E0 size: 32 bit */
 1037   
 1038           /* Second portion of a DCF record - do not use */
 1039           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD109y;/* offset: 0x06E4 size: 32 bit */
 1040           int8_t CFLASH_SHADOW_reserved_06E8_I1[8];
 1041   
 1042           /* First portion of a DCF record - do not use */
 1043           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD110x;/* offset: 0x06F0 size: 32 bit */
 1044   
 1045           /* Second portion of a DCF record - do not use */
 1046           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD110y;/* offset: 0x06F4 size: 32 bit */
 1047           int8_t CFLASH_SHADOW_reserved_06F8_I1[8];
 1048   
 1049           /* First portion of a DCF record - do not use */
 1050           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD111x;/* offset: 0x0700 size: 32 bit */
 1051   
 1052           /* Second portion of a DCF record - do not use */
 1053           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD111y;/* offset: 0x0704 size: 32 bit */
 1054           int8_t CFLASH_SHADOW_reserved_0708_I1[8];
 1055   
 1056           /* First portion of a DCF record - do not use */
 1057           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD112x;/* offset: 0x0710 size: 32 bit */
 1058   
 1059           /* Second portion of a DCF record - do not use */
 1060           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD112y;/* offset: 0x0714 size: 32 bit */
 1061           int8_t CFLASH_SHADOW_reserved_0718_I1[8];
 1062   
 1063           /* First portion of a DCF record - do not use */
 1064           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD113x;/* offset: 0x0720 size: 32 bit */
 1065   
 1066           /* Second portion of a DCF record - do not use */
 1067           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD113y;/* offset: 0x0724 size: 32 bit */
 1068           int8_t CFLASH_SHADOW_reserved_0728_I1[8];
 1069   
 1070           /* First portion of a DCF record - do not use */
 1071           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD114x;/* offset: 0x0730 size: 32 bit */
 1072   
 1073           /* Second portion of a DCF record - do not use */
 1074           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD114y;/* offset: 0x0734 size: 32 bit */
 1075           int8_t CFLASH_SHADOW_reserved_0738_I1[8];
 1076   
 1077           /* First portion of a DCF record - do not use */
 1078           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD115x;/* offset: 0x0740 size: 32 bit */
 1079   
 1080           /* Second portion of a DCF record - do not use */
 1081           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD115y;/* offset: 0x0744 size: 32 bit */
 1082           int8_t CFLASH_SHADOW_reserved_0748_I1[8];
 1083   
 1084           /* First portion of a DCF record - do not use */
 1085           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD116x;/* offset: 0x0750 size: 32 bit */
 1086   
 1087           /* Second portion of a DCF record - do not use */
 1088           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD116y;/* offset: 0x0754 size: 32 bit */
 1089           int8_t CFLASH_SHADOW_reserved_0758_I1[8];
 1090   
 1091           /* First portion of a DCF record - do not use */
 1092           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD117x;/* offset: 0x0760 size: 32 bit */
 1093   
 1094           /* Second portion of a DCF record - do not use */
 1095           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD117y;/* offset: 0x0764 size: 32 bit */
 1096           int8_t CFLASH_SHADOW_reserved_0768_I1[8];
 1097   
 1098           /* First portion of a DCF record - do not use */
 1099           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD118x;/* offset: 0x0770 size: 32 bit */
 1100   
 1101           /* Second portion of a DCF record - do not use */
 1102           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD118y;/* offset: 0x0774 size: 32 bit */
 1103           int8_t CFLASH_SHADOW_reserved_0778_I1[8];
 1104   
 1105           /* First portion of a DCF record - do not use */
 1106           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD119x;/* offset: 0x0780 size: 32 bit */
 1107   
 1108           /* Second portion of a DCF record - do not use */
 1109           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD119y;/* offset: 0x0784 size: 32 bit */
 1110           int8_t CFLASH_SHADOW_reserved_0788_I1[8];
 1111   
 1112           /* First portion of a DCF record - do not use */
 1113           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD120x;/* offset: 0x0790 size: 32 bit */
 1114   
 1115           /* Second portion of a DCF record - do not use */
 1116           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD120y;/* offset: 0x0794 size: 32 bit */
 1117           int8_t CFLASH_SHADOW_reserved_0798_I1[8];
 1118   
 1119           /* First portion of a DCF record - do not use */
 1120           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD121x;/* offset: 0x07A0 size: 32 bit */
 1121   
 1122           /* Second portion of a DCF record - do not use */
 1123           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD121y;/* offset: 0x07A4 size: 32 bit */
 1124           int8_t CFLASH_SHADOW_reserved_07A8_I1[8];
 1125   
 1126           /* First portion of a DCF record - do not use */
 1127           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD122x;/* offset: 0x07B0 size: 32 bit */
 1128   
 1129           /* Second portion of a DCF record - do not use */
 1130           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD122y;/* offset: 0x07B4 size: 32 bit */
 1131           int8_t CFLASH_SHADOW_reserved_07B8_I1[8];
 1132   
 1133           /* First portion of a DCF record - do not use */
 1134           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD123x;/* offset: 0x07C0 size: 32 bit */
 1135   
 1136           /* Second portion of a DCF record - do not use */
 1137           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD123y;/* offset: 0x07C4 size: 32 bit */
 1138           int8_t CFLASH_SHADOW_reserved_07C8_I1[8];
 1139   
 1140           /* First portion of a DCF record - do not use */
 1141           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD124x;/* offset: 0x07D0 size: 32 bit */
 1142   
 1143           /* Second portion of a DCF record - do not use */
 1144           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD124y;/* offset: 0x07D4 size: 32 bit */
 1145           int8_t CFLASH_SHADOW_reserved_07D8_I1[8];
 1146   
 1147           /* First portion of a DCF record - do not use */
 1148           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD125x;/* offset: 0x07E0 size: 32 bit */
 1149   
 1150           /* Second portion of a DCF record - do not use */
 1151           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD125y;/* offset: 0x07E4 size: 32 bit */
 1152           int8_t CFLASH_SHADOW_reserved_07E8_I1[8];
 1153   
 1154           /* First portion of a DCF record - do not use */
 1155           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD126x;/* offset: 0x07F0 size: 32 bit */
 1156   
 1157           /* Second portion of a DCF record - do not use */
 1158           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD126y;/* offset: 0x07F4 size: 32 bit */
 1159           int8_t CFLASH_SHADOW_reserved_07F8_I1[8];
 1160   
 1161           /* First portion of a DCF record - do not use */
 1162           CFLASH_SHADOW_DCF_RECORDx_32B_tag DCF_RECORD127x;/* offset: 0x0800 size: 32 bit */
 1163   
 1164           /* Second portion of a DCF record - do not use */
 1165           CFLASH_SHADOW_DCF_RECORDy_32B_tag DCF_RECORD127y;/* offset: 0x0804 size: 32 bit */
 1166           int8_t CFLASH_SHADOW_reserved_0808_E1[8];
 1167         };
 1168       };
 1169   
 1170       int8_t CFLASH_SHADOW_reserved_0810[13768];
 1171       union {
 1172         /* NVPWD0-1 - Non Volatile Private Censorship PassWorD Register */
 1173         CFLASH_SHADOW_NVPWD_32B_tag NVPWD[2];/* offset: 0x3DD8  (0x0004 x 2) */
 1174         struct {
 1175           /* NVPWD0-1 - Non Volatile Private Censorship PassWorD Register */
 1176           CFLASH_SHADOW_NVPWD_32B_tag NVPWD0;/* offset: 0x3DD8 size: 32 bit */
 1177           CFLASH_SHADOW_NVPWD_32B_tag NVPWD1;/* offset: 0x3DDC size: 32 bit */
 1178         };
 1179       };
 1180   
 1181       union {
 1182         /* NVSCI - Non Volatile System Censoring Information Register */
 1183         CFLASH_SHADOW_NVSCI_32B_tag NVSCI[2];/* offset: 0x3DE0  (0x0004 x 2) */
 1184         struct {
 1185           /* NVSCI - Non Volatile System Censoring Information Register */
 1186           CFLASH_SHADOW_NVSCI_32B_tag NVSCI0;/* offset: 0x3DE0 size: 32 bit */
 1187           CFLASH_SHADOW_NVSCI_32B_tag NVSCI1;/* offset: 0x3DE4 size: 32 bit */
 1188         };
 1189       };
 1190   
 1191       /* Non Volatile LML Default Value */
 1192       CFLASH_SHADOW_NVLML_32B_tag NVLML; /* offset: 0x3DE8 size: 32 bit */
 1193       int8_t CFLASH_SHADOW_reserved_3DEC[4];
 1194   
 1195       /* Non Volatile HBL Default Value */
 1196       CFLASH_SHADOW_NVHBL_32B_tag NVHBL; /* offset: 0x3DF0 size: 32 bit */
 1197       int8_t CFLASH_SHADOW_reserved_3DF4[4];
 1198   
 1199       /* Non Volatile SLL Default Value */
 1200       CFLASH_SHADOW_NVSLL_32B_tag NVSLL; /* offset: 0x3DF8 size: 32 bit */
 1201       int8_t CFLASH_SHADOW_reserved_3DFC[4];
 1202       union {
 1203         /*  Register set BIU_DEFAULTS */
 1204         CFLASH_SHADOW_BIU_DEFAULTS_tag BIU_DEFAULTS[3];/* offset: 0x3E00  (0x0008 x 3) */
 1205         struct {
 1206           /* Non Volatile Bus Interface Unit Register */
 1207           CFLASH_SHADOW_NVBIU_32B_tag NVBIU2;/* offset: 0x3E00 size: 32 bit */
 1208           int8_t CFLASH_SHADOW_reserved_3E04_I1[4];
 1209           CFLASH_SHADOW_NVBIU_32B_tag NVBIU3;/* offset: 0x3E08 size: 32 bit */
 1210           int8_t CFLASH_SHADOW_reserved_3E0C_I1[4];
 1211           CFLASH_SHADOW_NVBIU_32B_tag NVBIU4;/* offset: 0x3E10 size: 32 bit */
 1212           int8_t CFLASH_SHADOW_reserved_3E14_E1[4];
 1213         };
 1214       };
 1215   
 1216       /* NVUSRO - Non Volatile USeR Options Register */
 1217       CFLASH_SHADOW_NVUSRO_32B_tag NVUSRO;/* offset: 0x3E18 size: 32 bit */
 1218       int8_t CFLASH_SHADOW_reserved_3E1C[484];
 1219     } CFLASH_SHADOW_tag;
 1220   
 1221   #define CFLASH_SHADOW                  (*(volatile CFLASH_SHADOW_tag *) 0x00F00000UL)
 1222   
 1223     /****************************************************************/
 1224     /*                                                              */
 1225     /* Module: CFLASH  */
 1226     /*                                                              */
 1227     /****************************************************************/
 1228     typedef union {                      /* MCR - Module Configuration Register */
 1229       vuint32_t R;
 1230       struct {
 1231        vuint32_t:
 1232         5;
 1233         vuint32_t SIZE:3;                /* Array Space Size */
 1234        vuint32_t:
 1235         1;
 1236         vuint32_t LAS:3;                 /* Low Address Space */
 1237        vuint32_t:
 1238         3;
 1239         vuint32_t MAS:1;                 /* Mid Address Space Configuration */
 1240         vuint32_t EER:1;                 /* ECC Event Error */
 1241         vuint32_t RWE:1;                 /* Read-while-Write Event Error */
 1242         vuint32_t SBC:1;                 /* Single Bit Correction */
 1243        vuint32_t:
 1244         1;
 1245         vuint32_t PEAS:1;                /* Program/Erase Access Space */
 1246         vuint32_t DONE:1;                /* modify operation DONE */
 1247         vuint32_t PEG:1;                 /* Program/Erase Good */
 1248        vuint32_t:
 1249         4;
 1250         vuint32_t PGM:1;                 /* Program Bit */
 1251         vuint32_t PSUS:1;                /* Program Suspend */
 1252         vuint32_t ERS:1;                 /* Erase Bit */
 1253         vuint32_t ESUS:1;                /* Erase Suspend */
 1254         vuint32_t EHV:1;                 /* Enable High Voltage */
 1255       } B;
 1256     } CFLASH_MCR_32B_tag;
 1257   
 1258     typedef union {                      /* LML - Low/Mid Address Space Block Locking Register */
 1259       vuint32_t R;
 1260       struct {
 1261         vuint32_t LME:1;                 /* Low/Mid Address Space Block Enable */
 1262        vuint32_t:
 1263         10;
 1264   
 1265   #ifndef USE_FIELD_ALIASES_CFLASH
 1266   
 1267         vuint32_t SLOCK:1;               /* Shadow Address Space Block Lock */
 1268   
 1269   #else
 1270   
 1271         vuint32_t TSLK:1;                /* deprecated name - please avoid */
 1272   
 1273   #endif
 1274   
 1275        vuint32_t:
 1276         2;
 1277   
 1278   #ifndef USE_FIELD_ALIASES_CFLASH
 1279   
 1280         vuint32_t MLOCK:2;               /* Mid Address Space Block Lock */
 1281   
 1282   #else
 1283   
 1284         vuint32_t MLK:2;                 /* deprecated name - please avoid */
 1285   
 1286   #endif
 1287   
 1288        vuint32_t:
 1289         6;
 1290         vuint32_t LLOCK:10;              /* Low Address Space Block Lock */
 1291       } B;
 1292     } CFLASH_LML_32B_tag;
 1293   
 1294     typedef union {                      /* HBL - High Address Space Block Locking Register */
 1295       vuint32_t R;
 1296       struct {
 1297         vuint32_t HBE:1;                 /* High Address Space Block Enable */
 1298        vuint32_t:
 1299         21;
 1300         vuint32_t HLOCK:10;              /* High Address Space Block Lock */
 1301       } B;
 1302     } CFLASH_HBL_32B_tag;
 1303   
 1304     typedef union {                      /* SLL - Secondary Low/Mid Address Space Block Locking Register */
 1305       vuint32_t R;
 1306       struct {
 1307         vuint32_t SLE:1;                 /* Secondary Low/Mid Address Space Block Enable */
 1308        vuint32_t:
 1309         10;
 1310   
 1311   #ifndef USE_FIELD_ALIASES_CFLASH
 1312   
 1313         vuint32_t SSLOCK:1;              /* Secondary Shadow Address Space Block Lock */
 1314   
 1315   #else
 1316   
 1317         vuint32_t STSLK:1;               /* deprecated name - please avoid */
 1318   
 1319   #endif
 1320   
 1321        vuint32_t:
 1322         2;
 1323   
 1324   #ifndef USE_FIELD_ALIASES_CFLASH
 1325   
 1326         vuint32_t SMLOCK:2;              /* Secondary Mid Address Space Block Lock */
 1327   
 1328   #else
 1329   
 1330         vuint32_t SMK:2;                 /* deprecated name - please avoid */
 1331   
 1332   #endif
 1333   
 1334        vuint32_t:
 1335         6;
 1336         vuint32_t SLLOCK:10;             /* Secondary Low Address Space Block Lock */
 1337       } B;
 1338     } CFLASH_SLL_32B_tag;
 1339   
 1340     typedef union {                      /* LMS - Low/Mid Address Space Block Select Register */
 1341       vuint32_t R;
 1342       struct {
 1343        vuint32_t:
 1344         14;
 1345         vuint32_t MSL:2;                 /* Mid Address Space Block Select */
 1346        vuint32_t:
 1347         6;
 1348         vuint32_t LSL:10;                /* Low Address Space Block Select */
 1349       } B;
 1350     } CFLASH_LMS_32B_tag;
 1351   
 1352     typedef union {                      /* HBS - High Address Space Block Select Register */
 1353       vuint32_t R;
 1354       struct {
 1355        vuint32_t:
 1356         22;
 1357         vuint32_t HSL:10;                /* High Address Space Block Select */
 1358       } B;
 1359     } CFLASH_HBS_32B_tag;
 1360   
 1361     typedef union {                      /* ADR - Address Register */
 1362       vuint32_t R;
 1363       struct {
 1364         vuint32_t SAD:1;                 /* Shadow Address */
 1365        vuint32_t:
 1366         10;
 1367         vuint32_t ADDR:18;               /* Address */
 1368        vuint32_t:
 1369         3;
 1370       } B;
 1371     } CFLASH_ADR_32B_tag;
 1372   
 1373     typedef union {                      /* PFLASH2P_LCA_PFCR0 - Platform Flash Configuration Register 0 */
 1374       vuint32_t R;
 1375       struct {
 1376   
 1377   #ifndef USE_FIELD_ALIASES_CFLASH
 1378   
 1379         vuint32_t B02_APC:5;             /* Bank0+2 Address Pipelining Control */
 1380   
 1381   #else
 1382   
 1383         vuint32_t BK0_APC:5;             /* deprecated name - please avoid */
 1384   
 1385   #endif
 1386   
 1387   #ifndef USE_FIELD_ALIASES_CFLASH
 1388   
 1389         vuint32_t B02_WWSC:5;            /* Bank0+2 Write Wait State Control */
 1390   
 1391   #else
 1392   
 1393         vuint32_t BK0_WWSC:5;            /* deprecated name - please avoid */
 1394   
 1395   #endif
 1396   
 1397   #ifndef USE_FIELD_ALIASES_CFLASH
 1398   
 1399         vuint32_t B02_RWSC:5;            /* Bank0+2 Read Wait State Control */
 1400   
 1401   #else
 1402   
 1403         vuint32_t BK0_RWSC:5;            /* deprecated name - please avoid */
 1404   
 1405   #endif
 1406   
 1407   #ifndef USE_FIELD_ALIASES_CFLASH
 1408   
 1409         vuint32_t B02_RWWC2:1;           /* Bank 0+2 Read While Write Control, bit 2 */
 1410   
 1411   #else
 1412   
 1413         vuint32_t BK0_RWWC2:1;           /* deprecated name - please avoid */
 1414   
 1415   #endif
 1416   
 1417   #ifndef USE_FIELD_ALIASES_CFLASH
 1418   
 1419         vuint32_t B02_RWWC1:1;           /* Bank 0+2 Read While Write Control, bit 1 */
 1420   
 1421   #else
 1422   
 1423         vuint32_t BK0_RWWC1:1;           /* deprecated name - please avoid */
 1424   
 1425   #endif
 1426   
 1427   #ifndef USE_FIELD_ALIASES_CFLASH
 1428   
 1429         vuint32_t B02_P1_BCFG:2;         /* Bank0+2 Port 1 Page Buffer Configuration */
 1430   
 1431   #else
 1432   
 1433         vuint32_t B0_P1_BCFG:2;          /* deprecated name - please avoid */
 1434   
 1435   #endif
 1436   
 1437   #ifndef USE_FIELD_ALIASES_CFLASH
 1438   
 1439         vuint32_t B02_P1_DPFE:1;         /* Bank0+2 Port 1 Data Prefetch Enable */
 1440   
 1441   #else
 1442   
 1443         vuint32_t B0_P1_DPFE:1;          /* deprecated name - please avoid */
 1444   
 1445   #endif
 1446   
 1447   #ifndef USE_FIELD_ALIASES_CFLASH
 1448   
 1449         vuint32_t B02_P1_IPFE:1;         /* Bank0+2 Port 1 Inst Prefetch Enable */
 1450   
 1451   #else
 1452   
 1453         vuint32_t B0_P1_IPFE:1;          /* deprecated name - please avoid */
 1454   
 1455   #endif
 1456   
 1457   #ifndef USE_FIELD_ALIASES_CFLASH
 1458   
 1459         vuint32_t B02_P1_PFLM:2;         /* Bank0+2 Port 1 Prefetch Limit */
 1460   
 1461   #else
 1462   
 1463         vuint32_t B0_P1_PFLM:2;          /* deprecated name - please avoid */
 1464   
 1465   #endif
 1466   
 1467   #ifndef USE_FIELD_ALIASES_CFLASH
 1468   
 1469         vuint32_t B02_P1_BFE:1;          /* Bank0+2 Port 1 Buffer Enable */
 1470   
 1471   #else
 1472   
 1473         vuint32_t B0_P1_BFE:1;           /* deprecated name - please avoid */
 1474   
 1475   #endif
 1476   
 1477   #ifndef USE_FIELD_ALIASES_CFLASH
 1478   
 1479         vuint32_t B02_RWWC0:1;           /* Bank 0+2 Read While Write Control, bit 0 */
 1480   
 1481   #else
 1482   
 1483         vuint32_t BK0_RWWC0:1;           /* deprecated name - please avoid */
 1484   
 1485   #endif
 1486   
 1487   #ifndef USE_FIELD_ALIASES_CFLASH
 1488   
 1489         vuint32_t B02_P0_BCFG:2;         /* Bank0+2 Port 0 Page Buffer Configuration */
 1490   
 1491   #else
 1492   
 1493         vuint32_t B0_P0_BCFG:2;          /* deprecated name - please avoid */
 1494   
 1495   #endif
 1496   
 1497   #ifndef USE_FIELD_ALIASES_CFLASH
 1498   
 1499         vuint32_t B02_P0_DPFE:1;         /* Bank0+2 Port 0 Data Prefetch Enable */
 1500   
 1501   #else
 1502   
 1503         vuint32_t B0_P0_DPFE:1;          /* deprecated name - please avoid */
 1504   
 1505   #endif
 1506   
 1507   #ifndef USE_FIELD_ALIASES_CFLASH
 1508   
 1509         vuint32_t B02_P0_IPFE:1;         /* Bank0+2 Port 0 Inst Prefetch Enable */
 1510   
 1511   #else
 1512   
 1513         vuint32_t B0_P0_IPFE:1;          /* deprecated name - please avoid */
 1514   
 1515   #endif
 1516   
 1517   #ifndef USE_FIELD_ALIASES_CFLASH
 1518   
 1519         vuint32_t B02_P0_PFLM:2;         /* Bank0+2 Port 0 Prefetch Limit */
 1520   
 1521   #else
 1522   
 1523         vuint32_t B0_P0_PFLM:2;          /* deprecated name - please avoid */
 1524   
 1525   #endif
 1526   
 1527   #ifndef USE_FIELD_ALIASES_CFLASH
 1528   
 1529         vuint32_t B02_P0_BFE:1;          /* Bank0+2 Port 0 Buffer Enable */
 1530   
 1531   #else
 1532   
 1533         vuint32_t B0_P0_BFE:1;           /* deprecated name - please avoid */
 1534   
 1535   #endif
 1536   
 1537       } B;
 1538     } CFLASH_PFCR0_32B_tag;
 1539   
 1540     /* Register layout for all registers BIU ... */
 1541     typedef union {                      /* Bus Interface Unit Register */
 1542       vuint32_t R;
 1543     } CFLASH_BIU_32B_tag;
 1544   
 1545     typedef union {                      /* PFLASH2P_LCA_PFCR1 - Platform Flash Configuration Register 1 */
 1546       vuint32_t R;
 1547       struct {
 1548   
 1549   #ifndef USE_FIELD_ALIASES_CFLASH
 1550   
 1551         vuint32_t B1_APC:5;              /* Bank 1 Address Pipelining Control */
 1552   
 1553   #else
 1554   
 1555         vuint32_t BK1_APC:5;             /* deprecated name - please avoid */
 1556   
 1557   #endif
 1558   
 1559   #ifndef USE_FIELD_ALIASES_CFLASH
 1560   
 1561         vuint32_t B1_WWSC:5;             /* Bank 1 Write Wait State Control */
 1562   
 1563   #else
 1564   
 1565         vuint32_t BK1_WWSC:5;            /* deprecated name - please avoid */
 1566   
 1567   #endif
 1568   
 1569   #ifndef USE_FIELD_ALIASES_CFLASH
 1570   
 1571         vuint32_t B1_RWSC:5;             /* Bank 1 Read Wait State Control */
 1572   
 1573   #else
 1574   
 1575         vuint32_t BK1_RWSC:5;            /* deprecated name - please avoid */
 1576   
 1577   #endif
 1578   
 1579   #ifndef USE_FIELD_ALIASES_CFLASH
 1580   
 1581         vuint32_t B1_RWWC2:1;            /* Bank1 Read While Write Control, bit 2 */
 1582   
 1583   #else
 1584   
 1585         vuint32_t BK1_RWWC2:1;           /* deprecated name - please avoid */
 1586   
 1587   #endif
 1588   
 1589   #ifndef USE_FIELD_ALIASES_CFLASH
 1590   
 1591         vuint32_t B1_RWWC1:1;            /* Bank1 Read While Write Control, bit 1 */
 1592   
 1593   #else
 1594   
 1595         vuint32_t BK1_RWWC1:1;           /* deprecated name - please avoid */
 1596   
 1597   #endif
 1598   
 1599        vuint32_t:
 1600         6;
 1601   
 1602   #ifndef USE_FIELD_ALIASES_CFLASH
 1603   
 1604         vuint32_t B1_P1_BFE:1;           /* Bank 1 Port 1 Buffer Enable */
 1605   
 1606   #else
 1607   
 1608         vuint32_t B0_P1_BFE:1;           /* deprecated name - please avoid */
 1609   
 1610   #endif
 1611   
 1612   #ifndef USE_FIELD_ALIASES_CFLASH
 1613   
 1614         vuint32_t B1_RWWC0:1;            /* Bank1 Read While Write Control, bit 0 */
 1615   
 1616   #else
 1617   
 1618         vuint32_t BK1_RWWC0:1;           /* deprecated name - please avoid */
 1619   
 1620   #endif
 1621   
 1622        vuint32_t:
 1623         6;
 1624         vuint32_t B1_P0_BFE:1;           /* Bank 1 Port 0 Buffer Enable */
 1625       } B;
 1626     } CFLASH_PFCR1_32B_tag;
 1627   
 1628     typedef union {                      /* PFLASH2P_LCA_PFAPR - Platform Flash Access Protection Register */
 1629       vuint32_t R;
 1630       struct {
 1631        vuint32_t:
 1632         6;
 1633         vuint32_t ARBM:2;                /* Arbitration Mode */
 1634         vuint32_t M7PFD:1;               /* Master x Prefetch Disable */
 1635         vuint32_t M6PFD:1;               /* Master x Prefetch Disable */
 1636         vuint32_t M5PFD:1;               /* Master x Prefetch Disable */
 1637         vuint32_t M4PFD:1;               /* Master x Prefetch Disable */
 1638         vuint32_t M3PFD:1;               /* Master x Prefetch Disable */
 1639         vuint32_t M2PFD:1;               /* Master x Prefetch Disable */
 1640         vuint32_t M1PFD:1;               /* Master x Prefetch Disable */
 1641         vuint32_t M0PFD:1;               /* Master x Prefetch Disable */
 1642         vuint32_t M7AP:2;                /* Master 7 Access Protection */
 1643         vuint32_t M6AP:2;                /* Master 6 Access Protection */
 1644         vuint32_t M5AP:2;                /* Master 5 Access Protection */
 1645         vuint32_t M4AP:2;                /* Master 4 Access Protection */
 1646         vuint32_t M3AP:2;                /* Master 3 Access Protection */
 1647         vuint32_t M2AP:2;                /* Master 2 Access Protection */
 1648         vuint32_t M1AP:2;                /* Master 1 Access Protection */
 1649         vuint32_t M0AP:2;                /* Master 0 Access Protection */
 1650       } B;
 1651     } CFLASH_PFAPR_32B_tag;
 1652   
 1653     typedef union {                      /* UT0 - User Test Register */
 1654       vuint32_t R;
 1655       struct {
 1656         vuint32_t UTE:1;                 /* User Test Enable */
 1657         vuint32_t SBCE:1;                /* Single Bit Correction Enable */
 1658        vuint32_t:
 1659         6;
 1660         vuint32_t DSI:8;                 /* Data Syndrome Input */
 1661        vuint32_t:
 1662         10;
 1663         vuint32_t MRE:1;                 /* Margin Read Enable */
 1664         vuint32_t MRV:1;                 /* Margin Read Value */
 1665         vuint32_t EIE:1;                 /* ECC Data Input Enable */
 1666         vuint32_t AIS:1;                 /* Array Integrity Sequence */
 1667         vuint32_t AIE:1;                 /* Array Integrity Enable */
 1668         vuint32_t AID:1;                 /* Array Integrity Done */
 1669       } B;
 1670     } CFLASH_UT0_32B_tag;
 1671   
 1672     typedef union {                      /* UT1 - User Test Register */
 1673       vuint32_t R;
 1674     } CFLASH_UT1_32B_tag;
 1675   
 1676     typedef union {                      /* UT2 - User Test Register */
 1677       vuint32_t R;
 1678     } CFLASH_UT2_32B_tag;
 1679   
 1680     /* Register layout for all registers UM ... */
 1681     typedef union {                      /* UM - User Multiple Input Signature Register */
 1682       vuint32_t R;
 1683       struct {
 1684   
 1685   #ifndef USE_FIELD_ALIASES_CFLASH
 1686   
 1687         vuint32_t MISR:32;               /* Multiple Input Signature */
 1688   
 1689   #else
 1690   
 1691         vuint32_t MS:32;                 /* deprecated name - please avoid */
 1692   
 1693   #endif
 1694   
 1695       } B;
 1696     } CFLASH_UM_32B_tag;
 1697   
 1698     /* Register layout for generated register(s) UT... */
 1699     typedef union {                      /*  */
 1700       vuint32_t R;
 1701     } CFLASH_UT_32B_tag;
 1702   
 1703     /* Register layout for generated register(s) PFCR... */
 1704     typedef union {                      /*  */
 1705       vuint32_t R;
 1706     } CFLASH_PFCR_32B_tag;
 1707   
 1708     typedef struct CFLASH_struct_tag {
 1709       /* MCR - Module Configuration Register */
 1710       CFLASH_MCR_32B_tag MCR;            /* offset: 0x0000 size: 32 bit */
 1711   
 1712       /* LML - Low/Mid Address Space Block Locking Register */
 1713       CFLASH_LML_32B_tag LML;            /* offset: 0x0004 size: 32 bit */
 1714   
 1715       /* HBL - High Address Space Block Locking Register */
 1716       CFLASH_HBL_32B_tag HBL;            /* offset: 0x0008 size: 32 bit */
 1717   
 1718       /* SLL - Secondary Low/Mid Address Space Block Locking Register */
 1719       CFLASH_SLL_32B_tag SLL;            /* offset: 0x000C size: 32 bit */
 1720   
 1721       /* LMS - Low/Mid Address Space Block Select Register */
 1722       CFLASH_LMS_32B_tag LMS;            /* offset: 0x0010 size: 32 bit */
 1723   
 1724       /* HBS - High Address Space Block Select Register */
 1725       CFLASH_HBS_32B_tag HBS;            /* offset: 0x0014 size: 32 bit */
 1726   
 1727       /* ADR - Address Register */
 1728       CFLASH_ADR_32B_tag ADR;            /* offset: 0x0018 size: 32 bit */
 1729       union {
 1730         struct {
 1731           CFLASH_PFCR_32B_tag PFCR[2];   /* offset: 0x001C  (0x0004 x 2) */
 1732           int8_t CFLASH_reserved_0024_E0[12];
 1733         };
 1734   
 1735         /* Bus Interface Unit Register */
 1736         CFLASH_BIU_32B_tag BIU[5];       /* offset: 0x001C  (0x0004 x 5) */
 1737         struct {
 1738           /* Bus Interface Unit Register */
 1739           CFLASH_BIU_32B_tag BIU0;       /* offset: 0x001C size: 32 bit */
 1740           CFLASH_BIU_32B_tag BIU1;       /* offset: 0x0020 size: 32 bit */
 1741           CFLASH_BIU_32B_tag BIU2;       /* offset: 0x0024 size: 32 bit */
 1742           CFLASH_BIU_32B_tag BIU3;       /* offset: 0x0028 size: 32 bit */
 1743           CFLASH_BIU_32B_tag BIU4;       /* offset: 0x002C size: 32 bit */
 1744         };
 1745   
 1746         struct {
 1747           /* PFLASH2P_LCA_PFCR0 - Platform Flash Configuration Register 0 */
 1748           CFLASH_PFCR0_32B_tag PFCR0;    /* offset: 0x001C size: 32 bit */
 1749   
 1750           /* PFLASH2P_LCA_PFCR1 - Platform Flash Configuration Register 1 */
 1751           CFLASH_PFCR1_32B_tag PFCR1;    /* offset: 0x0020 size: 32 bit */
 1752   
 1753           /* PFLASH2P_LCA_PFAPR - Platform Flash Access Protection Register */
 1754           CFLASH_PFAPR_32B_tag PFAPR;    /* offset: 0x0024 size: 32 bit */
 1755           int8_t CFLASH_reserved_0028_E3[8];
 1756         };
 1757   
 1758         struct {
 1759           int8_t CFLASH_reserved_001C_I4[8];
 1760           CFLASH_PFAPR_32B_tag FAPR;     /* deprecated - please avoid */
 1761           int8_t CFLASH_reserved_0028_E4[8];
 1762         };
 1763       };
 1764   
 1765       int8_t CFLASH_reserved_0030[12];
 1766       union {
 1767         CFLASH_UT_32B_tag UT[3];         /* offset: 0x003C  (0x0004 x 3) */
 1768         struct {
 1769           /* UT0 - User Test Register */
 1770           CFLASH_UT0_32B_tag UT0;        /* offset: 0x003C size: 32 bit */
 1771   
 1772           /* UT1 - User Test Register */
 1773           CFLASH_UT1_32B_tag UT1;        /* offset: 0x0040 size: 32 bit */
 1774   
 1775           /* UT2 - User Test Register */
 1776           CFLASH_UT2_32B_tag UT2;        /* offset: 0x0044 size: 32 bit */
 1777         };
 1778       };
 1779   
 1780       union {
 1781         CFLASH_UM_32B_tag UMISR[5];      /* offset: 0x0048  (0x0004 x 5) */
 1782   
 1783         /* UM - User Multiple Input Signature Register */
 1784         CFLASH_UM_32B_tag UM[5];         /* offset: 0x0048  (0x0004 x 5) */
 1785         struct {
 1786           /* UM - User Multiple Input Signature Register */
 1787           CFLASH_UM_32B_tag UM0;         /* offset: 0x0048 size: 32 bit */
 1788           CFLASH_UM_32B_tag UM1;         /* offset: 0x004C size: 32 bit */
 1789           CFLASH_UM_32B_tag UM2;         /* offset: 0x0050 size: 32 bit */
 1790           CFLASH_UM_32B_tag UM3;         /* offset: 0x0054 size: 32 bit */
 1791           CFLASH_UM_32B_tag UM4;         /* offset: 0x0058 size: 32 bit */
 1792         };
 1793       };
 1794   
 1795       int8_t CFLASH_reserved_005C[16292];
 1796     } CFLASH_tag;
 1797   
 1798   #define CFLASH                         (*(volatile CFLASH_tag *) 0xC3F88000UL)
 1799   
 1800     /****************************************************************/
 1801     /*                                                              */
 1802     /* Module: SIUL  */
 1803     /*                                                              */
 1804     /****************************************************************/
 1805     typedef union {                      /* MIDR1 - MCU ID Register #1 */
 1806       vuint32_t R;
 1807       struct {
 1808         vuint32_t PARTNUM:16;            /* MCU Part Number */
 1809         vuint32_t CSP:1;                 /* CSP Package */
 1810         vuint32_t PKG:5;                 /* Package Settings */
 1811        vuint32_t:
 1812         2;
 1813   
 1814   #ifndef USE_FIELD_ALIASES_SIUL
 1815   
 1816         vuint32_t MAJOR_MASK:4;          /* Major Mask Revision */
 1817   
 1818   #else
 1819   
 1820         vuint32_t MAJORMASK:4;           /* deprecated name - please avoid */
 1821   
 1822   #endif
 1823   
 1824   #ifndef USE_FIELD_ALIASES_SIUL
 1825   
 1826         vuint32_t MINOR_MASK:4;          /* Minor Mask Revision */
 1827   
 1828   #else
 1829   
 1830         vuint32_t MINORMASK:4;           /* deprecated name - please avoid */
 1831   
 1832   #endif
 1833   
 1834       } B;
 1835     } SIUL_MIDR1_32B_tag;
 1836   
 1837     typedef union {                      /* MIDR2 - MCU ID Register #2 */
 1838       vuint32_t R;
 1839       struct {
 1840         vuint32_t SF:1;                  /* Manufacturer */
 1841         vuint32_t FLASH_SIZE_1:4;        /* Coarse Flash Memory Size */
 1842         vuint32_t FLASH_SIZE_2:4;        /* Fine Flash Memory Size */
 1843        vuint32_t:
 1844         7;
 1845   
 1846   #ifndef USE_FIELD_ALIASES_SIUL
 1847   
 1848         vuint32_t PARTNUM2:8;            /* MCU Part Number */
 1849   
 1850   #else
 1851   
 1852         vuint32_t PARTNUM:8;             /* deprecated name - please avoid */
 1853   
 1854   #endif
 1855   
 1856         vuint32_t TBD:1;                 /* Optional Bit */
 1857        vuint32_t:
 1858         2;
 1859         vuint32_t EE:1;                  /* Data Flash Present */
 1860        vuint32_t:
 1861         3;
 1862         vuint32_t FR:1;                  /* Flexray Present */
 1863       } B;
 1864     } SIUL_MIDR2_32B_tag;
 1865   
 1866     typedef union {                      /* ISR - Interrupt Status Flag Register */
 1867       vuint32_t R;
 1868       struct {
 1869         vuint32_t EIF31:1;               /* External Interrupt Status Flag */
 1870         vuint32_t EIF30:1;               /* External Interrupt Status Flag */
 1871         vuint32_t EIF29:1;               /* External Interrupt Status Flag */
 1872         vuint32_t EIF28:1;               /* External Interrupt Status Flag */
 1873         vuint32_t EIF27:1;               /* External Interrupt Status Flag */
 1874         vuint32_t EIF26:1;               /* External Interrupt Status Flag */
 1875         vuint32_t EIF25:1;               /* External Interrupt Status Flag */
 1876         vuint32_t EIF24:1;               /* External Interrupt Status Flag */
 1877         vuint32_t EIF23:1;               /* External Interrupt Status Flag */
 1878         vuint32_t EIF22:1;               /* External Interrupt Status Flag */
 1879         vuint32_t EIF21:1;               /* External Interrupt Status Flag */
 1880         vuint32_t EIF20:1;               /* External Interrupt Status Flag */
 1881         vuint32_t EIF19:1;               /* External Interrupt Status Flag */
 1882         vuint32_t EIF18:1;               /* External Interrupt Status Flag */
 1883         vuint32_t EIF17:1;               /* External Interrupt Status Flag */
 1884         vuint32_t EIF16:1;               /* External Interrupt Status Flag */
 1885         vuint32_t EIF15:1;               /* External Interrupt Status Flag */
 1886         vuint32_t EIF14:1;               /* External Interrupt Status Flag */
 1887         vuint32_t EIF13:1;               /* External Interrupt Status Flag */
 1888         vuint32_t EIF12:1;               /* External Interrupt Status Flag */
 1889         vuint32_t EIF11:1;               /* External Interrupt Status Flag */
 1890         vuint32_t EIF10:1;               /* External Interrupt Status Flag */
 1891         vuint32_t EIF9:1;                /* External Interrupt Status Flag */
 1892         vuint32_t EIF8:1;                /* External Interrupt Status Flag */
 1893         vuint32_t EIF7:1;                /* External Interrupt Status Flag */
 1894         vuint32_t EIF6:1;                /* External Interrupt Status Flag */
 1895         vuint32_t EIF5:1;                /* External Interrupt Status Flag */
 1896         vuint32_t EIF4:1;                /* External Interrupt Status Flag */
 1897         vuint32_t EIF3:1;                /* External Interrupt Status Flag */
 1898         vuint32_t EIF2:1;                /* External Interrupt Status Flag */
 1899         vuint32_t EIF1:1;                /* External Interrupt Status Flag */
 1900         vuint32_t EIF0:1;                /* External Interrupt Status Flag */
 1901       } B;
 1902     } SIUL_ISR_32B_tag;
 1903   
 1904     typedef union {                      /* IRER - Interrupt Request Enable Register */
 1905       vuint32_t R;
 1906       struct {
 1907         vuint32_t EIRE31:1;              /* Enable External Interrupt Requests */
 1908         vuint32_t EIRE30:1;              /* Enable External Interrupt Requests */
 1909         vuint32_t EIRE29:1;              /* Enable External Interrupt Requests */
 1910         vuint32_t EIRE28:1;              /* Enable External Interrupt Requests */
 1911         vuint32_t EIRE27:1;              /* Enable External Interrupt Requests */
 1912         vuint32_t EIRE26:1;              /* Enable External Interrupt Requests */
 1913         vuint32_t EIRE25:1;              /* Enable External Interrupt Requests */
 1914         vuint32_t EIRE24:1;              /* Enable External Interrupt Requests */
 1915         vuint32_t EIRE23:1;              /* Enable External Interrupt Requests */
 1916         vuint32_t EIRE22:1;              /* Enable External Interrupt Requests */
 1917         vuint32_t EIRE21:1;              /* Enable External Interrupt Requests */
 1918         vuint32_t EIRE20:1;              /* Enable External Interrupt Requests */
 1919         vuint32_t EIRE19:1;              /* Enable External Interrupt Requests */
 1920         vuint32_t EIRE18:1;              /* Enable External Interrupt Requests */
 1921         vuint32_t EIRE17:1;              /* Enable External Interrupt Requests */
 1922         vuint32_t EIRE16:1;              /* Enable External Interrupt Requests */
 1923         vuint32_t EIRE15:1;              /* Enable External Interrupt Requests */
 1924         vuint32_t EIRE14:1;              /* Enable External Interrupt Requests */
 1925         vuint32_t EIRE13:1;              /* Enable External Interrupt Requests */
 1926         vuint32_t EIRE12:1;              /* Enable External Interrupt Requests */
 1927         vuint32_t EIRE11:1;              /* Enable External Interrupt Requests */
 1928         vuint32_t EIRE10:1;              /* Enable External Interrupt Requests */
 1929         vuint32_t EIRE9:1;               /* Enable External Interrupt Requests */
 1930         vuint32_t EIRE8:1;               /* Enable External Interrupt Requests */
 1931         vuint32_t EIRE7:1;               /* Enable External Interrupt Requests */
 1932         vuint32_t EIRE6:1;               /* Enable External Interrupt Requests */
 1933         vuint32_t EIRE5:1;               /* Enable External Interrupt Requests */
 1934         vuint32_t EIRE4:1;               /* Enable External Interrupt Requests */
 1935         vuint32_t EIRE3:1;               /* Enable External Interrupt Requests */
 1936         vuint32_t EIRE2:1;               /* Enable External Interrupt Requests */
 1937         vuint32_t EIRE1:1;               /* Enable External Interrupt Requests */
 1938         vuint32_t EIRE0:1;               /* Enable External Interrupt Requests */
 1939       } B;
 1940     } SIUL_IRER_32B_tag;
 1941   
 1942     typedef union {                      /* IREER - Interrupt Rising Edge Event Enable */
 1943       vuint32_t R;
 1944       struct {
 1945         vuint32_t IREE31:1;              /* Enable rising-edge events */
 1946         vuint32_t IREE30:1;              /* Enable rising-edge events */
 1947         vuint32_t IREE29:1;              /* Enable rising-edge events */
 1948         vuint32_t IREE28:1;              /* Enable rising-edge events */
 1949         vuint32_t IREE27:1;              /* Enable rising-edge events */
 1950         vuint32_t IREE26:1;              /* Enable rising-edge events */
 1951         vuint32_t IREE25:1;              /* Enable rising-edge events */
 1952         vuint32_t IREE24:1;              /* Enable rising-edge events */
 1953         vuint32_t IREE23:1;              /* Enable rising-edge events */
 1954         vuint32_t IREE22:1;              /* Enable rising-edge events */
 1955         vuint32_t IREE21:1;              /* Enable rising-edge events */
 1956         vuint32_t IREE20:1;              /* Enable rising-edge events */
 1957         vuint32_t IREE19:1;              /* Enable rising-edge events */
 1958         vuint32_t IREE18:1;              /* Enable rising-edge events */
 1959         vuint32_t IREE17:1;              /* Enable rising-edge events */
 1960         vuint32_t IREE16:1;              /* Enable rising-edge events */
 1961         vuint32_t IREE15:1;              /* Enable rising-edge events */
 1962         vuint32_t IREE14:1;              /* Enable rising-edge events */
 1963         vuint32_t IREE13:1;              /* Enable rising-edge events */
 1964         vuint32_t IREE12:1;              /* Enable rising-edge events */
 1965         vuint32_t IREE11:1;              /* Enable rising-edge events */
 1966         vuint32_t IREE10:1;              /* Enable rising-edge events */
 1967         vuint32_t IREE9:1;               /* Enable rising-edge events */
 1968         vuint32_t IREE8:1;               /* Enable rising-edge events */
 1969         vuint32_t IREE7:1;               /* Enable rising-edge events */
 1970         vuint32_t IREE6:1;               /* Enable rising-edge events */
 1971         vuint32_t IREE5:1;               /* Enable rising-edge events */
 1972         vuint32_t IREE4:1;               /* Enable rising-edge events */
 1973         vuint32_t IREE3:1;               /* Enable rising-edge events */
 1974         vuint32_t IREE2:1;               /* Enable rising-edge events */
 1975         vuint32_t IREE1:1;               /* Enable rising-edge events */
 1976         vuint32_t IREE0:1;               /* Enable rising-edge events */
 1977       } B;
 1978     } SIUL_IREER_32B_tag;
 1979   
 1980     typedef union {                      /* IFEER - Interrupt Falling-Edge Event Enable */
 1981       vuint32_t R;
 1982       struct {
 1983         vuint32_t IFEE31:1;              /* Enable Falling Edge Events */
 1984         vuint32_t IFEE30:1;              /* Enable Falling Edge Events */
 1985         vuint32_t IFEE29:1;              /* Enable Falling Edge Events */
 1986         vuint32_t IFEE28:1;              /* Enable Falling Edge Events */
 1987         vuint32_t IFEE27:1;              /* Enable Falling Edge Events */
 1988         vuint32_t IFEE26:1;              /* Enable Falling Edge Events */
 1989         vuint32_t IFEE25:1;              /* Enable Falling Edge Events */
 1990         vuint32_t IFEE24:1;              /* Enable Falling Edge Events */
 1991         vuint32_t IFEE23:1;              /* Enable Falling Edge Events */
 1992         vuint32_t IFEE22:1;              /* Enable Falling Edge Events */
 1993         vuint32_t IFEE21:1;              /* Enable Falling Edge Events */
 1994         vuint32_t IFEE20:1;              /* Enable Falling Edge Events */
 1995         vuint32_t IFEE19:1;              /* Enable Falling Edge Events */
 1996         vuint32_t IFEE18:1;              /* Enable Falling Edge Events */
 1997         vuint32_t IFEE17:1;              /* Enable Falling Edge Events */
 1998         vuint32_t IFEE16:1;              /* Enable Falling Edge Events */
 1999         vuint32_t IFEE15:1;              /* Enable Falling Edge Events */
 2000         vuint32_t IFEE14:1;              /* Enable Falling Edge Events */
 2001         vuint32_t IFEE13:1;              /* Enable Falling Edge Events */
 2002         vuint32_t IFEE12:1;              /* Enable Falling Edge Events */
 2003         vuint32_t IFEE11:1;              /* Enable Falling Edge Events */
 2004         vuint32_t IFEE10:1;              /* Enable Falling Edge Events */
 2005         vuint32_t IFEE9:1;               /* Enable Falling Edge Events */
 2006         vuint32_t IFEE8:1;               /* Enable Falling Edge Events */
 2007         vuint32_t IFEE7:1;               /* Enable Falling Edge Events */
 2008         vuint32_t IFEE6:1;               /* Enable Falling Edge Events */
 2009         vuint32_t IFEE5:1;               /* Enable Falling Edge Events */
 2010         vuint32_t IFEE4:1;               /* Enable Falling Edge Events */
 2011         vuint32_t IFEE3:1;               /* Enable Falling Edge Events */
 2012         vuint32_t IFEE2:1;               /* Enable Falling Edge Events */
 2013         vuint32_t IFEE1:1;               /* Enable Falling Edge Events */
 2014         vuint32_t IFEE0:1;               /* Enable Falling Edge Events */
 2015       } B;
 2016     } SIUL_IFEER_32B_tag;
 2017   
 2018     typedef union {                      /* IFER Interrupt Filter Enable Register */
 2019       vuint32_t R;
 2020       struct {
 2021         vuint32_t IFE31:1;               /* Enable Digital Glitch Filter */
 2022         vuint32_t IFE30:1;               /* Enable Digital Glitch Filter */
 2023         vuint32_t IFE29:1;               /* Enable Digital Glitch Filter */
 2024         vuint32_t IFE28:1;               /* Enable Digital Glitch Filter */
 2025         vuint32_t IFE27:1;               /* Enable Digital Glitch Filter */
 2026         vuint32_t IFE26:1;               /* Enable Digital Glitch Filter */
 2027         vuint32_t IFE25:1;               /* Enable Digital Glitch Filter */
 2028         vuint32_t IFE24:1;               /* Enable Digital Glitch Filter */
 2029         vuint32_t IFE23:1;               /* Enable Digital Glitch Filter */
 2030         vuint32_t IFE22:1;               /* Enable Digital Glitch Filter */
 2031         vuint32_t IFE21:1;               /* Enable Digital Glitch Filter */
 2032         vuint32_t IFE20:1;               /* Enable Digital Glitch Filter */
 2033         vuint32_t IFE19:1;               /* Enable Digital Glitch Filter */
 2034         vuint32_t IFE18:1;               /* Enable Digital Glitch Filter */
 2035         vuint32_t IFE17:1;               /* Enable Digital Glitch Filter */
 2036         vuint32_t IFE16:1;               /* Enable Digital Glitch Filter */
 2037         vuint32_t IFE15:1;               /* Enable Digital Glitch Filter */
 2038         vuint32_t IFE14:1;               /* Enable Digital Glitch Filter */
 2039         vuint32_t IFE13:1;               /* Enable Digital Glitch Filter */
 2040         vuint32_t IFE12:1;               /* Enable Digital Glitch Filter */
 2041         vuint32_t IFE11:1;               /* Enable Digital Glitch Filter */
 2042         vuint32_t IFE10:1;               /* Enable Digital Glitch Filter */
 2043         vuint32_t IFE9:1;                /* Enable Digital Glitch Filter */
 2044         vuint32_t IFE8:1;                /* Enable Digital Glitch Filter */
 2045         vuint32_t IFE7:1;                /* Enable Digital Glitch Filter */
 2046         vuint32_t IFE6:1;                /* Enable Digital Glitch Filter */
 2047         vuint32_t IFE5:1;                /* Enable Digital Glitch Filter */
 2048         vuint32_t IFE4:1;                /* Enable Digital Glitch Filter */
 2049         vuint32_t IFE3:1;                /* Enable Digital Glitch Filter */
 2050         vuint32_t IFE2:1;                /* Enable Digital Glitch Filter */
 2051         vuint32_t IFE1:1;                /* Enable Digital Glitch Filter */
 2052         vuint32_t IFE0:1;                /* Enable Digital Glitch Filter */
 2053       } B;
 2054     } SIUL_IFER_32B_tag;
 2055   
 2056     /* Register layout for all registers PCR ... */
 2057     typedef union {                      /* PCR - Pad Configuration Register */
 2058       vuint16_t R;
 2059       struct {
 2060        vuint16_t:
 2061         1;
 2062   
 2063   #ifndef USE_FIELD_ALIASES_SIUL
 2064   
 2065         vuint16_t SMC:1;                 /* Safe Mode Control */
 2066   
 2067   #else
 2068   
 2069         vuint16_t SME:1;                 /* deprecated name - please avoid */
 2070   
 2071   #endif
 2072   
 2073         vuint16_t APC:1;                 /* Analog Pad Control */
 2074        vuint16_t:
 2075         1;
 2076         vuint16_t PA:2;                  /* Pad Output Assignment */
 2077         vuint16_t OBE:1;                 /* Output Buffer Enable */
 2078         vuint16_t IBE:1;                 /* Input Buffer Enable */
 2079   
 2080   #ifndef USE_FIELD_ALIASES_SIUL
 2081   
 2082         vuint16_t DSC:2;                 /* Drive Strength Control */
 2083   
 2084   #else
 2085   
 2086         vuint16_t DCS:2;                 /* deprecated name - please avoid */
 2087   
 2088   #endif
 2089   
 2090         vuint16_t ODE:1;                 /* Open Drain Output Enable */
 2091         vuint16_t HYS:1;                 /* Input Hysteresis */
 2092         vuint16_t SRC:2;                 /* Slew Rate Control */
 2093         vuint16_t WPE:1;                 /* Weak Pull Up/Down Enable */
 2094         vuint16_t WPS:1;                 /* Weak Pull Up/Down Select */
 2095       } B;
 2096     } SIUL_PCR_16B_tag;
 2097   
 2098     /* Register layout for all registers PSMI ... */
 2099     typedef union {                      /* PSMI - Pad Selection for Multiplexed Inputs */
 2100       vuint8_t R;
 2101       struct {
 2102        vuint8_t:
 2103         4;
 2104         vuint8_t PADSEL:4;               /* Pad selection for pin */
 2105       } B;
 2106     } SIUL_PSMI_8B_tag;
 2107   
 2108     /* Register layout for all registers PSMI ... */
 2109     typedef union {                      /* PSMI - Pad Selection for Multiplexed Inputs */
 2110       vuint32_t R;
 2111       struct {
 2112        vuint32_t:
 2113         4;
 2114         vuint32_t PADSEL0:4;             /* Pad selection for pin */
 2115        vuint32_t:
 2116         4;
 2117         vuint32_t PADSEL1:4;             /* Pad selection for pin */
 2118        vuint32_t:
 2119         4;
 2120         vuint32_t PADSEL2:4;             /* Pad selection for pin */
 2121        vuint32_t:
 2122         4;
 2123         vuint32_t PADSEL3:4;             /* Pad selection for pin */
 2124       } B;
 2125     } SIUL_PSMI_32B_tag;
 2126   
 2127     /* Register layout for all registers GPDO ... */
 2128     typedef union {                      /* GPDO - GPIO Pad Data Output Register */
 2129       vuint8_t R;
 2130       struct {
 2131        vuint8_t:
 2132         7;
 2133         vuint8_t PDO:1;                  /* Pad Data Out */
 2134       } B;
 2135     } SIUL_GPDO_8B_tag;
 2136   
 2137     /* Register layout for all registers GPDO ... */
 2138     typedef union {                      /* GPDO - GPIO Pad Data Output Register */
 2139       vuint32_t R;
 2140       struct {
 2141        vuint32_t:
 2142         7;
 2143         vuint32_t PDO0:1;                /* Pad Data Out */
 2144        vuint32_t:
 2145         7;
 2146         vuint32_t PDO1:1;                /* Pad Data Out */
 2147        vuint32_t:
 2148         7;
 2149         vuint32_t PDO2:1;                /* Pad Data Out */
 2150        vuint32_t:
 2151         7;
 2152         vuint32_t PDO3:1;                /* Pad Data Out */
 2153       } B;
 2154     } SIUL_GPDO_32B_tag;
 2155   
 2156     /* Register layout for all registers GPDI ... */
 2157     typedef union {                      /* GPDI - GPIO Pad Data Input Register */
 2158       vuint8_t R;
 2159       struct {
 2160        vuint8_t:
 2161         7;
 2162         vuint8_t PDI:1;                  /* Pad Data In */
 2163       } B;
 2164     } SIUL_GPDI_8B_tag;
 2165   
 2166     /* Register layout for all registers GPDI ... */
 2167     typedef union {                      /* GPDI - GPIO Pad Data Input Register */
 2168       vuint32_t R;
 2169       struct {
 2170        vuint32_t:
 2171         7;
 2172         vuint32_t PDI0:1;                /* Pad Data In */
 2173        vuint32_t:
 2174         7;
 2175         vuint32_t PDI1:1;                /* Pad Data In */
 2176        vuint32_t:
 2177         7;
 2178         vuint32_t PDI2:1;                /* Pad Data In */
 2179        vuint32_t:
 2180         7;
 2181         vuint32_t PDI3:1;                /* Pad Data In */
 2182       } B;
 2183     } SIUL_GPDI_32B_tag;
 2184   
 2185     /* Register layout for all registers PGPDO ... */
 2186     typedef union {                      /* PGPDO - Parallel GPIO Pad Data Out Register */
 2187       vuint16_t R;
 2188     } SIUL_PGPDO_16B_tag;
 2189   
 2190     /* Register layout for all registers PGPDI ... */
 2191     typedef union {                      /* PGPDI - Parallel GPIO Pad Data In Register */
 2192       vuint16_t R;
 2193     } SIUL_PGPDI_16B_tag;
 2194   
 2195     /* Register layout for all registers MPGPDO ... */
 2196     typedef union {                      /* MPGPDO - Masked Parallel GPIO Pad Data Out Register */
 2197       vuint32_t R;
 2198       struct {
 2199         vuint32_t MASK:16;               /* Mask Field */
 2200         vuint32_t MPPDO:16;              /* Masked Parallel Pad Data Out */
 2201       } B;
 2202     } SIUL_MPGPDO_32B_tag;
 2203   
 2204     /* Register layout for all registers IFMC ... */
 2205     typedef union {                      /* IFMC - Interrupt Filter Maximum Counter Register */
 2206       vuint32_t R;
 2207       struct {
 2208        vuint32_t:
 2209         28;
 2210         vuint32_t MAXCNT:4;              /* Maximum Interrupt Filter Counter Setting */
 2211       } B;
 2212     } SIUL_IFMC_32B_tag;
 2213   
 2214     typedef union {                      /* IFCPR - Inerrupt Filter Clock Prescaler Register */
 2215       vuint32_t R;
 2216       struct {
 2217        vuint32_t:
 2218         28;
 2219         vuint32_t IFCP:4;                /* Interrupt Filter Clock Prescaler Setting */
 2220       } B;
 2221     } SIUL_IFCPR_32B_tag;
 2222   
 2223     typedef struct SIUL_struct_tag {
 2224       int8_t SIUL_reserved_0000[4];
 2225       union {
 2226         /* MIDR1 - MCU ID Register #1 */
 2227         SIUL_MIDR1_32B_tag MIDR1;        /* offset: 0x0004 size: 32 bit */
 2228         SIUL_MIDR1_32B_tag MIDR;         /* deprecated - please avoid */
 2229       };
 2230   
 2231       /* MIDR2 - MCU ID Register #2 */
 2232       SIUL_MIDR2_32B_tag MIDR2;          /* offset: 0x0008 size: 32 bit */
 2233       int8_t SIUL_reserved_000C[8];
 2234   
 2235       /* ISR - Interrupt Status Flag Register */
 2236       SIUL_ISR_32B_tag ISR;              /* offset: 0x0014 size: 32 bit */
 2237   
 2238       /* IRER - Interrupt Request Enable Register */
 2239       SIUL_IRER_32B_tag IRER;            /* offset: 0x0018 size: 32 bit */
 2240       int8_t SIUL_reserved_001C[12];
 2241   
 2242       /* IREER - Interrupt Rising Edge Event Enable */
 2243       SIUL_IREER_32B_tag IREER;          /* offset: 0x0028 size: 32 bit */
 2244   
 2245       /* IFEER - Interrupt Falling-Edge Event Enable */
 2246       SIUL_IFEER_32B_tag IFEER;          /* offset: 0x002C size: 32 bit */
 2247   
 2248       /* IFER Interrupt Filter Enable Register */
 2249       SIUL_IFER_32B_tag IFER;            /* offset: 0x0030 size: 32 bit */
 2250       int8_t SIUL_reserved_0034[12];
 2251       union {
 2252         /* PCR - Pad Configuration Register */
 2253         SIUL_PCR_16B_tag PCR[512];       /* offset: 0x0040  (0x0002 x 512) */
 2254         struct {
 2255           /* PCR - Pad Configuration Register */
 2256           SIUL_PCR_16B_tag PCR0;         /* offset: 0x0040 size: 16 bit */
 2257           SIUL_PCR_16B_tag PCR1;         /* offset: 0x0042 size: 16 bit */
 2258           SIUL_PCR_16B_tag PCR2;         /* offset: 0x0044 size: 16 bit */
 2259           SIUL_PCR_16B_tag PCR3;         /* offset: 0x0046 size: 16 bit */
 2260           SIUL_PCR_16B_tag PCR4;         /* offset: 0x0048 size: 16 bit */
 2261           SIUL_PCR_16B_tag PCR5;         /* offset: 0x004A size: 16 bit */
 2262           SIUL_PCR_16B_tag PCR6;         /* offset: 0x004C size: 16 bit */
 2263           SIUL_PCR_16B_tag PCR7;         /* offset: 0x004E size: 16 bit */
 2264           SIUL_PCR_16B_tag PCR8;         /* offset: 0x0050 size: 16 bit */
 2265           SIUL_PCR_16B_tag PCR9;         /* offset: 0x0052 size: 16 bit */
 2266           SIUL_PCR_16B_tag PCR10;        /* offset: 0x0054 size: 16 bit */
 2267           SIUL_PCR_16B_tag PCR11;        /* offset: 0x0056 size: 16 bit */
 2268           SIUL_PCR_16B_tag PCR12;        /* offset: 0x0058 size: 16 bit */
 2269           SIUL_PCR_16B_tag PCR13;        /* offset: 0x005A size: 16 bit */
 2270           SIUL_PCR_16B_tag PCR14;        /* offset: 0x005C size: 16 bit */
 2271           SIUL_PCR_16B_tag PCR15;        /* offset: 0x005E size: 16 bit */
 2272           SIUL_PCR_16B_tag PCR16;        /* offset: 0x0060 size: 16 bit */
 2273           SIUL_PCR_16B_tag PCR17;        /* offset: 0x0062 size: 16 bit */
 2274           SIUL_PCR_16B_tag PCR18;        /* offset: 0x0064 size: 16 bit */
 2275           SIUL_PCR_16B_tag PCR19;        /* offset: 0x0066 size: 16 bit */
 2276           SIUL_PCR_16B_tag PCR20;        /* offset: 0x0068 size: 16 bit */
 2277           SIUL_PCR_16B_tag PCR21;        /* offset: 0x006A size: 16 bit */
 2278           SIUL_PCR_16B_tag PCR22;        /* offset: 0x006C size: 16 bit */
 2279           SIUL_PCR_16B_tag PCR23;        /* offset: 0x006E size: 16 bit */
 2280           SIUL_PCR_16B_tag PCR24;        /* offset: 0x0070 size: 16 bit */
 2281           SIUL_PCR_16B_tag PCR25;        /* offset: 0x0072 size: 16 bit */
 2282           SIUL_PCR_16B_tag PCR26;        /* offset: 0x0074 size: 16 bit */
 2283           SIUL_PCR_16B_tag PCR27;        /* offset: 0x0076 size: 16 bit */
 2284           SIUL_PCR_16B_tag PCR28;        /* offset: 0x0078 size: 16 bit */
 2285           SIUL_PCR_16B_tag PCR29;        /* offset: 0x007A size: 16 bit */
 2286           SIUL_PCR_16B_tag PCR30;        /* offset: 0x007C size: 16 bit */
 2287           SIUL_PCR_16B_tag PCR31;        /* offset: 0x007E size: 16 bit */
 2288           SIUL_PCR_16B_tag PCR32;        /* offset: 0x0080 size: 16 bit */
 2289           SIUL_PCR_16B_tag PCR33;        /* offset: 0x0082 size: 16 bit */
 2290           SIUL_PCR_16B_tag PCR34;        /* offset: 0x0084 size: 16 bit */
 2291           SIUL_PCR_16B_tag PCR35;        /* offset: 0x0086 size: 16 bit */
 2292           SIUL_PCR_16B_tag PCR36;        /* offset: 0x0088 size: 16 bit */
 2293           SIUL_PCR_16B_tag PCR37;        /* offset: 0x008A size: 16 bit */
 2294           SIUL_PCR_16B_tag PCR38;        /* offset: 0x008C size: 16 bit */
 2295           SIUL_PCR_16B_tag PCR39;        /* offset: 0x008E size: 16 bit */
 2296           SIUL_PCR_16B_tag PCR40;        /* offset: 0x0090 size: 16 bit */
 2297           SIUL_PCR_16B_tag PCR41;        /* offset: 0x0092 size: 16 bit */
 2298           SIUL_PCR_16B_tag PCR42;        /* offset: 0x0094 size: 16 bit */
 2299           SIUL_PCR_16B_tag PCR43;        /* offset: 0x0096 size: 16 bit */
 2300           SIUL_PCR_16B_tag PCR44;        /* offset: 0x0098 size: 16 bit */
 2301           SIUL_PCR_16B_tag PCR45;        /* offset: 0x009A size: 16 bit */
 2302           SIUL_PCR_16B_tag PCR46;        /* offset: 0x009C size: 16 bit */
 2303           SIUL_PCR_16B_tag PCR47;        /* offset: 0x009E size: 16 bit */
 2304           SIUL_PCR_16B_tag PCR48;        /* offset: 0x00A0 size: 16 bit */
 2305           SIUL_PCR_16B_tag PCR49;        /* offset: 0x00A2 size: 16 bit */
 2306           SIUL_PCR_16B_tag PCR50;        /* offset: 0x00A4 size: 16 bit */
 2307           SIUL_PCR_16B_tag PCR51;        /* offset: 0x00A6 size: 16 bit */
 2308           SIUL_PCR_16B_tag PCR52;        /* offset: 0x00A8 size: 16 bit */
 2309           SIUL_PCR_16B_tag PCR53;        /* offset: 0x00AA size: 16 bit */
 2310           SIUL_PCR_16B_tag PCR54;        /* offset: 0x00AC size: 16 bit */
 2311           SIUL_PCR_16B_tag PCR55;        /* offset: 0x00AE size: 16 bit */
 2312           SIUL_PCR_16B_tag PCR56;        /* offset: 0x00B0 size: 16 bit */
 2313           SIUL_PCR_16B_tag PCR57;        /* offset: 0x00B2 size: 16 bit */
 2314           SIUL_PCR_16B_tag PCR58;        /* offset: 0x00B4 size: 16 bit */
 2315           SIUL_PCR_16B_tag PCR59;        /* offset: 0x00B6 size: 16 bit */
 2316           SIUL_PCR_16B_tag PCR60;        /* offset: 0x00B8 size: 16 bit */
 2317           SIUL_PCR_16B_tag PCR61;        /* offset: 0x00BA size: 16 bit */
 2318           SIUL_PCR_16B_tag PCR62;        /* offset: 0x00BC size: 16 bit */
 2319           SIUL_PCR_16B_tag PCR63;        /* offset: 0x00BE size: 16 bit */
 2320           SIUL_PCR_16B_tag PCR64;        /* offset: 0x00C0 size: 16 bit */
 2321           SIUL_PCR_16B_tag PCR65;        /* offset: 0x00C2 size: 16 bit */
 2322           SIUL_PCR_16B_tag PCR66;        /* offset: 0x00C4 size: 16 bit */
 2323           SIUL_PCR_16B_tag PCR67;        /* offset: 0x00C6 size: 16 bit */
 2324           SIUL_PCR_16B_tag PCR68;        /* offset: 0x00C8 size: 16 bit */
 2325           SIUL_PCR_16B_tag PCR69;        /* offset: 0x00CA size: 16 bit */
 2326           SIUL_PCR_16B_tag PCR70;        /* offset: 0x00CC size: 16 bit */
 2327           SIUL_PCR_16B_tag PCR71;        /* offset: 0x00CE size: 16 bit */
 2328           SIUL_PCR_16B_tag PCR72;        /* offset: 0x00D0 size: 16 bit */
 2329           SIUL_PCR_16B_tag PCR73;        /* offset: 0x00D2 size: 16 bit */
 2330           SIUL_PCR_16B_tag PCR74;        /* offset: 0x00D4 size: 16 bit */
 2331           SIUL_PCR_16B_tag PCR75;        /* offset: 0x00D6 size: 16 bit */
 2332           SIUL_PCR_16B_tag PCR76;        /* offset: 0x00D8 size: 16 bit */
 2333           SIUL_PCR_16B_tag PCR77;        /* offset: 0x00DA size: 16 bit */
 2334           SIUL_PCR_16B_tag PCR78;        /* offset: 0x00DC size: 16 bit */
 2335           SIUL_PCR_16B_tag PCR79;        /* offset: 0x00DE size: 16 bit */
 2336           SIUL_PCR_16B_tag PCR80;        /* offset: 0x00E0 size: 16 bit */
 2337           SIUL_PCR_16B_tag PCR81;        /* offset: 0x00E2 size: 16 bit */
 2338           SIUL_PCR_16B_tag PCR82;        /* offset: 0x00E4 size: 16 bit */
 2339           SIUL_PCR_16B_tag PCR83;        /* offset: 0x00E6 size: 16 bit */
 2340           SIUL_PCR_16B_tag PCR84;        /* offset: 0x00E8 size: 16 bit */
 2341           SIUL_PCR_16B_tag PCR85;        /* offset: 0x00EA size: 16 bit */
 2342           SIUL_PCR_16B_tag PCR86;        /* offset: 0x00EC size: 16 bit */
 2343           SIUL_PCR_16B_tag PCR87;        /* offset: 0x00EE size: 16 bit */
 2344           SIUL_PCR_16B_tag PCR88;        /* offset: 0x00F0 size: 16 bit */
 2345           SIUL_PCR_16B_tag PCR89;        /* offset: 0x00F2 size: 16 bit */
 2346           SIUL_PCR_16B_tag PCR90;        /* offset: 0x00F4 size: 16 bit */
 2347           SIUL_PCR_16B_tag PCR91;        /* offset: 0x00F6 size: 16 bit */
 2348           SIUL_PCR_16B_tag PCR92;        /* offset: 0x00F8 size: 16 bit */
 2349           SIUL_PCR_16B_tag PCR93;        /* offset: 0x00FA size: 16 bit */
 2350           SIUL_PCR_16B_tag PCR94;        /* offset: 0x00FC size: 16 bit */
 2351           SIUL_PCR_16B_tag PCR95;        /* offset: 0x00FE size: 16 bit */
 2352           SIUL_PCR_16B_tag PCR96;        /* offset: 0x0100 size: 16 bit */
 2353           SIUL_PCR_16B_tag PCR97;        /* offset: 0x0102 size: 16 bit */
 2354           SIUL_PCR_16B_tag PCR98;        /* offset: 0x0104 size: 16 bit */
 2355           SIUL_PCR_16B_tag PCR99;        /* offset: 0x0106 size: 16 bit */
 2356           SIUL_PCR_16B_tag PCR100;       /* offset: 0x0108 size: 16 bit */
 2357           SIUL_PCR_16B_tag PCR101;       /* offset: 0x010A size: 16 bit */
 2358           SIUL_PCR_16B_tag PCR102;       /* offset: 0x010C size: 16 bit */
 2359           SIUL_PCR_16B_tag PCR103;       /* offset: 0x010E size: 16 bit */
 2360           SIUL_PCR_16B_tag PCR104;       /* offset: 0x0110 size: 16 bit */
 2361           SIUL_PCR_16B_tag PCR105;       /* offset: 0x0112 size: 16 bit */
 2362           SIUL_PCR_16B_tag PCR106;       /* offset: 0x0114 size: 16 bit */
 2363           SIUL_PCR_16B_tag PCR107;       /* offset: 0x0116 size: 16 bit */
 2364           SIUL_PCR_16B_tag PCR108;       /* offset: 0x0118 size: 16 bit */
 2365           SIUL_PCR_16B_tag PCR109;       /* offset: 0x011A size: 16 bit */
 2366           SIUL_PCR_16B_tag PCR110;       /* offset: 0x011C size: 16 bit */
 2367           SIUL_PCR_16B_tag PCR111;       /* offset: 0x011E size: 16 bit */
 2368           SIUL_PCR_16B_tag PCR112;       /* offset: 0x0120 size: 16 bit */
 2369           SIUL_PCR_16B_tag PCR113;       /* offset: 0x0122 size: 16 bit */
 2370           SIUL_PCR_16B_tag PCR114;       /* offset: 0x0124 size: 16 bit */
 2371           SIUL_PCR_16B_tag PCR115;       /* offset: 0x0126 size: 16 bit */
 2372           SIUL_PCR_16B_tag PCR116;       /* offset: 0x0128 size: 16 bit */
 2373           SIUL_PCR_16B_tag PCR117;       /* offset: 0x012A size: 16 bit */
 2374           SIUL_PCR_16B_tag PCR118;       /* offset: 0x012C size: 16 bit */
 2375           SIUL_PCR_16B_tag PCR119;       /* offset: 0x012E size: 16 bit */
 2376           SIUL_PCR_16B_tag PCR120;       /* offset: 0x0130 size: 16 bit */
 2377           SIUL_PCR_16B_tag PCR121;       /* offset: 0x0132 size: 16 bit */
 2378           SIUL_PCR_16B_tag PCR122;       /* offset: 0x0134 size: 16 bit */
 2379           SIUL_PCR_16B_tag PCR123;       /* offset: 0x0136 size: 16 bit */
 2380           SIUL_PCR_16B_tag PCR124;       /* offset: 0x0138 size: 16 bit */
 2381           SIUL_PCR_16B_tag PCR125;       /* offset: 0x013A size: 16 bit */
 2382           SIUL_PCR_16B_tag PCR126;       /* offset: 0x013C size: 16 bit */
 2383           SIUL_PCR_16B_tag PCR127;       /* offset: 0x013E size: 16 bit */
 2384           SIUL_PCR_16B_tag PCR128;       /* offset: 0x0140 size: 16 bit */
 2385           SIUL_PCR_16B_tag PCR129;       /* offset: 0x0142 size: 16 bit */
 2386           SIUL_PCR_16B_tag PCR130;       /* offset: 0x0144 size: 16 bit */
 2387           SIUL_PCR_16B_tag PCR131;       /* offset: 0x0146 size: 16 bit */
 2388           SIUL_PCR_16B_tag PCR132;       /* offset: 0x0148 size: 16 bit */
 2389           SIUL_PCR_16B_tag PCR133;       /* offset: 0x014A size: 16 bit */
 2390           SIUL_PCR_16B_tag PCR134;       /* offset: 0x014C size: 16 bit */
 2391           SIUL_PCR_16B_tag PCR135;       /* offset: 0x014E size: 16 bit */
 2392           SIUL_PCR_16B_tag PCR136;       /* offset: 0x0150 size: 16 bit */
 2393           SIUL_PCR_16B_tag PCR137;       /* offset: 0x0152 size: 16 bit */
 2394           SIUL_PCR_16B_tag PCR138;       /* offset: 0x0154 size: 16 bit */
 2395           SIUL_PCR_16B_tag PCR139;       /* offset: 0x0156 size: 16 bit */
 2396           SIUL_PCR_16B_tag PCR140;       /* offset: 0x0158 size: 16 bit */
 2397           SIUL_PCR_16B_tag PCR141;       /* offset: 0x015A size: 16 bit */
 2398           SIUL_PCR_16B_tag PCR142;       /* offset: 0x015C size: 16 bit */
 2399           SIUL_PCR_16B_tag PCR143;       /* offset: 0x015E size: 16 bit */
 2400           SIUL_PCR_16B_tag PCR144;       /* offset: 0x0160 size: 16 bit */
 2401           SIUL_PCR_16B_tag PCR145;       /* offset: 0x0162 size: 16 bit */
 2402           SIUL_PCR_16B_tag PCR146;       /* offset: 0x0164 size: 16 bit */
 2403           SIUL_PCR_16B_tag PCR147;       /* offset: 0x0166 size: 16 bit */
 2404           SIUL_PCR_16B_tag PCR148;       /* offset: 0x0168 size: 16 bit */
 2405           SIUL_PCR_16B_tag PCR149;       /* offset: 0x016A size: 16 bit */
 2406           SIUL_PCR_16B_tag PCR150;       /* offset: 0x016C size: 16 bit */
 2407           SIUL_PCR_16B_tag PCR151;       /* offset: 0x016E size: 16 bit */
 2408           SIUL_PCR_16B_tag PCR152;       /* offset: 0x0170 size: 16 bit */
 2409           SIUL_PCR_16B_tag PCR153;       /* offset: 0x0172 size: 16 bit */
 2410           SIUL_PCR_16B_tag PCR154;       /* offset: 0x0174 size: 16 bit */
 2411           SIUL_PCR_16B_tag PCR155;       /* offset: 0x0176 size: 16 bit */
 2412           SIUL_PCR_16B_tag PCR156;       /* offset: 0x0178 size: 16 bit */
 2413           SIUL_PCR_16B_tag PCR157;       /* offset: 0x017A size: 16 bit */
 2414           SIUL_PCR_16B_tag PCR158;       /* offset: 0x017C size: 16 bit */
 2415           SIUL_PCR_16B_tag PCR159;       /* offset: 0x017E size: 16 bit */
 2416           SIUL_PCR_16B_tag PCR160;       /* offset: 0x0180 size: 16 bit */
 2417           SIUL_PCR_16B_tag PCR161;       /* offset: 0x0182 size: 16 bit */
 2418           SIUL_PCR_16B_tag PCR162;       /* offset: 0x0184 size: 16 bit */
 2419           SIUL_PCR_16B_tag PCR163;       /* offset: 0x0186 size: 16 bit */
 2420           SIUL_PCR_16B_tag PCR164;       /* offset: 0x0188 size: 16 bit */
 2421           SIUL_PCR_16B_tag PCR165;       /* offset: 0x018A size: 16 bit */
 2422           SIUL_PCR_16B_tag PCR166;       /* offset: 0x018C size: 16 bit */
 2423           SIUL_PCR_16B_tag PCR167;       /* offset: 0x018E size: 16 bit */
 2424           SIUL_PCR_16B_tag PCR168;       /* offset: 0x0190 size: 16 bit */
 2425           SIUL_PCR_16B_tag PCR169;       /* offset: 0x0192 size: 16 bit */
 2426           SIUL_PCR_16B_tag PCR170;       /* offset: 0x0194 size: 16 bit */
 2427           SIUL_PCR_16B_tag PCR171;       /* offset: 0x0196 size: 16 bit */
 2428           SIUL_PCR_16B_tag PCR172;       /* offset: 0x0198 size: 16 bit */
 2429           SIUL_PCR_16B_tag PCR173;       /* offset: 0x019A size: 16 bit */
 2430           SIUL_PCR_16B_tag PCR174;       /* offset: 0x019C size: 16 bit */
 2431           SIUL_PCR_16B_tag PCR175;       /* offset: 0x019E size: 16 bit */
 2432           SIUL_PCR_16B_tag PCR176;       /* offset: 0x01A0 size: 16 bit */
 2433           SIUL_PCR_16B_tag PCR177;       /* offset: 0x01A2 size: 16 bit */
 2434           SIUL_PCR_16B_tag PCR178;       /* offset: 0x01A4 size: 16 bit */
 2435           SIUL_PCR_16B_tag PCR179;       /* offset: 0x01A6 size: 16 bit */
 2436           SIUL_PCR_16B_tag PCR180;       /* offset: 0x01A8 size: 16 bit */
 2437           SIUL_PCR_16B_tag PCR181;       /* offset: 0x01AA size: 16 bit */
 2438           SIUL_PCR_16B_tag PCR182;       /* offset: 0x01AC size: 16 bit */
 2439           SIUL_PCR_16B_tag PCR183;       /* offset: 0x01AE size: 16 bit */
 2440           SIUL_PCR_16B_tag PCR184;       /* offset: 0x01B0 size: 16 bit */
 2441           SIUL_PCR_16B_tag PCR185;       /* offset: 0x01B2 size: 16 bit */
 2442           SIUL_PCR_16B_tag PCR186;       /* offset: 0x01B4 size: 16 bit */
 2443           SIUL_PCR_16B_tag PCR187;       /* offset: 0x01B6 size: 16 bit */
 2444           SIUL_PCR_16B_tag PCR188;       /* offset: 0x01B8 size: 16 bit */
 2445           SIUL_PCR_16B_tag PCR189;       /* offset: 0x01BA size: 16 bit */
 2446           SIUL_PCR_16B_tag PCR190;       /* offset: 0x01BC size: 16 bit */
 2447           SIUL_PCR_16B_tag PCR191;       /* offset: 0x01BE size: 16 bit */
 2448           SIUL_PCR_16B_tag PCR192;       /* offset: 0x01C0 size: 16 bit */
 2449           SIUL_PCR_16B_tag PCR193;       /* offset: 0x01C2 size: 16 bit */
 2450           SIUL_PCR_16B_tag PCR194;       /* offset: 0x01C4 size: 16 bit */
 2451           SIUL_PCR_16B_tag PCR195;       /* offset: 0x01C6 size: 16 bit */
 2452           SIUL_PCR_16B_tag PCR196;       /* offset: 0x01C8 size: 16 bit */
 2453           SIUL_PCR_16B_tag PCR197;       /* offset: 0x01CA size: 16 bit */
 2454           SIUL_PCR_16B_tag PCR198;       /* offset: 0x01CC size: 16 bit */
 2455           SIUL_PCR_16B_tag PCR199;       /* offset: 0x01CE size: 16 bit */
 2456           SIUL_PCR_16B_tag PCR200;       /* offset: 0x01D0 size: 16 bit */
 2457           SIUL_PCR_16B_tag PCR201;       /* offset: 0x01D2 size: 16 bit */
 2458           SIUL_PCR_16B_tag PCR202;       /* offset: 0x01D4 size: 16 bit */
 2459           SIUL_PCR_16B_tag PCR203;       /* offset: 0x01D6 size: 16 bit */
 2460           SIUL_PCR_16B_tag PCR204;       /* offset: 0x01D8 size: 16 bit */
 2461           SIUL_PCR_16B_tag PCR205;       /* offset: 0x01DA size: 16 bit */
 2462           SIUL_PCR_16B_tag PCR206;       /* offset: 0x01DC size: 16 bit */
 2463           SIUL_PCR_16B_tag PCR207;       /* offset: 0x01DE size: 16 bit */
 2464           SIUL_PCR_16B_tag PCR208;       /* offset: 0x01E0 size: 16 bit */
 2465           SIUL_PCR_16B_tag PCR209;       /* offset: 0x01E2 size: 16 bit */
 2466           SIUL_PCR_16B_tag PCR210;       /* offset: 0x01E4 size: 16 bit */
 2467           SIUL_PCR_16B_tag PCR211;       /* offset: 0x01E6 size: 16 bit */
 2468           SIUL_PCR_16B_tag PCR212;       /* offset: 0x01E8 size: 16 bit */
 2469           SIUL_PCR_16B_tag PCR213;       /* offset: 0x01EA size: 16 bit */
 2470           SIUL_PCR_16B_tag PCR214;       /* offset: 0x01EC size: 16 bit */
 2471           SIUL_PCR_16B_tag PCR215;       /* offset: 0x01EE size: 16 bit */
 2472           SIUL_PCR_16B_tag PCR216;       /* offset: 0x01F0 size: 16 bit */
 2473           SIUL_PCR_16B_tag PCR217;       /* offset: 0x01F2 size: 16 bit */
 2474           SIUL_PCR_16B_tag PCR218;       /* offset: 0x01F4 size: 16 bit */
 2475           SIUL_PCR_16B_tag PCR219;       /* offset: 0x01F6 size: 16 bit */
 2476           SIUL_PCR_16B_tag PCR220;       /* offset: 0x01F8 size: 16 bit */
 2477           SIUL_PCR_16B_tag PCR221;       /* offset: 0x01FA size: 16 bit */
 2478           SIUL_PCR_16B_tag PCR222;       /* offset: 0x01FC size: 16 bit */
 2479           SIUL_PCR_16B_tag PCR223;       /* offset: 0x01FE size: 16 bit */
 2480           SIUL_PCR_16B_tag PCR224;       /* offset: 0x0200 size: 16 bit */
 2481           SIUL_PCR_16B_tag PCR225;       /* offset: 0x0202 size: 16 bit */
 2482           SIUL_PCR_16B_tag PCR226;       /* offset: 0x0204 size: 16 bit */
 2483           SIUL_PCR_16B_tag PCR227;       /* offset: 0x0206 size: 16 bit */
 2484           SIUL_PCR_16B_tag PCR228;       /* offset: 0x0208 size: 16 bit */
 2485           SIUL_PCR_16B_tag PCR229;       /* offset: 0x020A size: 16 bit */
 2486           SIUL_PCR_16B_tag PCR230;       /* offset: 0x020C size: 16 bit */
 2487           SIUL_PCR_16B_tag PCR231;       /* offset: 0x020E size: 16 bit */
 2488           SIUL_PCR_16B_tag PCR232;       /* offset: 0x0210 size: 16 bit */
 2489           SIUL_PCR_16B_tag PCR233;       /* offset: 0x0212 size: 16 bit */
 2490           SIUL_PCR_16B_tag PCR234;       /* offset: 0x0214 size: 16 bit */
 2491           SIUL_PCR_16B_tag PCR235;       /* offset: 0x0216 size: 16 bit */
 2492           SIUL_PCR_16B_tag PCR236;       /* offset: 0x0218 size: 16 bit */
 2493           SIUL_PCR_16B_tag PCR237;       /* offset: 0x021A size: 16 bit */
 2494           SIUL_PCR_16B_tag PCR238;       /* offset: 0x021C size: 16 bit */
 2495           SIUL_PCR_16B_tag PCR239;       /* offset: 0x021E size: 16 bit */
 2496           SIUL_PCR_16B_tag PCR240;       /* offset: 0x0220 size: 16 bit */
 2497           SIUL_PCR_16B_tag PCR241;       /* offset: 0x0222 size: 16 bit */
 2498           SIUL_PCR_16B_tag PCR242;       /* offset: 0x0224 size: 16 bit */
 2499           SIUL_PCR_16B_tag PCR243;       /* offset: 0x0226 size: 16 bit */
 2500           SIUL_PCR_16B_tag PCR244;       /* offset: 0x0228 size: 16 bit */
 2501           SIUL_PCR_16B_tag PCR245;       /* offset: 0x022A size: 16 bit */
 2502           SIUL_PCR_16B_tag PCR246;       /* offset: 0x022C size: 16 bit */
 2503           SIUL_PCR_16B_tag PCR247;       /* offset: 0x022E size: 16 bit */
 2504           SIUL_PCR_16B_tag PCR248;       /* offset: 0x0230 size: 16 bit */
 2505           SIUL_PCR_16B_tag PCR249;       /* offset: 0x0232 size: 16 bit */
 2506           SIUL_PCR_16B_tag PCR250;       /* offset: 0x0234 size: 16 bit */
 2507           SIUL_PCR_16B_tag PCR251;       /* offset: 0x0236 size: 16 bit */
 2508           SIUL_PCR_16B_tag PCR252;       /* offset: 0x0238 size: 16 bit */
 2509           SIUL_PCR_16B_tag PCR253;       /* offset: 0x023A size: 16 bit */
 2510           SIUL_PCR_16B_tag PCR254;       /* offset: 0x023C size: 16 bit */
 2511           SIUL_PCR_16B_tag PCR255;       /* offset: 0x023E size: 16 bit */
 2512           SIUL_PCR_16B_tag PCR256;       /* offset: 0x0240 size: 16 bit */
 2513           SIUL_PCR_16B_tag PCR257;       /* offset: 0x0242 size: 16 bit */
 2514           SIUL_PCR_16B_tag PCR258;       /* offset: 0x0244 size: 16 bit */
 2515           SIUL_PCR_16B_tag PCR259;       /* offset: 0x0246 size: 16 bit */
 2516           SIUL_PCR_16B_tag PCR260;       /* offset: 0x0248 size: 16 bit */
 2517           SIUL_PCR_16B_tag PCR261;       /* offset: 0x024A size: 16 bit */
 2518           SIUL_PCR_16B_tag PCR262;       /* offset: 0x024C size: 16 bit */
 2519           SIUL_PCR_16B_tag PCR263;       /* offset: 0x024E size: 16 bit */
 2520           SIUL_PCR_16B_tag PCR264;       /* offset: 0x0250 size: 16 bit */
 2521           SIUL_PCR_16B_tag PCR265;       /* offset: 0x0252 size: 16 bit */
 2522           SIUL_PCR_16B_tag PCR266;       /* offset: 0x0254 size: 16 bit */
 2523           SIUL_PCR_16B_tag PCR267;       /* offset: 0x0256 size: 16 bit */
 2524           SIUL_PCR_16B_tag PCR268;       /* offset: 0x0258 size: 16 bit */
 2525           SIUL_PCR_16B_tag PCR269;       /* offset: 0x025A size: 16 bit */
 2526           SIUL_PCR_16B_tag PCR270;       /* offset: 0x025C size: 16 bit */
 2527           SIUL_PCR_16B_tag PCR271;       /* offset: 0x025E size: 16 bit */
 2528           SIUL_PCR_16B_tag PCR272;       /* offset: 0x0260 size: 16 bit */
 2529           SIUL_PCR_16B_tag PCR273;       /* offset: 0x0262 size: 16 bit */
 2530           SIUL_PCR_16B_tag PCR274;       /* offset: 0x0264 size: 16 bit */
 2531           SIUL_PCR_16B_tag PCR275;       /* offset: 0x0266 size: 16 bit */
 2532           SIUL_PCR_16B_tag PCR276;       /* offset: 0x0268 size: 16 bit */
 2533           SIUL_PCR_16B_tag PCR277;       /* offset: 0x026A size: 16 bit */
 2534           SIUL_PCR_16B_tag PCR278;       /* offset: 0x026C size: 16 bit */
 2535           SIUL_PCR_16B_tag PCR279;       /* offset: 0x026E size: 16 bit */
 2536           SIUL_PCR_16B_tag PCR280;       /* offset: 0x0270 size: 16 bit */
 2537           SIUL_PCR_16B_tag PCR281;       /* offset: 0x0272 size: 16 bit */
 2538           SIUL_PCR_16B_tag PCR282;       /* offset: 0x0274 size: 16 bit */
 2539           SIUL_PCR_16B_tag PCR283;       /* offset: 0x0276 size: 16 bit */
 2540           SIUL_PCR_16B_tag PCR284;       /* offset: 0x0278 size: 16 bit */
 2541           SIUL_PCR_16B_tag PCR285;       /* offset: 0x027A size: 16 bit */
 2542           SIUL_PCR_16B_tag PCR286;       /* offset: 0x027C size: 16 bit */
 2543           SIUL_PCR_16B_tag PCR287;       /* offset: 0x027E size: 16 bit */
 2544           SIUL_PCR_16B_tag PCR288;       /* offset: 0x0280 size: 16 bit */
 2545           SIUL_PCR_16B_tag PCR289;       /* offset: 0x0282 size: 16 bit */
 2546           SIUL_PCR_16B_tag PCR290;       /* offset: 0x0284 size: 16 bit */
 2547           SIUL_PCR_16B_tag PCR291;       /* offset: 0x0286 size: 16 bit */
 2548           SIUL_PCR_16B_tag PCR292;       /* offset: 0x0288 size: 16 bit */
 2549           SIUL_PCR_16B_tag PCR293;       /* offset: 0x028A size: 16 bit */
 2550           SIUL_PCR_16B_tag PCR294;       /* offset: 0x028C size: 16 bit */
 2551           SIUL_PCR_16B_tag PCR295;       /* offset: 0x028E size: 16 bit */
 2552           SIUL_PCR_16B_tag PCR296;       /* offset: 0x0290 size: 16 bit */
 2553           SIUL_PCR_16B_tag PCR297;       /* offset: 0x0292 size: 16 bit */
 2554           SIUL_PCR_16B_tag PCR298;       /* offset: 0x0294 size: 16 bit */
 2555           SIUL_PCR_16B_tag PCR299;       /* offset: 0x0296 size: 16 bit */
 2556           SIUL_PCR_16B_tag PCR300;       /* offset: 0x0298 size: 16 bit */
 2557           SIUL_PCR_16B_tag PCR301;       /* offset: 0x029A size: 16 bit */
 2558           SIUL_PCR_16B_tag PCR302;       /* offset: 0x029C size: 16 bit */
 2559           SIUL_PCR_16B_tag PCR303;       /* offset: 0x029E size: 16 bit */
 2560           SIUL_PCR_16B_tag PCR304;       /* offset: 0x02A0 size: 16 bit */
 2561           SIUL_PCR_16B_tag PCR305;       /* offset: 0x02A2 size: 16 bit */
 2562           SIUL_PCR_16B_tag PCR306;       /* offset: 0x02A4 size: 16 bit */
 2563           SIUL_PCR_16B_tag PCR307;       /* offset: 0x02A6 size: 16 bit */
 2564           SIUL_PCR_16B_tag PCR308;       /* offset: 0x02A8 size: 16 bit */
 2565           SIUL_PCR_16B_tag PCR309;       /* offset: 0x02AA size: 16 bit */
 2566           SIUL_PCR_16B_tag PCR310;       /* offset: 0x02AC size: 16 bit */
 2567           SIUL_PCR_16B_tag PCR311;       /* offset: 0x02AE size: 16 bit */
 2568           SIUL_PCR_16B_tag PCR312;       /* offset: 0x02B0 size: 16 bit */
 2569           SIUL_PCR_16B_tag PCR313;       /* offset: 0x02B2 size: 16 bit */
 2570           SIUL_PCR_16B_tag PCR314;       /* offset: 0x02B4 size: 16 bit */
 2571           SIUL_PCR_16B_tag PCR315;       /* offset: 0x02B6 size: 16 bit */
 2572           SIUL_PCR_16B_tag PCR316;       /* offset: 0x02B8 size: 16 bit */
 2573           SIUL_PCR_16B_tag PCR317;       /* offset: 0x02BA size: 16 bit */
 2574           SIUL_PCR_16B_tag PCR318;       /* offset: 0x02BC size: 16 bit */
 2575           SIUL_PCR_16B_tag PCR319;       /* offset: 0x02BE size: 16 bit */
 2576           SIUL_PCR_16B_tag PCR320;       /* offset: 0x02C0 size: 16 bit */
 2577           SIUL_PCR_16B_tag PCR321;       /* offset: 0x02C2 size: 16 bit */
 2578           SIUL_PCR_16B_tag PCR322;       /* offset: 0x02C4 size: 16 bit */
 2579           SIUL_PCR_16B_tag PCR323;       /* offset: 0x02C6 size: 16 bit */
 2580           SIUL_PCR_16B_tag PCR324;       /* offset: 0x02C8 size: 16 bit */
 2581           SIUL_PCR_16B_tag PCR325;       /* offset: 0x02CA size: 16 bit */
 2582           SIUL_PCR_16B_tag PCR326;       /* offset: 0x02CC size: 16 bit */
 2583           SIUL_PCR_16B_tag PCR327;       /* offset: 0x02CE size: 16 bit */
 2584           SIUL_PCR_16B_tag PCR328;       /* offset: 0x02D0 size: 16 bit */
 2585           SIUL_PCR_16B_tag PCR329;       /* offset: 0x02D2 size: 16 bit */
 2586           SIUL_PCR_16B_tag PCR330;       /* offset: 0x02D4 size: 16 bit */
 2587           SIUL_PCR_16B_tag PCR331;       /* offset: 0x02D6 size: 16 bit */
 2588           SIUL_PCR_16B_tag PCR332;       /* offset: 0x02D8 size: 16 bit */
 2589           SIUL_PCR_16B_tag PCR333;       /* offset: 0x02DA size: 16 bit */
 2590           SIUL_PCR_16B_tag PCR334;       /* offset: 0x02DC size: 16 bit */
 2591           SIUL_PCR_16B_tag PCR335;       /* offset: 0x02DE size: 16 bit */
 2592           SIUL_PCR_16B_tag PCR336;       /* offset: 0x02E0 size: 16 bit */
 2593           SIUL_PCR_16B_tag PCR337;       /* offset: 0x02E2 size: 16 bit */
 2594           SIUL_PCR_16B_tag PCR338;       /* offset: 0x02E4 size: 16 bit */
 2595           SIUL_PCR_16B_tag PCR339;       /* offset: 0x02E6 size: 16 bit */
 2596           SIUL_PCR_16B_tag PCR340;       /* offset: 0x02E8 size: 16 bit */
 2597           SIUL_PCR_16B_tag PCR341;       /* offset: 0x02EA size: 16 bit */
 2598           SIUL_PCR_16B_tag PCR342;       /* offset: 0x02EC size: 16 bit */
 2599           SIUL_PCR_16B_tag PCR343;       /* offset: 0x02EE size: 16 bit */
 2600           SIUL_PCR_16B_tag PCR344;       /* offset: 0x02F0 size: 16 bit */
 2601           SIUL_PCR_16B_tag PCR345;       /* offset: 0x02F2 size: 16 bit */
 2602           SIUL_PCR_16B_tag PCR346;       /* offset: 0x02F4 size: 16 bit */
 2603           SIUL_PCR_16B_tag PCR347;       /* offset: 0x02F6 size: 16 bit */
 2604           SIUL_PCR_16B_tag PCR348;       /* offset: 0x02F8 size: 16 bit */
 2605           SIUL_PCR_16B_tag PCR349;       /* offset: 0x02FA size: 16 bit */
 2606           SIUL_PCR_16B_tag PCR350;       /* offset: 0x02FC size: 16 bit */
 2607           SIUL_PCR_16B_tag PCR351;       /* offset: 0x02FE size: 16 bit */
 2608           SIUL_PCR_16B_tag PCR352;       /* offset: 0x0300 size: 16 bit */
 2609           SIUL_PCR_16B_tag PCR353;       /* offset: 0x0302 size: 16 bit */
 2610           SIUL_PCR_16B_tag PCR354;       /* offset: 0x0304 size: 16 bit */
 2611           SIUL_PCR_16B_tag PCR355;       /* offset: 0x0306 size: 16 bit */
 2612           SIUL_PCR_16B_tag PCR356;       /* offset: 0x0308 size: 16 bit */
 2613           SIUL_PCR_16B_tag PCR357;       /* offset: 0x030A size: 16 bit */
 2614           SIUL_PCR_16B_tag PCR358;       /* offset: 0x030C size: 16 bit */
 2615           SIUL_PCR_16B_tag PCR359;       /* offset: 0x030E size: 16 bit */
 2616           SIUL_PCR_16B_tag PCR360;       /* offset: 0x0310 size: 16 bit */
 2617           SIUL_PCR_16B_tag PCR361;       /* offset: 0x0312 size: 16 bit */
 2618           SIUL_PCR_16B_tag PCR362;       /* offset: 0x0314 size: 16 bit */
 2619           SIUL_PCR_16B_tag PCR363;       /* offset: 0x0316 size: 16 bit */
 2620           SIUL_PCR_16B_tag PCR364;       /* offset: 0x0318 size: 16 bit */
 2621           SIUL_PCR_16B_tag PCR365;       /* offset: 0x031A size: 16 bit */
 2622           SIUL_PCR_16B_tag PCR366;       /* offset: 0x031C size: 16 bit */
 2623           SIUL_PCR_16B_tag PCR367;       /* offset: 0x031E size: 16 bit */
 2624           SIUL_PCR_16B_tag PCR368;       /* offset: 0x0320 size: 16 bit */
 2625           SIUL_PCR_16B_tag PCR369;       /* offset: 0x0322 size: 16 bit */
 2626           SIUL_PCR_16B_tag PCR370;       /* offset: 0x0324 size: 16 bit */
 2627           SIUL_PCR_16B_tag PCR371;       /* offset: 0x0326 size: 16 bit */
 2628           SIUL_PCR_16B_tag PCR372;       /* offset: 0x0328 size: 16 bit */
 2629           SIUL_PCR_16B_tag PCR373;       /* offset: 0x032A size: 16 bit */
 2630           SIUL_PCR_16B_tag PCR374;       /* offset: 0x032C size: 16 bit */
 2631           SIUL_PCR_16B_tag PCR375;       /* offset: 0x032E size: 16 bit */
 2632           SIUL_PCR_16B_tag PCR376;       /* offset: 0x0330 size: 16 bit */
 2633           SIUL_PCR_16B_tag PCR377;       /* offset: 0x0332 size: 16 bit */
 2634           SIUL_PCR_16B_tag PCR378;       /* offset: 0x0334 size: 16 bit */
 2635           SIUL_PCR_16B_tag PCR379;       /* offset: 0x0336 size: 16 bit */
 2636           SIUL_PCR_16B_tag PCR380;       /* offset: 0x0338 size: 16 bit */
 2637           SIUL_PCR_16B_tag PCR381;       /* offset: 0x033A size: 16 bit */
 2638           SIUL_PCR_16B_tag PCR382;       /* offset: 0x033C size: 16 bit */
 2639           SIUL_PCR_16B_tag PCR383;       /* offset: 0x033E size: 16 bit */
 2640           SIUL_PCR_16B_tag PCR384;       /* offset: 0x0340 size: 16 bit */
 2641           SIUL_PCR_16B_tag PCR385;       /* offset: 0x0342 size: 16 bit */
 2642           SIUL_PCR_16B_tag PCR386;       /* offset: 0x0344 size: 16 bit */
 2643           SIUL_PCR_16B_tag PCR387;       /* offset: 0x0346 size: 16 bit */
 2644           SIUL_PCR_16B_tag PCR388;       /* offset: 0x0348 size: 16 bit */
 2645           SIUL_PCR_16B_tag PCR389;       /* offset: 0x034A size: 16 bit */
 2646           SIUL_PCR_16B_tag PCR390;       /* offset: 0x034C size: 16 bit */
 2647           SIUL_PCR_16B_tag PCR391;       /* offset: 0x034E size: 16 bit */
 2648           SIUL_PCR_16B_tag PCR392;       /* offset: 0x0350 size: 16 bit */
 2649           SIUL_PCR_16B_tag PCR393;       /* offset: 0x0352 size: 16 bit */
 2650           SIUL_PCR_16B_tag PCR394;       /* offset: 0x0354 size: 16 bit */
 2651           SIUL_PCR_16B_tag PCR395;       /* offset: 0x0356 size: 16 bit */
 2652           SIUL_PCR_16B_tag PCR396;       /* offset: 0x0358 size: 16 bit */
 2653           SIUL_PCR_16B_tag PCR397;       /* offset: 0x035A size: 16 bit */
 2654           SIUL_PCR_16B_tag PCR398;       /* offset: 0x035C size: 16 bit */
 2655           SIUL_PCR_16B_tag PCR399;       /* offset: 0x035E size: 16 bit */
 2656           SIUL_PCR_16B_tag PCR400;       /* offset: 0x0360 size: 16 bit */
 2657           SIUL_PCR_16B_tag PCR401;       /* offset: 0x0362 size: 16 bit */
 2658           SIUL_PCR_16B_tag PCR402;       /* offset: 0x0364 size: 16 bit */
 2659           SIUL_PCR_16B_tag PCR403;       /* offset: 0x0366 size: 16 bit */
 2660           SIUL_PCR_16B_tag PCR404;       /* offset: 0x0368 size: 16 bit */
 2661           SIUL_PCR_16B_tag PCR405;       /* offset: 0x036A size: 16 bit */
 2662           SIUL_PCR_16B_tag PCR406;       /* offset: 0x036C size: 16 bit */
 2663           SIUL_PCR_16B_tag PCR407;       /* offset: 0x036E size: 16 bit */
 2664           SIUL_PCR_16B_tag PCR408;       /* offset: 0x0370 size: 16 bit */
 2665           SIUL_PCR_16B_tag PCR409;       /* offset: 0x0372 size: 16 bit */
 2666           SIUL_PCR_16B_tag PCR410;       /* offset: 0x0374 size: 16 bit */
 2667           SIUL_PCR_16B_tag PCR411;       /* offset: 0x0376 size: 16 bit */
 2668           SIUL_PCR_16B_tag PCR412;       /* offset: 0x0378 size: 16 bit */
 2669           SIUL_PCR_16B_tag PCR413;       /* offset: 0x037A size: 16 bit */
 2670           SIUL_PCR_16B_tag PCR414;       /* offset: 0x037C size: 16 bit */
 2671           SIUL_PCR_16B_tag PCR415;       /* offset: 0x037E size: 16 bit */
 2672           SIUL_PCR_16B_tag PCR416;       /* offset: 0x0380 size: 16 bit */
 2673           SIUL_PCR_16B_tag PCR417;       /* offset: 0x0382 size: 16 bit */
 2674           SIUL_PCR_16B_tag PCR418;       /* offset: 0x0384 size: 16 bit */
 2675           SIUL_PCR_16B_tag PCR419;       /* offset: 0x0386 size: 16 bit */
 2676           SIUL_PCR_16B_tag PCR420;       /* offset: 0x0388 size: 16 bit */
 2677           SIUL_PCR_16B_tag PCR421;       /* offset: 0x038A size: 16 bit */
 2678           SIUL_PCR_16B_tag PCR422;       /* offset: 0x038C size: 16 bit */
 2679           SIUL_PCR_16B_tag PCR423;       /* offset: 0x038E size: 16 bit */
 2680           SIUL_PCR_16B_tag PCR424;       /* offset: 0x0390 size: 16 bit */
 2681           SIUL_PCR_16B_tag PCR425;       /* offset: 0x0392 size: 16 bit */
 2682           SIUL_PCR_16B_tag PCR426;       /* offset: 0x0394 size: 16 bit */
 2683           SIUL_PCR_16B_tag PCR427;       /* offset: 0x0396 size: 16 bit */
 2684           SIUL_PCR_16B_tag PCR428;       /* offset: 0x0398 size: 16 bit */
 2685           SIUL_PCR_16B_tag PCR429;       /* offset: 0x039A size: 16 bit */
 2686           SIUL_PCR_16B_tag PCR430;       /* offset: 0x039C size: 16 bit */
 2687           SIUL_PCR_16B_tag PCR431;       /* offset: 0x039E size: 16 bit */
 2688           SIUL_PCR_16B_tag PCR432;       /* offset: 0x03A0 size: 16 bit */
 2689           SIUL_PCR_16B_tag PCR433;       /* offset: 0x03A2 size: 16 bit */
 2690           SIUL_PCR_16B_tag PCR434;       /* offset: 0x03A4 size: 16 bit */
 2691           SIUL_PCR_16B_tag PCR435;       /* offset: 0x03A6 size: 16 bit */
 2692           SIUL_PCR_16B_tag PCR436;       /* offset: 0x03A8 size: 16 bit */
 2693           SIUL_PCR_16B_tag PCR437;       /* offset: 0x03AA size: 16 bit */
 2694           SIUL_PCR_16B_tag PCR438;       /* offset: 0x03AC size: 16 bit */
 2695           SIUL_PCR_16B_tag PCR439;       /* offset: 0x03AE size: 16 bit */
 2696           SIUL_PCR_16B_tag PCR440;       /* offset: 0x03B0 size: 16 bit */
 2697           SIUL_PCR_16B_tag PCR441;       /* offset: 0x03B2 size: 16 bit */
 2698           SIUL_PCR_16B_tag PCR442;       /* offset: 0x03B4 size: 16 bit */
 2699           SIUL_PCR_16B_tag PCR443;       /* offset: 0x03B6 size: 16 bit */
 2700           SIUL_PCR_16B_tag PCR444;       /* offset: 0x03B8 size: 16 bit */
 2701           SIUL_PCR_16B_tag PCR445;       /* offset: 0x03BA size: 16 bit */
 2702           SIUL_PCR_16B_tag PCR446;       /* offset: 0x03BC size: 16 bit */
 2703           SIUL_PCR_16B_tag PCR447;       /* offset: 0x03BE size: 16 bit */
 2704           SIUL_PCR_16B_tag PCR448;       /* offset: 0x03C0 size: 16 bit */
 2705           SIUL_PCR_16B_tag PCR449;       /* offset: 0x03C2 size: 16 bit */
 2706           SIUL_PCR_16B_tag PCR450;       /* offset: 0x03C4 size: 16 bit */
 2707           SIUL_PCR_16B_tag PCR451;       /* offset: 0x03C6 size: 16 bit */
 2708           SIUL_PCR_16B_tag PCR452;       /* offset: 0x03C8 size: 16 bit */
 2709           SIUL_PCR_16B_tag PCR453;       /* offset: 0x03CA size: 16 bit */
 2710           SIUL_PCR_16B_tag PCR454;       /* offset: 0x03CC size: 16 bit */
 2711           SIUL_PCR_16B_tag PCR455;       /* offset: 0x03CE size: 16 bit */
 2712           SIUL_PCR_16B_tag PCR456;       /* offset: 0x03D0 size: 16 bit */
 2713           SIUL_PCR_16B_tag PCR457;       /* offset: 0x03D2 size: 16 bit */
 2714           SIUL_PCR_16B_tag PCR458;       /* offset: 0x03D4 size: 16 bit */
 2715           SIUL_PCR_16B_tag PCR459;       /* offset: 0x03D6 size: 16 bit */
 2716           SIUL_PCR_16B_tag PCR460;       /* offset: 0x03D8 size: 16 bit */
 2717           SIUL_PCR_16B_tag PCR461;       /* offset: 0x03DA size: 16 bit */
 2718           SIUL_PCR_16B_tag PCR462;       /* offset: 0x03DC size: 16 bit */
 2719           SIUL_PCR_16B_tag PCR463;       /* offset: 0x03DE size: 16 bit */
 2720           SIUL_PCR_16B_tag PCR464;       /* offset: 0x03E0 size: 16 bit */
 2721           SIUL_PCR_16B_tag PCR465;       /* offset: 0x03E2 size: 16 bit */
 2722           SIUL_PCR_16B_tag PCR466;       /* offset: 0x03E4 size: 16 bit */
 2723           SIUL_PCR_16B_tag PCR467;       /* offset: 0x03E6 size: 16 bit */
 2724           SIUL_PCR_16B_tag PCR468;       /* offset: 0x03E8 size: 16 bit */
 2725           SIUL_PCR_16B_tag PCR469;       /* offset: 0x03EA size: 16 bit */
 2726           SIUL_PCR_16B_tag PCR470;       /* offset: 0x03EC size: 16 bit */
 2727           SIUL_PCR_16B_tag PCR471;       /* offset: 0x03EE size: 16 bit */
 2728           SIUL_PCR_16B_tag PCR472;       /* offset: 0x03F0 size: 16 bit */
 2729           SIUL_PCR_16B_tag PCR473;       /* offset: 0x03F2 size: 16 bit */
 2730           SIUL_PCR_16B_tag PCR474;       /* offset: 0x03F4 size: 16 bit */
 2731           SIUL_PCR_16B_tag PCR475;       /* offset: 0x03F6 size: 16 bit */
 2732           SIUL_PCR_16B_tag PCR476;       /* offset: 0x03F8 size: 16 bit */
 2733           SIUL_PCR_16B_tag PCR477;       /* offset: 0x03FA size: 16 bit */
 2734           SIUL_PCR_16B_tag PCR478;       /* offset: 0x03FC size: 16 bit */
 2735           SIUL_PCR_16B_tag PCR479;       /* offset: 0x03FE size: 16 bit */
 2736           SIUL_PCR_16B_tag PCR480;       /* offset: 0x0400 size: 16 bit */
 2737           SIUL_PCR_16B_tag PCR481;       /* offset: 0x0402 size: 16 bit */
 2738           SIUL_PCR_16B_tag PCR482;       /* offset: 0x0404 size: 16 bit */
 2739           SIUL_PCR_16B_tag PCR483;       /* offset: 0x0406 size: 16 bit */
 2740           SIUL_PCR_16B_tag PCR484;       /* offset: 0x0408 size: 16 bit */
 2741           SIUL_PCR_16B_tag PCR485;       /* offset: 0x040A size: 16 bit */
 2742           SIUL_PCR_16B_tag PCR486;       /* offset: 0x040C size: 16 bit */
 2743           SIUL_PCR_16B_tag PCR487;       /* offset: 0x040E size: 16 bit */
 2744           SIUL_PCR_16B_tag PCR488;       /* offset: 0x0410 size: 16 bit */
 2745           SIUL_PCR_16B_tag PCR489;       /* offset: 0x0412 size: 16 bit */
 2746           SIUL_PCR_16B_tag PCR490;       /* offset: 0x0414 size: 16 bit */
 2747           SIUL_PCR_16B_tag PCR491;       /* offset: 0x0416 size: 16 bit */
 2748           SIUL_PCR_16B_tag PCR492;       /* offset: 0x0418 size: 16 bit */
 2749           SIUL_PCR_16B_tag PCR493;       /* offset: 0x041A size: 16 bit */
 2750           SIUL_PCR_16B_tag PCR494;       /* offset: 0x041C size: 16 bit */
 2751           SIUL_PCR_16B_tag PCR495;       /* offset: 0x041E size: 16 bit */
 2752           SIUL_PCR_16B_tag PCR496;       /* offset: 0x0420 size: 16 bit */
 2753           SIUL_PCR_16B_tag PCR497;       /* offset: 0x0422 size: 16 bit */
 2754           SIUL_PCR_16B_tag PCR498;       /* offset: 0x0424 size: 16 bit */
 2755           SIUL_PCR_16B_tag PCR499;       /* offset: 0x0426 size: 16 bit */
 2756           SIUL_PCR_16B_tag PCR500;       /* offset: 0x0428 size: 16 bit */
 2757           SIUL_PCR_16B_tag PCR501;       /* offset: 0x042A size: 16 bit */
 2758           SIUL_PCR_16B_tag PCR502;       /* offset: 0x042C size: 16 bit */
 2759           SIUL_PCR_16B_tag PCR503;       /* offset: 0x042E size: 16 bit */
 2760           SIUL_PCR_16B_tag PCR504;       /* offset: 0x0430 size: 16 bit */
 2761           SIUL_PCR_16B_tag PCR505;       /* offset: 0x0432 size: 16 bit */
 2762           SIUL_PCR_16B_tag PCR506;       /* offset: 0x0434 size: 16 bit */
 2763           SIUL_PCR_16B_tag PCR507;       /* offset: 0x0436 size: 16 bit */
 2764           SIUL_PCR_16B_tag PCR508;       /* offset: 0x0438 size: 16 bit */
 2765           SIUL_PCR_16B_tag PCR509;       /* offset: 0x043A size: 16 bit */
 2766           SIUL_PCR_16B_tag PCR510;       /* offset: 0x043C size: 16 bit */
 2767           SIUL_PCR_16B_tag PCR511;       /* offset: 0x043E size: 16 bit */
 2768         };
 2769       };
 2770   
 2771       int8_t SIUL_reserved_0440[192];
 2772       union {
 2773         /* PSMI - Pad Selection for Multiplexed Inputs */
 2774         SIUL_PSMI_32B_tag PSMI_32B[64];  /* offset: 0x0500  (0x0004 x 64) */
 2775   
 2776         /* PSMI - Pad Selection for Multiplexed Inputs */
 2777         SIUL_PSMI_8B_tag PSMI[256];      /* offset: 0x0500  (0x0001 x 256) */
 2778         struct {
 2779           /* PSMI - Pad Selection for Multiplexed Inputs */
 2780           SIUL_PSMI_32B_tag PSMI0_3;     /* offset: 0x0500 size: 32 bit */
 2781           SIUL_PSMI_32B_tag PSMI4_7;     /* offset: 0x0504 size: 32 bit */
 2782           SIUL_PSMI_32B_tag PSMI8_11;    /* offset: 0x0508 size: 32 bit */
 2783           SIUL_PSMI_32B_tag PSMI12_15;   /* offset: 0x050C size: 32 bit */
 2784           SIUL_PSMI_32B_tag PSMI16_19;   /* offset: 0x0510 size: 32 bit */
 2785           SIUL_PSMI_32B_tag PSMI20_23;   /* offset: 0x0514 size: 32 bit */
 2786           SIUL_PSMI_32B_tag PSMI24_27;   /* offset: 0x0518 size: 32 bit */
 2787           SIUL_PSMI_32B_tag PSMI28_31;   /* offset: 0x051C size: 32 bit */
 2788           SIUL_PSMI_32B_tag PSMI32_35;   /* offset: 0x0520 size: 32 bit */
 2789           SIUL_PSMI_32B_tag PSMI36_39;   /* offset: 0x0524 size: 32 bit */
 2790           SIUL_PSMI_32B_tag PSMI40_43;   /* offset: 0x0528 size: 32 bit */
 2791           SIUL_PSMI_32B_tag PSMI44_47;   /* offset: 0x052C size: 32 bit */
 2792           SIUL_PSMI_32B_tag PSMI48_51;   /* offset: 0x0530 size: 32 bit */
 2793           SIUL_PSMI_32B_tag PSMI52_55;   /* offset: 0x0534 size: 32 bit */
 2794           SIUL_PSMI_32B_tag PSMI56_59;   /* offset: 0x0538 size: 32 bit */
 2795           SIUL_PSMI_32B_tag PSMI60_63;   /* offset: 0x053C size: 32 bit */
 2796           SIUL_PSMI_32B_tag PSMI64_67;   /* offset: 0x0540 size: 32 bit */
 2797           SIUL_PSMI_32B_tag PSMI68_71;   /* offset: 0x0544 size: 32 bit */
 2798           SIUL_PSMI_32B_tag PSMI72_75;   /* offset: 0x0548 size: 32 bit */
 2799           SIUL_PSMI_32B_tag PSMI76_79;   /* offset: 0x054C size: 32 bit */
 2800           SIUL_PSMI_32B_tag PSMI80_83;   /* offset: 0x0550 size: 32 bit */
 2801           SIUL_PSMI_32B_tag PSMI84_87;   /* offset: 0x0554 size: 32 bit */
 2802           SIUL_PSMI_32B_tag PSMI88_91;   /* offset: 0x0558 size: 32 bit */
 2803           SIUL_PSMI_32B_tag PSMI92_95;   /* offset: 0x055C size: 32 bit */
 2804           SIUL_PSMI_32B_tag PSMI96_99;   /* offset: 0x0560 size: 32 bit */
 2805           SIUL_PSMI_32B_tag PSMI100_103; /* offset: 0x0564 size: 32 bit */
 2806           SIUL_PSMI_32B_tag PSMI104_107; /* offset: 0x0568 size: 32 bit */
 2807           SIUL_PSMI_32B_tag PSMI108_111; /* offset: 0x056C size: 32 bit */
 2808           SIUL_PSMI_32B_tag PSMI112_115; /* offset: 0x0570 size: 32 bit */
 2809           SIUL_PSMI_32B_tag PSMI116_119; /* offset: 0x0574 size: 32 bit */
 2810           SIUL_PSMI_32B_tag PSMI120_123; /* offset: 0x0578 size: 32 bit */
 2811           SIUL_PSMI_32B_tag PSMI124_127; /* offset: 0x057C size: 32 bit */
 2812           SIUL_PSMI_32B_tag PSMI128_131; /* offset: 0x0580 size: 32 bit */
 2813           SIUL_PSMI_32B_tag PSMI132_135; /* offset: 0x0584 size: 32 bit */
 2814           SIUL_PSMI_32B_tag PSMI136_139; /* offset: 0x0588 size: 32 bit */
 2815           SIUL_PSMI_32B_tag PSMI140_143; /* offset: 0x058C size: 32 bit */
 2816           SIUL_PSMI_32B_tag PSMI144_147; /* offset: 0x0590 size: 32 bit */
 2817           SIUL_PSMI_32B_tag PSMI148_151; /* offset: 0x0594 size: 32 bit */
 2818           SIUL_PSMI_32B_tag PSMI152_155; /* offset: 0x0598 size: 32 bit */
 2819           SIUL_PSMI_32B_tag PSMI156_159; /* offset: 0x059C size: 32 bit */
 2820           SIUL_PSMI_32B_tag PSMI160_163; /* offset: 0x05A0 size: 32 bit */
 2821           SIUL_PSMI_32B_tag PSMI164_167; /* offset: 0x05A4 size: 32 bit */
 2822           SIUL_PSMI_32B_tag PSMI168_171; /* offset: 0x05A8 size: 32 bit */
 2823           SIUL_PSMI_32B_tag PSMI172_175; /* offset: 0x05AC size: 32 bit */
 2824           SIUL_PSMI_32B_tag PSMI176_179; /* offset: 0x05B0 size: 32 bit */
 2825           SIUL_PSMI_32B_tag PSMI180_183; /* offset: 0x05B4 size: 32 bit */
 2826           SIUL_PSMI_32B_tag PSMI184_187; /* offset: 0x05B8 size: 32 bit */
 2827           SIUL_PSMI_32B_tag PSMI188_191; /* offset: 0x05BC size: 32 bit */
 2828           SIUL_PSMI_32B_tag PSMI192_195; /* offset: 0x05C0 size: 32 bit */
 2829           SIUL_PSMI_32B_tag PSMI196_199; /* offset: 0x05C4 size: 32 bit */
 2830           SIUL_PSMI_32B_tag PSMI200_203; /* offset: 0x05C8 size: 32 bit */
 2831           SIUL_PSMI_32B_tag PSMI204_207; /* offset: 0x05CC size: 32 bit */
 2832           SIUL_PSMI_32B_tag PSMI208_211; /* offset: 0x05D0 size: 32 bit */
 2833           SIUL_PSMI_32B_tag PSMI212_215; /* offset: 0x05D4 size: 32 bit */
 2834           SIUL_PSMI_32B_tag PSMI216_219; /* offset: 0x05D8 size: 32 bit */
 2835           SIUL_PSMI_32B_tag PSMI220_223; /* offset: 0x05DC size: 32 bit */
 2836           SIUL_PSMI_32B_tag PSMI224_227; /* offset: 0x05E0 size: 32 bit */
 2837           SIUL_PSMI_32B_tag PSMI228_231; /* offset: 0x05E4 size: 32 bit */
 2838           SIUL_PSMI_32B_tag PSMI232_235; /* offset: 0x05E8 size: 32 bit */
 2839           SIUL_PSMI_32B_tag PSMI236_239; /* offset: 0x05EC size: 32 bit */
 2840           SIUL_PSMI_32B_tag PSMI240_243; /* offset: 0x05F0 size: 32 bit */
 2841           SIUL_PSMI_32B_tag PSMI244_247; /* offset: 0x05F4 size: 32 bit */
 2842           SIUL_PSMI_32B_tag PSMI248_251; /* offset: 0x05F8 size: 32 bit */
 2843           SIUL_PSMI_32B_tag PSMI252_255; /* offset: 0x05FC size: 32 bit */
 2844         };
 2845   
 2846         struct {
 2847           /* PSMI - Pad Selection for Multiplexed Inputs */
 2848           SIUL_PSMI_8B_tag PSMI0;        /* offset: 0x0500 size: 8 bit */
 2849           SIUL_PSMI_8B_tag PSMI1;        /* offset: 0x0501 size: 8 bit */
 2850           SIUL_PSMI_8B_tag PSMI2;        /* offset: 0x0502 size: 8 bit */
 2851           SIUL_PSMI_8B_tag PSMI3;        /* offset: 0x0503 size: 8 bit */
 2852           SIUL_PSMI_8B_tag PSMI4;        /* offset: 0x0504 size: 8 bit */
 2853           SIUL_PSMI_8B_tag PSMI5;        /* offset: 0x0505 size: 8 bit */
 2854           SIUL_PSMI_8B_tag PSMI6;        /* offset: 0x0506 size: 8 bit */
 2855           SIUL_PSMI_8B_tag PSMI7;        /* offset: 0x0507 size: 8 bit */
 2856           SIUL_PSMI_8B_tag PSMI8;        /* offset: 0x0508 size: 8 bit */
 2857           SIUL_PSMI_8B_tag PSMI9;        /* offset: 0x0509 size: 8 bit */
 2858           SIUL_PSMI_8B_tag PSMI10;       /* offset: 0x050A size: 8 bit */
 2859           SIUL_PSMI_8B_tag PSMI11;       /* offset: 0x050B size: 8 bit */
 2860           SIUL_PSMI_8B_tag PSMI12;       /* offset: 0x050C size: 8 bit */
 2861           SIUL_PSMI_8B_tag PSMI13;       /* offset: 0x050D size: 8 bit */
 2862           SIUL_PSMI_8B_tag PSMI14;       /* offset: 0x050E size: 8 bit */
 2863           SIUL_PSMI_8B_tag PSMI15;       /* offset: 0x050F size: 8 bit */
 2864           SIUL_PSMI_8B_tag PSMI16;       /* offset: 0x0510 size: 8 bit */
 2865           SIUL_PSMI_8B_tag PSMI17;       /* offset: 0x0511 size: 8 bit */
 2866           SIUL_PSMI_8B_tag PSMI18;       /* offset: 0x0512 size: 8 bit */
 2867           SIUL_PSMI_8B_tag PSMI19;       /* offset: 0x0513 size: 8 bit */
 2868           SIUL_PSMI_8B_tag PSMI20;       /* offset: 0x0514 size: 8 bit */
 2869           SIUL_PSMI_8B_tag PSMI21;       /* offset: 0x0515 size: 8 bit */
 2870           SIUL_PSMI_8B_tag PSMI22;       /* offset: 0x0516 size: 8 bit */
 2871           SIUL_PSMI_8B_tag PSMI23;       /* offset: 0x0517 size: 8 bit */
 2872           SIUL_PSMI_8B_tag PSMI24;       /* offset: 0x0518 size: 8 bit */
 2873           SIUL_PSMI_8B_tag PSMI25;       /* offset: 0x0519 size: 8 bit */
 2874           SIUL_PSMI_8B_tag PSMI26;       /* offset: 0x051A size: 8 bit */
 2875           SIUL_PSMI_8B_tag PSMI27;       /* offset: 0x051B size: 8 bit */
 2876           SIUL_PSMI_8B_tag PSMI28;       /* offset: 0x051C size: 8 bit */
 2877           SIUL_PSMI_8B_tag PSMI29;       /* offset: 0x051D size: 8 bit */
 2878           SIUL_PSMI_8B_tag PSMI30;       /* offset: 0x051E size: 8 bit */
 2879           SIUL_PSMI_8B_tag PSMI31;       /* offset: 0x051F size: 8 bit */
 2880           SIUL_PSMI_8B_tag PSMI32;       /* offset: 0x0520 size: 8 bit */
 2881           SIUL_PSMI_8B_tag PSMI33;       /* offset: 0x0521 size: 8 bit */
 2882           SIUL_PSMI_8B_tag PSMI34;       /* offset: 0x0522 size: 8 bit */
 2883           SIUL_PSMI_8B_tag PSMI35;       /* offset: 0x0523 size: 8 bit */
 2884           SIUL_PSMI_8B_tag PSMI36;       /* offset: 0x0524 size: 8 bit */
 2885           SIUL_PSMI_8B_tag PSMI37;       /* offset: 0x0525 size: 8 bit */
 2886           SIUL_PSMI_8B_tag PSMI38;       /* offset: 0x0526 size: 8 bit */
 2887           SIUL_PSMI_8B_tag PSMI39;       /* offset: 0x0527 size: 8 bit */
 2888           SIUL_PSMI_8B_tag PSMI40;       /* offset: 0x0528 size: 8 bit */
 2889           SIUL_PSMI_8B_tag PSMI41;       /* offset: 0x0529 size: 8 bit */
 2890           SIUL_PSMI_8B_tag PSMI42;       /* offset: 0x052A size: 8 bit */
 2891           SIUL_PSMI_8B_tag PSMI43;       /* offset: 0x052B size: 8 bit */
 2892           SIUL_PSMI_8B_tag PSMI44;       /* offset: 0x052C size: 8 bit */
 2893           SIUL_PSMI_8B_tag PSMI45;       /* offset: 0x052D size: 8 bit */
 2894           SIUL_PSMI_8B_tag PSMI46;       /* offset: 0x052E size: 8 bit */
 2895           SIUL_PSMI_8B_tag PSMI47;       /* offset: 0x052F size: 8 bit */
 2896           SIUL_PSMI_8B_tag PSMI48;       /* offset: 0x0530 size: 8 bit */
 2897           SIUL_PSMI_8B_tag PSMI49;       /* offset: 0x0531 size: 8 bit */
 2898           SIUL_PSMI_8B_tag PSMI50;       /* offset: 0x0532 size: 8 bit */
 2899           SIUL_PSMI_8B_tag PSMI51;       /* offset: 0x0533 size: 8 bit */
 2900           SIUL_PSMI_8B_tag PSMI52;       /* offset: 0x0534 size: 8 bit */
 2901           SIUL_PSMI_8B_tag PSMI53;       /* offset: 0x0535 size: 8 bit */
 2902           SIUL_PSMI_8B_tag PSMI54;       /* offset: 0x0536 size: 8 bit */
 2903           SIUL_PSMI_8B_tag PSMI55;       /* offset: 0x0537 size: 8 bit */
 2904           SIUL_PSMI_8B_tag PSMI56;       /* offset: 0x0538 size: 8 bit */
 2905           SIUL_PSMI_8B_tag PSMI57;       /* offset: 0x0539 size: 8 bit */
 2906           SIUL_PSMI_8B_tag PSMI58;       /* offset: 0x053A size: 8 bit */
 2907           SIUL_PSMI_8B_tag PSMI59;       /* offset: 0x053B size: 8 bit */
 2908           SIUL_PSMI_8B_tag PSMI60;       /* offset: 0x053C size: 8 bit */
 2909           SIUL_PSMI_8B_tag PSMI61;       /* offset: 0x053D size: 8 bit */
 2910           SIUL_PSMI_8B_tag PSMI62;       /* offset: 0x053E size: 8 bit */
 2911           SIUL_PSMI_8B_tag PSMI63;       /* offset: 0x053F size: 8 bit */
 2912           SIUL_PSMI_8B_tag PSMI64;       /* offset: 0x0540 size: 8 bit */
 2913           SIUL_PSMI_8B_tag PSMI65;       /* offset: 0x0541 size: 8 bit */
 2914           SIUL_PSMI_8B_tag PSMI66;       /* offset: 0x0542 size: 8 bit */
 2915           SIUL_PSMI_8B_tag PSMI67;       /* offset: 0x0543 size: 8 bit */
 2916           SIUL_PSMI_8B_tag PSMI68;       /* offset: 0x0544 size: 8 bit */
 2917           SIUL_PSMI_8B_tag PSMI69;       /* offset: 0x0545 size: 8 bit */
 2918           SIUL_PSMI_8B_tag PSMI70;       /* offset: 0x0546 size: 8 bit */
 2919           SIUL_PSMI_8B_tag PSMI71;       /* offset: 0x0547 size: 8 bit */
 2920           SIUL_PSMI_8B_tag PSMI72;       /* offset: 0x0548 size: 8 bit */
 2921           SIUL_PSMI_8B_tag PSMI73;       /* offset: 0x0549 size: 8 bit */
 2922           SIUL_PSMI_8B_tag PSMI74;       /* offset: 0x054A size: 8 bit */
 2923           SIUL_PSMI_8B_tag PSMI75;       /* offset: 0x054B size: 8 bit */
 2924           SIUL_PSMI_8B_tag PSMI76;       /* offset: 0x054C size: 8 bit */
 2925           SIUL_PSMI_8B_tag PSMI77;       /* offset: 0x054D size: 8 bit */
 2926           SIUL_PSMI_8B_tag PSMI78;       /* offset: 0x054E size: 8 bit */
 2927           SIUL_PSMI_8B_tag PSMI79;       /* offset: 0x054F size: 8 bit */
 2928           SIUL_PSMI_8B_tag PSMI80;       /* offset: 0x0550 size: 8 bit */
 2929           SIUL_PSMI_8B_tag PSMI81;       /* offset: 0x0551 size: 8 bit */
 2930           SIUL_PSMI_8B_tag PSMI82;       /* offset: 0x0552 size: 8 bit */
 2931           SIUL_PSMI_8B_tag PSMI83;       /* offset: 0x0553 size: 8 bit */
 2932           SIUL_PSMI_8B_tag PSMI84;       /* offset: 0x0554 size: 8 bit */
 2933           SIUL_PSMI_8B_tag PSMI85;       /* offset: 0x0555 size: 8 bit */
 2934           SIUL_PSMI_8B_tag PSMI86;       /* offset: 0x0556 size: 8 bit */
 2935           SIUL_PSMI_8B_tag PSMI87;       /* offset: 0x0557 size: 8 bit */
 2936           SIUL_PSMI_8B_tag PSMI88;       /* offset: 0x0558 size: 8 bit */
 2937           SIUL_PSMI_8B_tag PSMI89;       /* offset: 0x0559 size: 8 bit */
 2938           SIUL_PSMI_8B_tag PSMI90;       /* offset: 0x055A size: 8 bit */
 2939           SIUL_PSMI_8B_tag PSMI91;       /* offset: 0x055B size: 8 bit */
 2940           SIUL_PSMI_8B_tag PSMI92;       /* offset: 0x055C size: 8 bit */
 2941           SIUL_PSMI_8B_tag PSMI93;       /* offset: 0x055D size: 8 bit */
 2942           SIUL_PSMI_8B_tag PSMI94;       /* offset: 0x055E size: 8 bit */
 2943           SIUL_PSMI_8B_tag PSMI95;       /* offset: 0x055F size: 8 bit */
 2944           SIUL_PSMI_8B_tag PSMI96;       /* offset: 0x0560 size: 8 bit */
 2945           SIUL_PSMI_8B_tag PSMI97;       /* offset: 0x0561 size: 8 bit */
 2946           SIUL_PSMI_8B_tag PSMI98;       /* offset: 0x0562 size: 8 bit */
 2947           SIUL_PSMI_8B_tag PSMI99;       /* offset: 0x0563 size: 8 bit */
 2948           SIUL_PSMI_8B_tag PSMI100;      /* offset: 0x0564 size: 8 bit */
 2949           SIUL_PSMI_8B_tag PSMI101;      /* offset: 0x0565 size: 8 bit */
 2950           SIUL_PSMI_8B_tag PSMI102;      /* offset: 0x0566 size: 8 bit */
 2951           SIUL_PSMI_8B_tag PSMI103;      /* offset: 0x0567 size: 8 bit */
 2952           SIUL_PSMI_8B_tag PSMI104;      /* offset: 0x0568 size: 8 bit */
 2953           SIUL_PSMI_8B_tag PSMI105;      /* offset: 0x0569 size: 8 bit */
 2954           SIUL_PSMI_8B_tag PSMI106;      /* offset: 0x056A size: 8 bit */
 2955           SIUL_PSMI_8B_tag PSMI107;      /* offset: 0x056B size: 8 bit */
 2956           SIUL_PSMI_8B_tag PSMI108;      /* offset: 0x056C size: 8 bit */
 2957           SIUL_PSMI_8B_tag PSMI109;      /* offset: 0x056D size: 8 bit */
 2958           SIUL_PSMI_8B_tag PSMI110;      /* offset: 0x056E size: 8 bit */
 2959           SIUL_PSMI_8B_tag PSMI111;      /* offset: 0x056F size: 8 bit */
 2960           SIUL_PSMI_8B_tag PSMI112;      /* offset: 0x0570 size: 8 bit */
 2961           SIUL_PSMI_8B_tag PSMI113;      /* offset: 0x0571 size: 8 bit */
 2962           SIUL_PSMI_8B_tag PSMI114;      /* offset: 0x0572 size: 8 bit */
 2963           SIUL_PSMI_8B_tag PSMI115;      /* offset: 0x0573 size: 8 bit */
 2964           SIUL_PSMI_8B_tag PSMI116;      /* offset: 0x0574 size: 8 bit */
 2965           SIUL_PSMI_8B_tag PSMI117;      /* offset: 0x0575 size: 8 bit */
 2966           SIUL_PSMI_8B_tag PSMI118;      /* offset: 0x0576 size: 8 bit */
 2967           SIUL_PSMI_8B_tag PSMI119;      /* offset: 0x0577 size: 8 bit */
 2968           SIUL_PSMI_8B_tag PSMI120;      /* offset: 0x0578 size: 8 bit */
 2969           SIUL_PSMI_8B_tag PSMI121;      /* offset: 0x0579 size: 8 bit */
 2970           SIUL_PSMI_8B_tag PSMI122;      /* offset: 0x057A size: 8 bit */
 2971           SIUL_PSMI_8B_tag PSMI123;      /* offset: 0x057B size: 8 bit */
 2972           SIUL_PSMI_8B_tag PSMI124;      /* offset: 0x057C size: 8 bit */
 2973           SIUL_PSMI_8B_tag PSMI125;      /* offset: 0x057D size: 8 bit */
 2974           SIUL_PSMI_8B_tag PSMI126;      /* offset: 0x057E size: 8 bit */
 2975           SIUL_PSMI_8B_tag PSMI127;      /* offset: 0x057F size: 8 bit */
 2976           SIUL_PSMI_8B_tag PSMI128;      /* offset: 0x0580 size: 8 bit */
 2977           SIUL_PSMI_8B_tag PSMI129;      /* offset: 0x0581 size: 8 bit */
 2978           SIUL_PSMI_8B_tag PSMI130;      /* offset: 0x0582 size: 8 bit */
 2979           SIUL_PSMI_8B_tag PSMI131;      /* offset: 0x0583 size: 8 bit */
 2980           SIUL_PSMI_8B_tag PSMI132;      /* offset: 0x0584 size: 8 bit */
 2981           SIUL_PSMI_8B_tag PSMI133;      /* offset: 0x0585 size: 8 bit */
 2982           SIUL_PSMI_8B_tag PSMI134;      /* offset: 0x0586 size: 8 bit */
 2983           SIUL_PSMI_8B_tag PSMI135;      /* offset: 0x0587 size: 8 bit */
 2984           SIUL_PSMI_8B_tag PSMI136;      /* offset: 0x0588 size: 8 bit */
 2985           SIUL_PSMI_8B_tag PSMI137;      /* offset: 0x0589 size: 8 bit */
 2986           SIUL_PSMI_8B_tag PSMI138;      /* offset: 0x058A size: 8 bit */
 2987           SIUL_PSMI_8B_tag PSMI139;      /* offset: 0x058B size: 8 bit */
 2988           SIUL_PSMI_8B_tag PSMI140;      /* offset: 0x058C size: 8 bit */
 2989           SIUL_PSMI_8B_tag PSMI141;      /* offset: 0x058D size: 8 bit */
 2990           SIUL_PSMI_8B_tag PSMI142;      /* offset: 0x058E size: 8 bit */
 2991           SIUL_PSMI_8B_tag PSMI143;      /* offset: 0x058F size: 8 bit */
 2992           SIUL_PSMI_8B_tag PSMI144;      /* offset: 0x0590 size: 8 bit */
 2993           SIUL_PSMI_8B_tag PSMI145;      /* offset: 0x0591 size: 8 bit */
 2994           SIUL_PSMI_8B_tag PSMI146;      /* offset: 0x0592 size: 8 bit */
 2995           SIUL_PSMI_8B_tag PSMI147;      /* offset: 0x0593 size: 8 bit */
 2996           SIUL_PSMI_8B_tag PSMI148;      /* offset: 0x0594 size: 8 bit */
 2997           SIUL_PSMI_8B_tag PSMI149;      /* offset: 0x0595 size: 8 bit */
 2998           SIUL_PSMI_8B_tag PSMI150;      /* offset: 0x0596 size: 8 bit */
 2999           SIUL_PSMI_8B_tag PSMI151;      /* offset: 0x0597 size: 8 bit */
 3000           SIUL_PSMI_8B_tag PSMI152;      /* offset: 0x0598 size: 8 bit */
 3001           SIUL_PSMI_8B_tag PSMI153;      /* offset: 0x0599 size: 8 bit */
 3002           SIUL_PSMI_8B_tag PSMI154;      /* offset: 0x059A size: 8 bit */
 3003           SIUL_PSMI_8B_tag PSMI155;      /* offset: 0x059B size: 8 bit */
 3004           SIUL_PSMI_8B_tag PSMI156;      /* offset: 0x059C size: 8 bit */
 3005           SIUL_PSMI_8B_tag PSMI157;      /* offset: 0x059D size: 8 bit */
 3006           SIUL_PSMI_8B_tag PSMI158;      /* offset: 0x059E size: 8 bit */
 3007           SIUL_PSMI_8B_tag PSMI159;      /* offset: 0x059F size: 8 bit */
 3008           SIUL_PSMI_8B_tag PSMI160;      /* offset: 0x05A0 size: 8 bit */
 3009           SIUL_PSMI_8B_tag PSMI161;      /* offset: 0x05A1 size: 8 bit */
 3010           SIUL_PSMI_8B_tag PSMI162;      /* offset: 0x05A2 size: 8 bit */
 3011           SIUL_PSMI_8B_tag PSMI163;      /* offset: 0x05A3 size: 8 bit */
 3012           SIUL_PSMI_8B_tag PSMI164;      /* offset: 0x05A4 size: 8 bit */
 3013           SIUL_PSMI_8B_tag PSMI165;      /* offset: 0x05A5 size: 8 bit */
 3014           SIUL_PSMI_8B_tag PSMI166;      /* offset: 0x05A6 size: 8 bit */
 3015           SIUL_PSMI_8B_tag PSMI167;      /* offset: 0x05A7 size: 8 bit */
 3016           SIUL_PSMI_8B_tag PSMI168;      /* offset: 0x05A8 size: 8 bit */
 3017           SIUL_PSMI_8B_tag PSMI169;      /* offset: 0x05A9 size: 8 bit */
 3018           SIUL_PSMI_8B_tag PSMI170;      /* offset: 0x05AA size: 8 bit */
 3019           SIUL_PSMI_8B_tag PSMI171;      /* offset: 0x05AB size: 8 bit */
 3020           SIUL_PSMI_8B_tag PSMI172;      /* offset: 0x05AC size: 8 bit */
 3021           SIUL_PSMI_8B_tag PSMI173;      /* offset: 0x05AD size: 8 bit */
 3022           SIUL_PSMI_8B_tag PSMI174;      /* offset: 0x05AE size: 8 bit */
 3023           SIUL_PSMI_8B_tag PSMI175;      /* offset: 0x05AF size: 8 bit */
 3024           SIUL_PSMI_8B_tag PSMI176;      /* offset: 0x05B0 size: 8 bit */
 3025           SIUL_PSMI_8B_tag PSMI177;      /* offset: 0x05B1 size: 8 bit */
 3026           SIUL_PSMI_8B_tag PSMI178;      /* offset: 0x05B2 size: 8 bit */
 3027           SIUL_PSMI_8B_tag PSMI179;      /* offset: 0x05B3 size: 8 bit */
 3028           SIUL_PSMI_8B_tag PSMI180;      /* offset: 0x05B4 size: 8 bit */
 3029           SIUL_PSMI_8B_tag PSMI181;      /* offset: 0x05B5 size: 8 bit */
 3030           SIUL_PSMI_8B_tag PSMI182;      /* offset: 0x05B6 size: 8 bit */
 3031           SIUL_PSMI_8B_tag PSMI183;      /* offset: 0x05B7 size: 8 bit */
 3032           SIUL_PSMI_8B_tag PSMI184;      /* offset: 0x05B8 size: 8 bit */
 3033           SIUL_PSMI_8B_tag PSMI185;      /* offset: 0x05B9 size: 8 bit */
 3034           SIUL_PSMI_8B_tag PSMI186;      /* offset: 0x05BA size: 8 bit */
 3035           SIUL_PSMI_8B_tag PSMI187;      /* offset: 0x05BB size: 8 bit */
 3036           SIUL_PSMI_8B_tag PSMI188;      /* offset: 0x05BC size: 8 bit */
 3037           SIUL_PSMI_8B_tag PSMI189;      /* offset: 0x05BD size: 8 bit */
 3038           SIUL_PSMI_8B_tag PSMI190;      /* offset: 0x05BE size: 8 bit */
 3039           SIUL_PSMI_8B_tag PSMI191;      /* offset: 0x05BF size: 8 bit */
 3040           SIUL_PSMI_8B_tag PSMI192;      /* offset: 0x05C0 size: 8 bit */
 3041           SIUL_PSMI_8B_tag PSMI193;      /* offset: 0x05C1 size: 8 bit */
 3042           SIUL_PSMI_8B_tag PSMI194;      /* offset: 0x05C2 size: 8 bit */
 3043           SIUL_PSMI_8B_tag PSMI195;      /* offset: 0x05C3 size: 8 bit */
 3044           SIUL_PSMI_8B_tag PSMI196;      /* offset: 0x05C4 size: 8 bit */
 3045           SIUL_PSMI_8B_tag PSMI197;      /* offset: 0x05C5 size: 8 bit */
 3046           SIUL_PSMI_8B_tag PSMI198;      /* offset: 0x05C6 size: 8 bit */
 3047           SIUL_PSMI_8B_tag PSMI199;      /* offset: 0x05C7 size: 8 bit */
 3048           SIUL_PSMI_8B_tag PSMI200;      /* offset: 0x05C8 size: 8 bit */
 3049           SIUL_PSMI_8B_tag PSMI201;      /* offset: 0x05C9 size: 8 bit */
 3050           SIUL_PSMI_8B_tag PSMI202;      /* offset: 0x05CA size: 8 bit */
 3051           SIUL_PSMI_8B_tag PSMI203;      /* offset: 0x05CB size: 8 bit */
 3052           SIUL_PSMI_8B_tag PSMI204;      /* offset: 0x05CC size: 8 bit */
 3053           SIUL_PSMI_8B_tag PSMI205;      /* offset: 0x05CD size: 8 bit */
 3054           SIUL_PSMI_8B_tag PSMI206;      /* offset: 0x05CE size: 8 bit */
 3055           SIUL_PSMI_8B_tag PSMI207;      /* offset: 0x05CF size: 8 bit */
 3056           SIUL_PSMI_8B_tag PSMI208;      /* offset: 0x05D0 size: 8 bit */
 3057           SIUL_PSMI_8B_tag PSMI209;      /* offset: 0x05D1 size: 8 bit */
 3058           SIUL_PSMI_8B_tag PSMI210;      /* offset: 0x05D2 size: 8 bit */
 3059           SIUL_PSMI_8B_tag PSMI211;      /* offset: 0x05D3 size: 8 bit */
 3060           SIUL_PSMI_8B_tag PSMI212;      /* offset: 0x05D4 size: 8 bit */
 3061           SIUL_PSMI_8B_tag PSMI213;      /* offset: 0x05D5 size: 8 bit */
 3062           SIUL_PSMI_8B_tag PSMI214;      /* offset: 0x05D6 size: 8 bit */
 3063           SIUL_PSMI_8B_tag PSMI215;      /* offset: 0x05D7 size: 8 bit */
 3064           SIUL_PSMI_8B_tag PSMI216;      /* offset: 0x05D8 size: 8 bit */
 3065           SIUL_PSMI_8B_tag PSMI217;      /* offset: 0x05D9 size: 8 bit */
 3066           SIUL_PSMI_8B_tag PSMI218;      /* offset: 0x05DA size: 8 bit */
 3067           SIUL_PSMI_8B_tag PSMI219;      /* offset: 0x05DB size: 8 bit */
 3068           SIUL_PSMI_8B_tag PSMI220;      /* offset: 0x05DC size: 8 bit */
 3069           SIUL_PSMI_8B_tag PSMI221;      /* offset: 0x05DD size: 8 bit */
 3070           SIUL_PSMI_8B_tag PSMI222;      /* offset: 0x05DE size: 8 bit */
 3071           SIUL_PSMI_8B_tag PSMI223;      /* offset: 0x05DF size: 8 bit */
 3072           SIUL_PSMI_8B_tag PSMI224;      /* offset: 0x05E0 size: 8 bit */
 3073           SIUL_PSMI_8B_tag PSMI225;      /* offset: 0x05E1 size: 8 bit */
 3074           SIUL_PSMI_8B_tag PSMI226;      /* offset: 0x05E2 size: 8 bit */
 3075           SIUL_PSMI_8B_tag PSMI227;      /* offset: 0x05E3 size: 8 bit */
 3076           SIUL_PSMI_8B_tag PSMI228;      /* offset: 0x05E4 size: 8 bit */
 3077           SIUL_PSMI_8B_tag PSMI229;      /* offset: 0x05E5 size: 8 bit */
 3078           SIUL_PSMI_8B_tag PSMI230;      /* offset: 0x05E6 size: 8 bit */
 3079           SIUL_PSMI_8B_tag PSMI231;      /* offset: 0x05E7 size: 8 bit */
 3080           SIUL_PSMI_8B_tag PSMI232;      /* offset: 0x05E8 size: 8 bit */
 3081           SIUL_PSMI_8B_tag PSMI233;      /* offset: 0x05E9 size: 8 bit */
 3082           SIUL_PSMI_8B_tag PSMI234;      /* offset: 0x05EA size: 8 bit */
 3083           SIUL_PSMI_8B_tag PSMI235;      /* offset: 0x05EB size: 8 bit */
 3084           SIUL_PSMI_8B_tag PSMI236;      /* offset: 0x05EC size: 8 bit */
 3085           SIUL_PSMI_8B_tag PSMI237;      /* offset: 0x05ED size: 8 bit */
 3086           SIUL_PSMI_8B_tag PSMI238;      /* offset: 0x05EE size: 8 bit */
 3087           SIUL_PSMI_8B_tag PSMI239;      /* offset: 0x05EF size: 8 bit */
 3088           SIUL_PSMI_8B_tag PSMI240;      /* offset: 0x05F0 size: 8 bit */
 3089           SIUL_PSMI_8B_tag PSMI241;      /* offset: 0x05F1 size: 8 bit */
 3090           SIUL_PSMI_8B_tag PSMI242;      /* offset: 0x05F2 size: 8 bit */
 3091           SIUL_PSMI_8B_tag PSMI243;      /* offset: 0x05F3 size: 8 bit */
 3092           SIUL_PSMI_8B_tag PSMI244;      /* offset: 0x05F4 size: 8 bit */
 3093           SIUL_PSMI_8B_tag PSMI245;      /* offset: 0x05F5 size: 8 bit */
 3094           SIUL_PSMI_8B_tag PSMI246;      /* offset: 0x05F6 size: 8 bit */
 3095           SIUL_PSMI_8B_tag PSMI247;      /* offset: 0x05F7 size: 8 bit */
 3096           SIUL_PSMI_8B_tag PSMI248;      /* offset: 0x05F8 size: 8 bit */
 3097           SIUL_PSMI_8B_tag PSMI249;      /* offset: 0x05F9 size: 8 bit */
 3098           SIUL_PSMI_8B_tag PSMI250;      /* offset: 0x05FA size: 8 bit */
 3099           SIUL_PSMI_8B_tag PSMI251;      /* offset: 0x05FB size: 8 bit */
 3100           SIUL_PSMI_8B_tag PSMI252;      /* offset: 0x05FC size: 8 bit */
 3101           SIUL_PSMI_8B_tag PSMI253;      /* offset: 0x05FD size: 8 bit */
 3102           SIUL_PSMI_8B_tag PSMI254;      /* offset: 0x05FE size: 8 bit */
 3103           SIUL_PSMI_8B_tag PSMI255;      /* offset: 0x05FF size: 8 bit */
 3104         };
 3105       };
 3106   
 3107       union {
 3108         /* GPDO - GPIO Pad Data Output Register */
 3109         SIUL_GPDO_32B_tag GPDO_32B[128]; /* offset: 0x0600  (0x0004 x 128) */
 3110   
 3111         /* GPDO - GPIO Pad Data Output Register */
 3112         SIUL_GPDO_8B_tag GPDO[512];      /* offset: 0x0600  (0x0001 x 512) */
 3113         struct {
 3114           /* GPDO - GPIO Pad Data Output Register */
 3115           SIUL_GPDO_32B_tag GPDO0_3;     /* offset: 0x0600 size: 32 bit */
 3116           SIUL_GPDO_32B_tag GPDO4_7;     /* offset: 0x0604 size: 32 bit */
 3117           SIUL_GPDO_32B_tag GPDO8_11;    /* offset: 0x0608 size: 32 bit */
 3118           SIUL_GPDO_32B_tag GPDO12_15;   /* offset: 0x060C size: 32 bit */
 3119           SIUL_GPDO_32B_tag GPDO16_19;   /* offset: 0x0610 size: 32 bit */
 3120           SIUL_GPDO_32B_tag GPDO20_23;   /* offset: 0x0614 size: 32 bit */
 3121           SIUL_GPDO_32B_tag GPDO24_27;   /* offset: 0x0618 size: 32 bit */
 3122           SIUL_GPDO_32B_tag GPDO28_31;   /* offset: 0x061C size: 32 bit */
 3123           SIUL_GPDO_32B_tag GPDO32_35;   /* offset: 0x0620 size: 32 bit */
 3124           SIUL_GPDO_32B_tag GPDO36_39;   /* offset: 0x0624 size: 32 bit */
 3125           SIUL_GPDO_32B_tag GPDO40_43;   /* offset: 0x0628 size: 32 bit */
 3126           SIUL_GPDO_32B_tag GPDO44_47;   /* offset: 0x062C size: 32 bit */
 3127           SIUL_GPDO_32B_tag GPDO48_51;   /* offset: 0x0630 size: 32 bit */
 3128           SIUL_GPDO_32B_tag GPDO52_55;   /* offset: 0x0634 size: 32 bit */
 3129           SIUL_GPDO_32B_tag GPDO56_59;   /* offset: 0x0638 size: 32 bit */
 3130           SIUL_GPDO_32B_tag GPDO60_63;   /* offset: 0x063C size: 32 bit */
 3131           SIUL_GPDO_32B_tag GPDO64_67;   /* offset: 0x0640 size: 32 bit */
 3132           SIUL_GPDO_32B_tag GPDO68_71;   /* offset: 0x0644 size: 32 bit */
 3133           SIUL_GPDO_32B_tag GPDO72_75;   /* offset: 0x0648 size: 32 bit */
 3134           SIUL_GPDO_32B_tag GPDO76_79;   /* offset: 0x064C size: 32 bit */
 3135           SIUL_GPDO_32B_tag GPDO80_83;   /* offset: 0x0650 size: 32 bit */
 3136           SIUL_GPDO_32B_tag GPDO84_87;   /* offset: 0x0654 size: 32 bit */
 3137           SIUL_GPDO_32B_tag GPDO88_91;   /* offset: 0x0658 size: 32 bit */
 3138           SIUL_GPDO_32B_tag GPDO92_95;   /* offset: 0x065C size: 32 bit */
 3139           SIUL_GPDO_32B_tag GPDO96_99;   /* offset: 0x0660 size: 32 bit */
 3140           SIUL_GPDO_32B_tag GPDO100_103; /* offset: 0x0664 size: 32 bit */
 3141           SIUL_GPDO_32B_tag GPDO104_107; /* offset: 0x0668 size: 32 bit */
 3142           SIUL_GPDO_32B_tag GPDO108_111; /* offset: 0x066C size: 32 bit */
 3143           SIUL_GPDO_32B_tag GPDO112_115; /* offset: 0x0670 size: 32 bit */
 3144           SIUL_GPDO_32B_tag GPDO116_119; /* offset: 0x0674 size: 32 bit */
 3145           SIUL_GPDO_32B_tag GPDO120_123; /* offset: 0x0678 size: 32 bit */
 3146           SIUL_GPDO_32B_tag GPDO124_127; /* offset: 0x067C size: 32 bit */
 3147           SIUL_GPDO_32B_tag GPDO128_131; /* offset: 0x0680 size: 32 bit */
 3148           SIUL_GPDO_32B_tag GPDO132_135; /* offset: 0x0684 size: 32 bit */
 3149           SIUL_GPDO_32B_tag GPDO136_139; /* offset: 0x0688 size: 32 bit */
 3150           SIUL_GPDO_32B_tag GPDO140_143; /* offset: 0x068C size: 32 bit */
 3151           SIUL_GPDO_32B_tag GPDO144_147; /* offset: 0x0690 size: 32 bit */
 3152           SIUL_GPDO_32B_tag GPDO148_151; /* offset: 0x0694 size: 32 bit */
 3153           SIUL_GPDO_32B_tag GPDO152_155; /* offset: 0x0698 size: 32 bit */
 3154           SIUL_GPDO_32B_tag GPDO156_159; /* offset: 0x069C size: 32 bit */
 3155           SIUL_GPDO_32B_tag GPDO160_163; /* offset: 0x06A0 size: 32 bit */
 3156           SIUL_GPDO_32B_tag GPDO164_167; /* offset: 0x06A4 size: 32 bit */
 3157           SIUL_GPDO_32B_tag GPDO168_171; /* offset: 0x06A8 size: 32 bit */
 3158           SIUL_GPDO_32B_tag GPDO172_175; /* offset: 0x06AC size: 32 bit */
 3159           SIUL_GPDO_32B_tag GPDO176_179; /* offset: 0x06B0 size: 32 bit */
 3160           SIUL_GPDO_32B_tag GPDO180_183; /* offset: 0x06B4 size: 32 bit */
 3161           SIUL_GPDO_32B_tag GPDO184_187; /* offset: 0x06B8 size: 32 bit */
 3162           SIUL_GPDO_32B_tag GPDO188_191; /* offset: 0x06BC size: 32 bit */
 3163           SIUL_GPDO_32B_tag GPDO192_195; /* offset: 0x06C0 size: 32 bit */
 3164           SIUL_GPDO_32B_tag GPDO196_199; /* offset: 0x06C4 size: 32 bit */
 3165           SIUL_GPDO_32B_tag GPDO200_203; /* offset: 0x06C8 size: 32 bit */
 3166           SIUL_GPDO_32B_tag GPDO204_207; /* offset: 0x06CC size: 32 bit */
 3167           SIUL_GPDO_32B_tag GPDO208_211; /* offset: 0x06D0 size: 32 bit */
 3168           SIUL_GPDO_32B_tag GPDO212_215; /* offset: 0x06D4 size: 32 bit */
 3169           SIUL_GPDO_32B_tag GPDO216_219; /* offset: 0x06D8 size: 32 bit */
 3170           SIUL_GPDO_32B_tag GPDO220_223; /* offset: 0x06DC size: 32 bit */
 3171           SIUL_GPDO_32B_tag GPDO224_227; /* offset: 0x06E0 size: 32 bit */
 3172           SIUL_GPDO_32B_tag GPDO228_231; /* offset: 0x06E4 size: 32 bit */
 3173           SIUL_GPDO_32B_tag GPDO232_235; /* offset: 0x06E8 size: 32 bit */
 3174           SIUL_GPDO_32B_tag GPDO236_239; /* offset: 0x06EC size: 32 bit */
 3175           SIUL_GPDO_32B_tag GPDO240_243; /* offset: 0x06F0 size: 32 bit */
 3176           SIUL_GPDO_32B_tag GPDO244_247; /* offset: 0x06F4 size: 32 bit */
 3177           SIUL_GPDO_32B_tag GPDO248_251; /* offset: 0x06F8 size: 32 bit */
 3178           SIUL_GPDO_32B_tag GPDO252_255; /* offset: 0x06FC size: 32 bit */
 3179           SIUL_GPDO_32B_tag GPDO256_259; /* offset: 0x0700 size: 32 bit */
 3180           SIUL_GPDO_32B_tag GPDO260_263; /* offset: 0x0704 size: 32 bit */
 3181           SIUL_GPDO_32B_tag GPDO264_267; /* offset: 0x0708 size: 32 bit */
 3182           SIUL_GPDO_32B_tag GPDO268_271; /* offset: 0x070C size: 32 bit */
 3183           SIUL_GPDO_32B_tag GPDO272_275; /* offset: 0x0710 size: 32 bit */
 3184           SIUL_GPDO_32B_tag GPDO276_279; /* offset: 0x0714 size: 32 bit */
 3185           SIUL_GPDO_32B_tag GPDO280_283; /* offset: 0x0718 size: 32 bit */
 3186           SIUL_GPDO_32B_tag GPDO284_287; /* offset: 0x071C size: 32 bit */
 3187           SIUL_GPDO_32B_tag GPDO288_291; /* offset: 0x0720 size: 32 bit */
 3188           SIUL_GPDO_32B_tag GPDO292_295; /* offset: 0x0724 size: 32 bit */
 3189           SIUL_GPDO_32B_tag GPDO296_299; /* offset: 0x0728 size: 32 bit */
 3190           SIUL_GPDO_32B_tag GPDO300_303; /* offset: 0x072C size: 32 bit */
 3191           SIUL_GPDO_32B_tag GPDO304_307; /* offset: 0x0730 size: 32 bit */
 3192           SIUL_GPDO_32B_tag GPDO308_311; /* offset: 0x0734 size: 32 bit */
 3193           SIUL_GPDO_32B_tag GPDO312_315; /* offset: 0x0738 size: 32 bit */
 3194           SIUL_GPDO_32B_tag GPDO316_319; /* offset: 0x073C size: 32 bit */
 3195           SIUL_GPDO_32B_tag GPDO320_323; /* offset: 0x0740 size: 32 bit */
 3196           SIUL_GPDO_32B_tag GPDO324_327; /* offset: 0x0744 size: 32 bit */
 3197           SIUL_GPDO_32B_tag GPDO328_331; /* offset: 0x0748 size: 32 bit */
 3198           SIUL_GPDO_32B_tag GPDO332_335; /* offset: 0x074C size: 32 bit */
 3199           SIUL_GPDO_32B_tag GPDO336_339; /* offset: 0x0750 size: 32 bit */
 3200           SIUL_GPDO_32B_tag GPDO340_343; /* offset: 0x0754 size: 32 bit */
 3201           SIUL_GPDO_32B_tag GPDO344_347; /* offset: 0x0758 size: 32 bit */
 3202           SIUL_GPDO_32B_tag GPDO348_351; /* offset: 0x075C size: 32 bit */
 3203           SIUL_GPDO_32B_tag GPDO352_355; /* offset: 0x0760 size: 32 bit */
 3204           SIUL_GPDO_32B_tag GPDO356_359; /* offset: 0x0764 size: 32 bit */
 3205           SIUL_GPDO_32B_tag GPDO360_363; /* offset: 0x0768 size: 32 bit */
 3206           SIUL_GPDO_32B_tag GPDO364_367; /* offset: 0x076C size: 32 bit */
 3207           SIUL_GPDO_32B_tag GPDO368_371; /* offset: 0x0770 size: 32 bit */
 3208           SIUL_GPDO_32B_tag GPDO372_375; /* offset: 0x0774 size: 32 bit */
 3209           SIUL_GPDO_32B_tag GPDO376_379; /* offset: 0x0778 size: 32 bit */
 3210           SIUL_GPDO_32B_tag GPDO380_383; /* offset: 0x077C size: 32 bit */
 3211           SIUL_GPDO_32B_tag GPDO384_387; /* offset: 0x0780 size: 32 bit */
 3212           SIUL_GPDO_32B_tag GPDO388_391; /* offset: 0x0784 size: 32 bit */
 3213           SIUL_GPDO_32B_tag GPDO392_395; /* offset: 0x0788 size: 32 bit */
 3214           SIUL_GPDO_32B_tag GPDO396_399; /* offset: 0x078C size: 32 bit */
 3215           SIUL_GPDO_32B_tag GPDO400_403; /* offset: 0x0790 size: 32 bit */
 3216           SIUL_GPDO_32B_tag GPDO404_407; /* offset: 0x0794 size: 32 bit */
 3217           SIUL_GPDO_32B_tag GPDO408_411; /* offset: 0x0798 size: 32 bit */
 3218           SIUL_GPDO_32B_tag GPDO412_415; /* offset: 0x079C size: 32 bit */
 3219           SIUL_GPDO_32B_tag GPDO416_419; /* offset: 0x07A0 size: 32 bit */
 3220           SIUL_GPDO_32B_tag GPDO420_423; /* offset: 0x07A4 size: 32 bit */
 3221           SIUL_GPDO_32B_tag GPDO424_427; /* offset: 0x07A8 size: 32 bit */
 3222           SIUL_GPDO_32B_tag GPDO428_431; /* offset: 0x07AC size: 32 bit */
 3223           SIUL_GPDO_32B_tag GPDO432_435; /* offset: 0x07B0 size: 32 bit */
 3224           SIUL_GPDO_32B_tag GPDO436_439; /* offset: 0x07B4 size: 32 bit */
 3225           SIUL_GPDO_32B_tag GPDO440_443; /* offset: 0x07B8 size: 32 bit */
 3226           SIUL_GPDO_32B_tag GPDO444_447; /* offset: 0x07BC size: 32 bit */
 3227           SIUL_GPDO_32B_tag GPDO448_451; /* offset: 0x07C0 size: 32 bit */
 3228           SIUL_GPDO_32B_tag GPDO452_455; /* offset: 0x07C4 size: 32 bit */
 3229           SIUL_GPDO_32B_tag GPDO456_459; /* offset: 0x07C8 size: 32 bit */
 3230           SIUL_GPDO_32B_tag GPDO460_463; /* offset: 0x07CC size: 32 bit */
 3231           SIUL_GPDO_32B_tag GPDO464_467; /* offset: 0x07D0 size: 32 bit */
 3232           SIUL_GPDO_32B_tag GPDO468_471; /* offset: 0x07D4 size: 32 bit */
 3233           SIUL_GPDO_32B_tag GPDO472_475; /* offset: 0x07D8 size: 32 bit */
 3234           SIUL_GPDO_32B_tag GPDO476_479; /* offset: 0x07DC size: 32 bit */
 3235           SIUL_GPDO_32B_tag GPDO480_483; /* offset: 0x07E0 size: 32 bit */
 3236           SIUL_GPDO_32B_tag GPDO484_487; /* offset: 0x07E4 size: 32 bit */
 3237           SIUL_GPDO_32B_tag GPDO488_491; /* offset: 0x07E8 size: 32 bit */
 3238           SIUL_GPDO_32B_tag GPDO492_495; /* offset: 0x07EC size: 32 bit */
 3239           SIUL_GPDO_32B_tag GPDO496_499; /* offset: 0x07F0 size: 32 bit */
 3240           SIUL_GPDO_32B_tag GPDO500_503; /* offset: 0x07F4 size: 32 bit */
 3241           SIUL_GPDO_32B_tag GPDO504_507; /* offset: 0x07F8 size: 32 bit */
 3242           SIUL_GPDO_32B_tag GPDO508_511; /* offset: 0x07FC size: 32 bit */
 3243         };
 3244   
 3245         struct {
 3246           /* GPDO - GPIO Pad Data Output Register */
 3247           SIUL_GPDO_8B_tag GPDO0;        /* offset: 0x0600 size: 8 bit */
 3248           SIUL_GPDO_8B_tag GPDO1;        /* offset: 0x0601 size: 8 bit */
 3249           SIUL_GPDO_8B_tag GPDO2;        /* offset: 0x0602 size: 8 bit */
 3250           SIUL_GPDO_8B_tag GPDO3;        /* offset: 0x0603 size: 8 bit */
 3251           SIUL_GPDO_8B_tag GPDO4;        /* offset: 0x0604 size: 8 bit */
 3252           SIUL_GPDO_8B_tag GPDO5;        /* offset: 0x0605 size: 8 bit */
 3253           SIUL_GPDO_8B_tag GPDO6;        /* offset: 0x0606 size: 8 bit */
 3254           SIUL_GPDO_8B_tag GPDO7;        /* offset: 0x0607 size: 8 bit */
 3255           SIUL_GPDO_8B_tag GPDO8;        /* offset: 0x0608 size: 8 bit */
 3256           SIUL_GPDO_8B_tag GPDO9;        /* offset: 0x0609 size: 8 bit */
 3257           SIUL_GPDO_8B_tag GPDO10;       /* offset: 0x060A size: 8 bit */
 3258           SIUL_GPDO_8B_tag GPDO11;       /* offset: 0x060B size: 8 bit */
 3259           SIUL_GPDO_8B_tag GPDO12;       /* offset: 0x060C size: 8 bit */
 3260           SIUL_GPDO_8B_tag GPDO13;       /* offset: 0x060D size: 8 bit */
 3261           SIUL_GPDO_8B_tag GPDO14;       /* offset: 0x060E size: 8 bit */
 3262           SIUL_GPDO_8B_tag GPDO15;       /* offset: 0x060F size: 8 bit */
 3263           SIUL_GPDO_8B_tag GPDO16;       /* offset: 0x0610 size: 8 bit */
 3264           SIUL_GPDO_8B_tag GPDO17;       /* offset: 0x0611 size: 8 bit */
 3265           SIUL_GPDO_8B_tag GPDO18;       /* offset: 0x0612 size: 8 bit */
 3266           SIUL_GPDO_8B_tag GPDO19;       /* offset: 0x0613 size: 8 bit */
 3267           SIUL_GPDO_8B_tag GPDO20;       /* offset: 0x0614 size: 8 bit */
 3268           SIUL_GPDO_8B_tag GPDO21;       /* offset: 0x0615 size: 8 bit */
 3269           SIUL_GPDO_8B_tag GPDO22;       /* offset: 0x0616 size: 8 bit */
 3270           SIUL_GPDO_8B_tag GPDO23;       /* offset: 0x0617 size: 8 bit */
 3271           SIUL_GPDO_8B_tag GPDO24;       /* offset: 0x0618 size: 8 bit */
 3272           SIUL_GPDO_8B_tag GPDO25;       /* offset: 0x0619 size: 8 bit */
 3273           SIUL_GPDO_8B_tag GPDO26;       /* offset: 0x061A size: 8 bit */
 3274           SIUL_GPDO_8B_tag GPDO27;       /* offset: 0x061B size: 8 bit */
 3275           SIUL_GPDO_8B_tag GPDO28;       /* offset: 0x061C size: 8 bit */
 3276           SIUL_GPDO_8B_tag GPDO29;       /* offset: 0x061D size: 8 bit */
 3277           SIUL_GPDO_8B_tag GPDO30;       /* offset: 0x061E size: 8 bit */
 3278           SIUL_GPDO_8B_tag GPDO31;       /* offset: 0x061F size: 8 bit */
 3279           SIUL_GPDO_8B_tag GPDO32;       /* offset: 0x0620 size: 8 bit */
 3280           SIUL_GPDO_8B_tag GPDO33;       /* offset: 0x0621 size: 8 bit */
 3281           SIUL_GPDO_8B_tag GPDO34;       /* offset: 0x0622 size: 8 bit */
 3282           SIUL_GPDO_8B_tag GPDO35;       /* offset: 0x0623 size: 8 bit */
 3283           SIUL_GPDO_8B_tag GPDO36;       /* offset: 0x0624 size: 8 bit */
 3284           SIUL_GPDO_8B_tag GPDO37;       /* offset: 0x0625 size: 8 bit */
 3285           SIUL_GPDO_8B_tag GPDO38;       /* offset: 0x0626 size: 8 bit */
 3286           SIUL_GPDO_8B_tag GPDO39;       /* offset: 0x0627 size: 8 bit */
 3287           SIUL_GPDO_8B_tag GPDO40;       /* offset: 0x0628 size: 8 bit */
 3288           SIUL_GPDO_8B_tag GPDO41;       /* offset: 0x0629 size: 8 bit */
 3289           SIUL_GPDO_8B_tag GPDO42;       /* offset: 0x062A size: 8 bit */
 3290           SIUL_GPDO_8B_tag GPDO43;       /* offset: 0x062B size: 8 bit */
 3291           SIUL_GPDO_8B_tag GPDO44;       /* offset: 0x062C size: 8 bit */
 3292           SIUL_GPDO_8B_tag GPDO45;       /* offset: 0x062D size: 8 bit */
 3293           SIUL_GPDO_8B_tag GPDO46;       /* offset: 0x062E size: 8 bit */
 3294           SIUL_GPDO_8B_tag GPDO47;       /* offset: 0x062F size: 8 bit */
 3295           SIUL_GPDO_8B_tag GPDO48;       /* offset: 0x0630 size: 8 bit */
 3296           SIUL_GPDO_8B_tag GPDO49;       /* offset: 0x0631 size: 8 bit */
 3297           SIUL_GPDO_8B_tag GPDO50;       /* offset: 0x0632 size: 8 bit */
 3298           SIUL_GPDO_8B_tag GPDO51;       /* offset: 0x0633 size: 8 bit */
 3299           SIUL_GPDO_8B_tag GPDO52;       /* offset: 0x0634 size: 8 bit */
 3300           SIUL_GPDO_8B_tag GPDO53;       /* offset: 0x0635 size: 8 bit */
 3301           SIUL_GPDO_8B_tag GPDO54;       /* offset: 0x0636 size: 8 bit */
 3302           SIUL_GPDO_8B_tag GPDO55;       /* offset: 0x0637 size: 8 bit */
 3303           SIUL_GPDO_8B_tag GPDO56;       /* offset: 0x0638 size: 8 bit */
 3304           SIUL_GPDO_8B_tag GPDO57;       /* offset: 0x0639 size: 8 bit */
 3305           SIUL_GPDO_8B_tag GPDO58;       /* offset: 0x063A size: 8 bit */
 3306           SIUL_GPDO_8B_tag GPDO59;       /* offset: 0x063B size: 8 bit */
 3307           SIUL_GPDO_8B_tag GPDO60;       /* offset: 0x063C size: 8 bit */
 3308           SIUL_GPDO_8B_tag GPDO61;       /* offset: 0x063D size: 8 bit */
 3309           SIUL_GPDO_8B_tag GPDO62;       /* offset: 0x063E size: 8 bit */
 3310           SIUL_GPDO_8B_tag GPDO63;       /* offset: 0x063F size: 8 bit */
 3311           SIUL_GPDO_8B_tag GPDO64;       /* offset: 0x0640 size: 8 bit */
 3312           SIUL_GPDO_8B_tag GPDO65;       /* offset: 0x0641 size: 8 bit */
 3313           SIUL_GPDO_8B_tag GPDO66;       /* offset: 0x0642 size: 8 bit */
 3314           SIUL_GPDO_8B_tag GPDO67;       /* offset: 0x0643 size: 8 bit */
 3315           SIUL_GPDO_8B_tag GPDO68;       /* offset: 0x0644 size: 8 bit */
 3316           SIUL_GPDO_8B_tag GPDO69;       /* offset: 0x0645 size: 8 bit */
 3317           SIUL_GPDO_8B_tag GPDO70;       /* offset: 0x0646 size: 8 bit */
 3318           SIUL_GPDO_8B_tag GPDO71;       /* offset: 0x0647 size: 8 bit */
 3319           SIUL_GPDO_8B_tag GPDO72;       /* offset: 0x0648 size: 8 bit */
 3320           SIUL_GPDO_8B_tag GPDO73;       /* offset: 0x0649 size: 8 bit */
 3321           SIUL_GPDO_8B_tag GPDO74;       /* offset: 0x064A size: 8 bit */
 3322           SIUL_GPDO_8B_tag GPDO75;       /* offset: 0x064B size: 8 bit */
 3323           SIUL_GPDO_8B_tag GPDO76;       /* offset: 0x064C size: 8 bit */
 3324           SIUL_GPDO_8B_tag GPDO77;       /* offset: 0x064D size: 8 bit */
 3325           SIUL_GPDO_8B_tag GPDO78;       /* offset: 0x064E size: 8 bit */
 3326           SIUL_GPDO_8B_tag GPDO79;       /* offset: 0x064F size: 8 bit */
 3327           SIUL_GPDO_8B_tag GPDO80;       /* offset: 0x0650 size: 8 bit */
 3328           SIUL_GPDO_8B_tag GPDO81;       /* offset: 0x0651 size: 8 bit */
 3329           SIUL_GPDO_8B_tag GPDO82;       /* offset: 0x0652 size: 8 bit */
 3330           SIUL_GPDO_8B_tag GPDO83;       /* offset: 0x0653 size: 8 bit */
 3331           SIUL_GPDO_8B_tag GPDO84;       /* offset: 0x0654 size: 8 bit */
 3332           SIUL_GPDO_8B_tag GPDO85;       /* offset: 0x0655 size: 8 bit */
 3333           SIUL_GPDO_8B_tag GPDO86;       /* offset: 0x0656 size: 8 bit */
 3334           SIUL_GPDO_8B_tag GPDO87;       /* offset: 0x0657 size: 8 bit */
 3335           SIUL_GPDO_8B_tag GPDO88;       /* offset: 0x0658 size: 8 bit */
 3336           SIUL_GPDO_8B_tag GPDO89;       /* offset: 0x0659 size: 8 bit */
 3337           SIUL_GPDO_8B_tag GPDO90;       /* offset: 0x065A size: 8 bit */
 3338           SIUL_GPDO_8B_tag GPDO91;       /* offset: 0x065B size: 8 bit */
 3339           SIUL_GPDO_8B_tag GPDO92;       /* offset: 0x065C size: 8 bit */
 3340           SIUL_GPDO_8B_tag GPDO93;       /* offset: 0x065D size: 8 bit */
 3341           SIUL_GPDO_8B_tag GPDO94;       /* offset: 0x065E size: 8 bit */
 3342           SIUL_GPDO_8B_tag GPDO95;       /* offset: 0x065F size: 8 bit */
 3343           SIUL_GPDO_8B_tag GPDO96;       /* offset: 0x0660 size: 8 bit */
 3344           SIUL_GPDO_8B_tag GPDO97;       /* offset: 0x0661 size: 8 bit */
 3345           SIUL_GPDO_8B_tag GPDO98;       /* offset: 0x0662 size: 8 bit */
 3346           SIUL_GPDO_8B_tag GPDO99;       /* offset: 0x0663 size: 8 bit */
 3347           SIUL_GPDO_8B_tag GPDO100;      /* offset: 0x0664 size: 8 bit */
 3348           SIUL_GPDO_8B_tag GPDO101;      /* offset: 0x0665 size: 8 bit */
 3349           SIUL_GPDO_8B_tag GPDO102;      /* offset: 0x0666 size: 8 bit */
 3350           SIUL_GPDO_8B_tag GPDO103;      /* offset: 0x0667 size: 8 bit */
 3351           SIUL_GPDO_8B_tag GPDO104;      /* offset: 0x0668 size: 8 bit */
 3352           SIUL_GPDO_8B_tag GPDO105;      /* offset: 0x0669 size: 8 bit */
 3353           SIUL_GPDO_8B_tag GPDO106;      /* offset: 0x066A size: 8 bit */
 3354           SIUL_GPDO_8B_tag GPDO107;      /* offset: 0x066B size: 8 bit */
 3355           SIUL_GPDO_8B_tag GPDO108;      /* offset: 0x066C size: 8 bit */
 3356           SIUL_GPDO_8B_tag GPDO109;      /* offset: 0x066D size: 8 bit */
 3357           SIUL_GPDO_8B_tag GPDO110;      /* offset: 0x066E size: 8 bit */
 3358           SIUL_GPDO_8B_tag GPDO111;      /* offset: 0x066F size: 8 bit */
 3359           SIUL_GPDO_8B_tag GPDO112;      /* offset: 0x0670 size: 8 bit */
 3360           SIUL_GPDO_8B_tag GPDO113;      /* offset: 0x0671 size: 8 bit */
 3361           SIUL_GPDO_8B_tag GPDO114;      /* offset: 0x0672 size: 8 bit */
 3362           SIUL_GPDO_8B_tag GPDO115;      /* offset: 0x0673 size: 8 bit */
 3363           SIUL_GPDO_8B_tag GPDO116;      /* offset: 0x0674 size: 8 bit */
 3364           SIUL_GPDO_8B_tag GPDO117;      /* offset: 0x0675 size: 8 bit */
 3365           SIUL_GPDO_8B_tag GPDO118;      /* offset: 0x0676 size: 8 bit */
 3366           SIUL_GPDO_8B_tag GPDO119;      /* offset: 0x0677 size: 8 bit */
 3367           SIUL_GPDO_8B_tag GPDO120;      /* offset: 0x0678 size: 8 bit */
 3368           SIUL_GPDO_8B_tag GPDO121;      /* offset: 0x0679 size: 8 bit */
 3369           SIUL_GPDO_8B_tag GPDO122;      /* offset: 0x067A size: 8 bit */
 3370           SIUL_GPDO_8B_tag GPDO123;      /* offset: 0x067B size: 8 bit */
 3371           SIUL_GPDO_8B_tag GPDO124;      /* offset: 0x067C size: 8 bit */
 3372           SIUL_GPDO_8B_tag GPDO125;      /* offset: 0x067D size: 8 bit */
 3373           SIUL_GPDO_8B_tag GPDO126;      /* offset: 0x067E size: 8 bit */
 3374           SIUL_GPDO_8B_tag GPDO127;      /* offset: 0x067F size: 8 bit */
 3375           SIUL_GPDO_8B_tag GPDO128;      /* offset: 0x0680 size: 8 bit */
 3376           SIUL_GPDO_8B_tag GPDO129;      /* offset: 0x0681 size: 8 bit */
 3377           SIUL_GPDO_8B_tag GPDO130;      /* offset: 0x0682 size: 8 bit */
 3378           SIUL_GPDO_8B_tag GPDO131;      /* offset: 0x0683 size: 8 bit */
 3379           SIUL_GPDO_8B_tag GPDO132;      /* offset: 0x0684 size: 8 bit */
 3380           SIUL_GPDO_8B_tag GPDO133;      /* offset: 0x0685 size: 8 bit */
 3381           SIUL_GPDO_8B_tag GPDO134;      /* offset: 0x0686 size: 8 bit */
 3382           SIUL_GPDO_8B_tag GPDO135;      /* offset: 0x0687 size: 8 bit */
 3383           SIUL_GPDO_8B_tag GPDO136;      /* offset: 0x0688 size: 8 bit */
 3384           SIUL_GPDO_8B_tag GPDO137;      /* offset: 0x0689 size: 8 bit */
 3385           SIUL_GPDO_8B_tag GPDO138;      /* offset: 0x068A size: 8 bit */
 3386           SIUL_GPDO_8B_tag GPDO139;      /* offset: 0x068B size: 8 bit */
 3387           SIUL_GPDO_8B_tag GPDO140;      /* offset: 0x068C size: 8 bit */
 3388           SIUL_GPDO_8B_tag GPDO141;      /* offset: 0x068D size: 8 bit */
 3389           SIUL_GPDO_8B_tag GPDO142;      /* offset: 0x068E size: 8 bit */
 3390           SIUL_GPDO_8B_tag GPDO143;      /* offset: 0x068F size: 8 bit */
 3391           SIUL_GPDO_8B_tag GPDO144;      /* offset: 0x0690 size: 8 bit */
 3392           SIUL_GPDO_8B_tag GPDO145;      /* offset: 0x0691 size: 8 bit */
 3393           SIUL_GPDO_8B_tag GPDO146;      /* offset: 0x0692 size: 8 bit */
 3394           SIUL_GPDO_8B_tag GPDO147;      /* offset: 0x0693 size: 8 bit */
 3395           SIUL_GPDO_8B_tag GPDO148;      /* offset: 0x0694 size: 8 bit */
 3396           SIUL_GPDO_8B_tag GPDO149;      /* offset: 0x0695 size: 8 bit */
 3397           SIUL_GPDO_8B_tag GPDO150;      /* offset: 0x0696 size: 8 bit */
 3398           SIUL_GPDO_8B_tag GPDO151;      /* offset: 0x0697 size: 8 bit */
 3399           SIUL_GPDO_8B_tag GPDO152;      /* offset: 0x0698 size: 8 bit */
 3400           SIUL_GPDO_8B_tag GPDO153;      /* offset: 0x0699 size: 8 bit */
 3401           SIUL_GPDO_8B_tag GPDO154;      /* offset: 0x069A size: 8 bit */
 3402           SIUL_GPDO_8B_tag GPDO155;      /* offset: 0x069B size: 8 bit */
 3403           SIUL_GPDO_8B_tag GPDO156;      /* offset: 0x069C size: 8 bit */
 3404           SIUL_GPDO_8B_tag GPDO157;      /* offset: 0x069D size: 8 bit */
 3405           SIUL_GPDO_8B_tag GPDO158;      /* offset: 0x069E size: 8 bit */
 3406           SIUL_GPDO_8B_tag GPDO159;      /* offset: 0x069F size: 8 bit */
 3407           SIUL_GPDO_8B_tag GPDO160;      /* offset: 0x06A0 size: 8 bit */
 3408           SIUL_GPDO_8B_tag GPDO161;      /* offset: 0x06A1 size: 8 bit */
 3409           SIUL_GPDO_8B_tag GPDO162;      /* offset: 0x06A2 size: 8 bit */
 3410           SIUL_GPDO_8B_tag GPDO163;      /* offset: 0x06A3 size: 8 bit */
 3411           SIUL_GPDO_8B_tag GPDO164;      /* offset: 0x06A4 size: 8 bit */
 3412           SIUL_GPDO_8B_tag GPDO165;      /* offset: 0x06A5 size: 8 bit */
 3413           SIUL_GPDO_8B_tag GPDO166;      /* offset: 0x06A6 size: 8 bit */
 3414           SIUL_GPDO_8B_tag GPDO167;      /* offset: 0x06A7 size: 8 bit */
 3415           SIUL_GPDO_8B_tag GPDO168;      /* offset: 0x06A8 size: 8 bit */
 3416           SIUL_GPDO_8B_tag GPDO169;      /* offset: 0x06A9 size: 8 bit */
 3417           SIUL_GPDO_8B_tag GPDO170;      /* offset: 0x06AA size: 8 bit */
 3418           SIUL_GPDO_8B_tag GPDO171;      /* offset: 0x06AB size: 8 bit */
 3419           SIUL_GPDO_8B_tag GPDO172;      /* offset: 0x06AC size: 8 bit */
 3420           SIUL_GPDO_8B_tag GPDO173;      /* offset: 0x06AD size: 8 bit */
 3421           SIUL_GPDO_8B_tag GPDO174;      /* offset: 0x06AE size: 8 bit */
 3422           SIUL_GPDO_8B_tag GPDO175;      /* offset: 0x06AF size: 8 bit */
 3423           SIUL_GPDO_8B_tag GPDO176;      /* offset: 0x06B0 size: 8 bit */
 3424           SIUL_GPDO_8B_tag GPDO177;      /* offset: 0x06B1 size: 8 bit */
 3425           SIUL_GPDO_8B_tag GPDO178;      /* offset: 0x06B2 size: 8 bit */
 3426           SIUL_GPDO_8B_tag GPDO179;      /* offset: 0x06B3 size: 8 bit */
 3427           SIUL_GPDO_8B_tag GPDO180;      /* offset: 0x06B4 size: 8 bit */
 3428           SIUL_GPDO_8B_tag GPDO181;      /* offset: 0x06B5 size: 8 bit */
 3429           SIUL_GPDO_8B_tag GPDO182;      /* offset: 0x06B6 size: 8 bit */
 3430           SIUL_GPDO_8B_tag GPDO183;      /* offset: 0x06B7 size: 8 bit */
 3431           SIUL_GPDO_8B_tag GPDO184;      /* offset: 0x06B8 size: 8 bit */
 3432           SIUL_GPDO_8B_tag GPDO185;      /* offset: 0x06B9 size: 8 bit */
 3433           SIUL_GPDO_8B_tag GPDO186;      /* offset: 0x06BA size: 8 bit */
 3434           SIUL_GPDO_8B_tag GPDO187;      /* offset: 0x06BB size: 8 bit */
 3435           SIUL_GPDO_8B_tag GPDO188;      /* offset: 0x06BC size: 8 bit */
 3436           SIUL_GPDO_8B_tag GPDO189;      /* offset: 0x06BD size: 8 bit */
 3437           SIUL_GPDO_8B_tag GPDO190;      /* offset: 0x06BE size: 8 bit */
 3438           SIUL_GPDO_8B_tag GPDO191;      /* offset: 0x06BF size: 8 bit */
 3439           SIUL_GPDO_8B_tag GPDO192;      /* offset: 0x06C0 size: 8 bit */
 3440           SIUL_GPDO_8B_tag GPDO193;      /* offset: 0x06C1 size: 8 bit */
 3441           SIUL_GPDO_8B_tag GPDO194;      /* offset: 0x06C2 size: 8 bit */
 3442           SIUL_GPDO_8B_tag GPDO195;      /* offset: 0x06C3 size: 8 bit */
 3443           SIUL_GPDO_8B_tag GPDO196;      /* offset: 0x06C4 size: 8 bit */
 3444           SIUL_GPDO_8B_tag GPDO197;      /* offset: 0x06C5 size: 8 bit */
 3445           SIUL_GPDO_8B_tag GPDO198;      /* offset: 0x06C6 size: 8 bit */
 3446           SIUL_GPDO_8B_tag GPDO199;      /* offset: 0x06C7 size: 8 bit */
 3447           SIUL_GPDO_8B_tag GPDO200;      /* offset: 0x06C8 size: 8 bit */
 3448           SIUL_GPDO_8B_tag GPDO201;      /* offset: 0x06C9 size: 8 bit */
 3449           SIUL_GPDO_8B_tag GPDO202;      /* offset: 0x06CA size: 8 bit */
 3450           SIUL_GPDO_8B_tag GPDO203;      /* offset: 0x06CB size: 8 bit */
 3451           SIUL_GPDO_8B_tag GPDO204;      /* offset: 0x06CC size: 8 bit */
 3452           SIUL_GPDO_8B_tag GPDO205;      /* offset: 0x06CD size: 8 bit */
 3453           SIUL_GPDO_8B_tag GPDO206;      /* offset: 0x06CE size: 8 bit */
 3454           SIUL_GPDO_8B_tag GPDO207;      /* offset: 0x06CF size: 8 bit */
 3455           SIUL_GPDO_8B_tag GPDO208;      /* offset: 0x06D0 size: 8 bit */
 3456           SIUL_GPDO_8B_tag GPDO209;      /* offset: 0x06D1 size: 8 bit */
 3457           SIUL_GPDO_8B_tag GPDO210;      /* offset: 0x06D2 size: 8 bit */
 3458           SIUL_GPDO_8B_tag GPDO211;      /* offset: 0x06D3 size: 8 bit */
 3459           SIUL_GPDO_8B_tag GPDO212;      /* offset: 0x06D4 size: 8 bit */
 3460           SIUL_GPDO_8B_tag GPDO213;      /* offset: 0x06D5 size: 8 bit */
 3461           SIUL_GPDO_8B_tag GPDO214;      /* offset: 0x06D6 size: 8 bit */
 3462           SIUL_GPDO_8B_tag GPDO215;      /* offset: 0x06D7 size: 8 bit */
 3463           SIUL_GPDO_8B_tag GPDO216;      /* offset: 0x06D8 size: 8 bit */
 3464           SIUL_GPDO_8B_tag GPDO217;      /* offset: 0x06D9 size: 8 bit */
 3465           SIUL_GPDO_8B_tag GPDO218;      /* offset: 0x06DA size: 8 bit */
 3466           SIUL_GPDO_8B_tag GPDO219;      /* offset: 0x06DB size: 8 bit */
 3467           SIUL_GPDO_8B_tag GPDO220;      /* offset: 0x06DC size: 8 bit */
 3468           SIUL_GPDO_8B_tag GPDO221;      /* offset: 0x06DD size: 8 bit */
 3469           SIUL_GPDO_8B_tag GPDO222;      /* offset: 0x06DE size: 8 bit */
 3470           SIUL_GPDO_8B_tag GPDO223;      /* offset: 0x06DF size: 8 bit */
 3471           SIUL_GPDO_8B_tag GPDO224;      /* offset: 0x06E0 size: 8 bit */
 3472           SIUL_GPDO_8B_tag GPDO225;      /* offset: 0x06E1 size: 8 bit */
 3473           SIUL_GPDO_8B_tag GPDO226;      /* offset: 0x06E2 size: 8 bit */
 3474           SIUL_GPDO_8B_tag GPDO227;      /* offset: 0x06E3 size: 8 bit */
 3475           SIUL_GPDO_8B_tag GPDO228;      /* offset: 0x06E4 size: 8 bit */
 3476           SIUL_GPDO_8B_tag GPDO229;      /* offset: 0x06E5 size: 8 bit */
 3477           SIUL_GPDO_8B_tag GPDO230;      /* offset: 0x06E6 size: 8 bit */
 3478           SIUL_GPDO_8B_tag GPDO231;      /* offset: 0x06E7 size: 8 bit */
 3479           SIUL_GPDO_8B_tag GPDO232;      /* offset: 0x06E8 size: 8 bit */
 3480           SIUL_GPDO_8B_tag GPDO233;      /* offset: 0x06E9 size: 8 bit */
 3481           SIUL_GPDO_8B_tag GPDO234;      /* offset: 0x06EA size: 8 bit */
 3482           SIUL_GPDO_8B_tag GPDO235;      /* offset: 0x06EB size: 8 bit */
 3483           SIUL_GPDO_8B_tag GPDO236;      /* offset: 0x06EC size: 8 bit */
 3484           SIUL_GPDO_8B_tag GPDO237;      /* offset: 0x06ED size: 8 bit */
 3485           SIUL_GPDO_8B_tag GPDO238;      /* offset: 0x06EE size: 8 bit */
 3486           SIUL_GPDO_8B_tag GPDO239;      /* offset: 0x06EF size: 8 bit */
 3487           SIUL_GPDO_8B_tag GPDO240;      /* offset: 0x06F0 size: 8 bit */
 3488           SIUL_GPDO_8B_tag GPDO241;      /* offset: 0x06F1 size: 8 bit */
 3489           SIUL_GPDO_8B_tag GPDO242;      /* offset: 0x06F2 size: 8 bit */
 3490           SIUL_GPDO_8B_tag GPDO243;      /* offset: 0x06F3 size: 8 bit */
 3491           SIUL_GPDO_8B_tag GPDO244;      /* offset: 0x06F4 size: 8 bit */
 3492           SIUL_GPDO_8B_tag GPDO245;      /* offset: 0x06F5 size: 8 bit */
 3493           SIUL_GPDO_8B_tag GPDO246;      /* offset: 0x06F6 size: 8 bit */
 3494           SIUL_GPDO_8B_tag GPDO247;      /* offset: 0x06F7 size: 8 bit */
 3495           SIUL_GPDO_8B_tag GPDO248;      /* offset: 0x06F8 size: 8 bit */
 3496           SIUL_GPDO_8B_tag GPDO249;      /* offset: 0x06F9 size: 8 bit */
 3497           SIUL_GPDO_8B_tag GPDO250;      /* offset: 0x06FA size: 8 bit */
 3498           SIUL_GPDO_8B_tag GPDO251;      /* offset: 0x06FB size: 8 bit */
 3499           SIUL_GPDO_8B_tag GPDO252;      /* offset: 0x06FC size: 8 bit */
 3500           SIUL_GPDO_8B_tag GPDO253;      /* offset: 0x06FD size: 8 bit */
 3501           SIUL_GPDO_8B_tag GPDO254;      /* offset: 0x06FE size: 8 bit */
 3502           SIUL_GPDO_8B_tag GPDO255;      /* offset: 0x06FF size: 8 bit */
 3503           SIUL_GPDO_8B_tag GPDO256;      /* offset: 0x0700 size: 8 bit */
 3504           SIUL_GPDO_8B_tag GPDO257;      /* offset: 0x0701 size: 8 bit */
 3505           SIUL_GPDO_8B_tag GPDO258;      /* offset: 0x0702 size: 8 bit */
 3506           SIUL_GPDO_8B_tag GPDO259;      /* offset: 0x0703 size: 8 bit */
 3507           SIUL_GPDO_8B_tag GPDO260;      /* offset: 0x0704 size: 8 bit */
 3508           SIUL_GPDO_8B_tag GPDO261;      /* offset: 0x0705 size: 8 bit */
 3509           SIUL_GPDO_8B_tag GPDO262;      /* offset: 0x0706 size: 8 bit */
 3510           SIUL_GPDO_8B_tag GPDO263;      /* offset: 0x0707 size: 8 bit */
 3511           SIUL_GPDO_8B_tag GPDO264;      /* offset: 0x0708 size: 8 bit */
 3512           SIUL_GPDO_8B_tag GPDO265;      /* offset: 0x0709 size: 8 bit */
 3513           SIUL_GPDO_8B_tag GPDO266;      /* offset: 0x070A size: 8 bit */
 3514           SIUL_GPDO_8B_tag GPDO267;      /* offset: 0x070B size: 8 bit */
 3515           SIUL_GPDO_8B_tag GPDO268;      /* offset: 0x070C size: 8 bit */
 3516           SIUL_GPDO_8B_tag GPDO269;      /* offset: 0x070D size: 8 bit */
 3517           SIUL_GPDO_8B_tag GPDO270;      /* offset: 0x070E size: 8 bit */
 3518           SIUL_GPDO_8B_tag GPDO271;      /* offset: 0x070F size: 8 bit */
 3519           SIUL_GPDO_8B_tag GPDO272;      /* offset: 0x0710 size: 8 bit */
 3520           SIUL_GPDO_8B_tag GPDO273;      /* offset: 0x0711 size: 8 bit */
 3521           SIUL_GPDO_8B_tag GPDO274;      /* offset: 0x0712 size: 8 bit */
 3522           SIUL_GPDO_8B_tag GPDO275;      /* offset: 0x0713 size: 8 bit */
 3523           SIUL_GPDO_8B_tag GPDO276;      /* offset: 0x0714 size: 8 bit */
 3524           SIUL_GPDO_8B_tag GPDO277;      /* offset: 0x0715 size: 8 bit */
 3525           SIUL_GPDO_8B_tag GPDO278;      /* offset: 0x0716 size: 8 bit */
 3526           SIUL_GPDO_8B_tag GPDO279;      /* offset: 0x0717 size: 8 bit */
 3527           SIUL_GPDO_8B_tag GPDO280;      /* offset: 0x0718 size: 8 bit */
 3528           SIUL_GPDO_8B_tag GPDO281;      /* offset: 0x0719 size: 8 bit */
 3529           SIUL_GPDO_8B_tag GPDO282;      /* offset: 0x071A size: 8 bit */
 3530           SIUL_GPDO_8B_tag GPDO283;      /* offset: 0x071B size: 8 bit */
 3531           SIUL_GPDO_8B_tag GPDO284;      /* offset: 0x071C size: 8 bit */
 3532           SIUL_GPDO_8B_tag GPDO285;      /* offset: 0x071D size: 8 bit */
 3533           SIUL_GPDO_8B_tag GPDO286;      /* offset: 0x071E size: 8 bit */
 3534           SIUL_GPDO_8B_tag GPDO287;      /* offset: 0x071F size: 8 bit */
 3535           SIUL_GPDO_8B_tag GPDO288;      /* offset: 0x0720 size: 8 bit */
 3536           SIUL_GPDO_8B_tag GPDO289;      /* offset: 0x0721 size: 8 bit */
 3537           SIUL_GPDO_8B_tag GPDO290;      /* offset: 0x0722 size: 8 bit */
 3538           SIUL_GPDO_8B_tag GPDO291;      /* offset: 0x0723 size: 8 bit */
 3539           SIUL_GPDO_8B_tag GPDO292;      /* offset: 0x0724 size: 8 bit */
 3540           SIUL_GPDO_8B_tag GPDO293;      /* offset: 0x0725 size: 8 bit */
 3541           SIUL_GPDO_8B_tag GPDO294;      /* offset: 0x0726 size: 8 bit */
 3542           SIUL_GPDO_8B_tag GPDO295;      /* offset: 0x0727 size: 8 bit */
 3543           SIUL_GPDO_8B_tag GPDO296;      /* offset: 0x0728 size: 8 bit */
 3544           SIUL_GPDO_8B_tag GPDO297;      /* offset: 0x0729 size: 8 bit */
 3545           SIUL_GPDO_8B_tag GPDO298;      /* offset: 0x072A size: 8 bit */
 3546           SIUL_GPDO_8B_tag GPDO299;      /* offset: 0x072B size: 8 bit */
 3547           SIUL_GPDO_8B_tag GPDO300;      /* offset: 0x072C size: 8 bit */
 3548           SIUL_GPDO_8B_tag GPDO301;      /* offset: 0x072D size: 8 bit */
 3549           SIUL_GPDO_8B_tag GPDO302;      /* offset: 0x072E size: 8 bit */
 3550           SIUL_GPDO_8B_tag GPDO303;      /* offset: 0x072F size: 8 bit */
 3551           SIUL_GPDO_8B_tag GPDO304;      /* offset: 0x0730 size: 8 bit */
 3552           SIUL_GPDO_8B_tag GPDO305;      /* offset: 0x0731 size: 8 bit */
 3553           SIUL_GPDO_8B_tag GPDO306;      /* offset: 0x0732 size: 8 bit */
 3554           SIUL_GPDO_8B_tag GPDO307;      /* offset: 0x0733 size: 8 bit */
 3555           SIUL_GPDO_8B_tag GPDO308;      /* offset: 0x0734 size: 8 bit */
 3556           SIUL_GPDO_8B_tag GPDO309;      /* offset: 0x0735 size: 8 bit */
 3557           SIUL_GPDO_8B_tag GPDO310;      /* offset: 0x0736 size: 8 bit */
 3558           SIUL_GPDO_8B_tag GPDO311;      /* offset: 0x0737 size: 8 bit */
 3559           SIUL_GPDO_8B_tag GPDO312;      /* offset: 0x0738 size: 8 bit */
 3560           SIUL_GPDO_8B_tag GPDO313;      /* offset: 0x0739 size: 8 bit */
 3561           SIUL_GPDO_8B_tag GPDO314;      /* offset: 0x073A size: 8 bit */
 3562           SIUL_GPDO_8B_tag GPDO315;      /* offset: 0x073B size: 8 bit */
 3563           SIUL_GPDO_8B_tag GPDO316;      /* offset: 0x073C size: 8 bit */
 3564           SIUL_GPDO_8B_tag GPDO317;      /* offset: 0x073D size: 8 bit */
 3565           SIUL_GPDO_8B_tag GPDO318;      /* offset: 0x073E size: 8 bit */
 3566           SIUL_GPDO_8B_tag GPDO319;      /* offset: 0x073F size: 8 bit */
 3567           SIUL_GPDO_8B_tag GPDO320;      /* offset: 0x0740 size: 8 bit */
 3568           SIUL_GPDO_8B_tag GPDO321;      /* offset: 0x0741 size: 8 bit */
 3569           SIUL_GPDO_8B_tag GPDO322;      /* offset: 0x0742 size: 8 bit */
 3570           SIUL_GPDO_8B_tag GPDO323;      /* offset: 0x0743 size: 8 bit */
 3571           SIUL_GPDO_8B_tag GPDO324;      /* offset: 0x0744 size: 8 bit */
 3572           SIUL_GPDO_8B_tag GPDO325;      /* offset: 0x0745 size: 8 bit */
 3573           SIUL_GPDO_8B_tag GPDO326;      /* offset: 0x0746 size: 8 bit */
 3574           SIUL_GPDO_8B_tag GPDO327;      /* offset: 0x0747 size: 8 bit */
 3575           SIUL_GPDO_8B_tag GPDO328;      /* offset: 0x0748 size: 8 bit */
 3576           SIUL_GPDO_8B_tag GPDO329;      /* offset: 0x0749 size: 8 bit */
 3577           SIUL_GPDO_8B_tag GPDO330;      /* offset: 0x074A size: 8 bit */
 3578           SIUL_GPDO_8B_tag GPDO331;      /* offset: 0x074B size: 8 bit */
 3579           SIUL_GPDO_8B_tag GPDO332;      /* offset: 0x074C size: 8 bit */
 3580           SIUL_GPDO_8B_tag GPDO333;      /* offset: 0x074D size: 8 bit */
 3581           SIUL_GPDO_8B_tag GPDO334;      /* offset: 0x074E size: 8 bit */
 3582           SIUL_GPDO_8B_tag GPDO335;      /* offset: 0x074F size: 8 bit */
 3583           SIUL_GPDO_8B_tag GPDO336;      /* offset: 0x0750 size: 8 bit */
 3584           SIUL_GPDO_8B_tag GPDO337;      /* offset: 0x0751 size: 8 bit */
 3585           SIUL_GPDO_8B_tag GPDO338;      /* offset: 0x0752 size: 8 bit */
 3586           SIUL_GPDO_8B_tag GPDO339;      /* offset: 0x0753 size: 8 bit */
 3587           SIUL_GPDO_8B_tag GPDO340;      /* offset: 0x0754 size: 8 bit */
 3588           SIUL_GPDO_8B_tag GPDO341;      /* offset: 0x0755 size: 8 bit */
 3589           SIUL_GPDO_8B_tag GPDO342;      /* offset: 0x0756 size: 8 bit */
 3590           SIUL_GPDO_8B_tag GPDO343;      /* offset: 0x0757 size: 8 bit */
 3591           SIUL_GPDO_8B_tag GPDO344;      /* offset: 0x0758 size: 8 bit */
 3592           SIUL_GPDO_8B_tag GPDO345;      /* offset: 0x0759 size: 8 bit */
 3593           SIUL_GPDO_8B_tag GPDO346;      /* offset: 0x075A size: 8 bit */
 3594           SIUL_GPDO_8B_tag GPDO347;      /* offset: 0x075B size: 8 bit */
 3595           SIUL_GPDO_8B_tag GPDO348;      /* offset: 0x075C size: 8 bit */
 3596           SIUL_GPDO_8B_tag GPDO349;      /* offset: 0x075D size: 8 bit */
 3597           SIUL_GPDO_8B_tag GPDO350;      /* offset: 0x075E size: 8 bit */
 3598           SIUL_GPDO_8B_tag GPDO351;      /* offset: 0x075F size: 8 bit */
 3599           SIUL_GPDO_8B_tag GPDO352;      /* offset: 0x0760 size: 8 bit */
 3600           SIUL_GPDO_8B_tag GPDO353;      /* offset: 0x0761 size: 8 bit */
 3601           SIUL_GPDO_8B_tag GPDO354;      /* offset: 0x0762 size: 8 bit */
 3602           SIUL_GPDO_8B_tag GPDO355;      /* offset: 0x0763 size: 8 bit */
 3603           SIUL_GPDO_8B_tag GPDO356;      /* offset: 0x0764 size: 8 bit */
 3604           SIUL_GPDO_8B_tag GPDO357;      /* offset: 0x0765 size: 8 bit */
 3605           SIUL_GPDO_8B_tag GPDO358;      /* offset: 0x0766 size: 8 bit */
 3606           SIUL_GPDO_8B_tag GPDO359;      /* offset: 0x0767 size: 8 bit */
 3607           SIUL_GPDO_8B_tag GPDO360;      /* offset: 0x0768 size: 8 bit */
 3608           SIUL_GPDO_8B_tag GPDO361;      /* offset: 0x0769 size: 8 bit */
 3609           SIUL_GPDO_8B_tag GPDO362;      /* offset: 0x076A size: 8 bit */
 3610           SIUL_GPDO_8B_tag GPDO363;      /* offset: 0x076B size: 8 bit */
 3611           SIUL_GPDO_8B_tag GPDO364;      /* offset: 0x076C size: 8 bit */
 3612           SIUL_GPDO_8B_tag GPDO365;      /* offset: 0x076D size: 8 bit */
 3613           SIUL_GPDO_8B_tag GPDO366;      /* offset: 0x076E size: 8 bit */
 3614           SIUL_GPDO_8B_tag GPDO367;      /* offset: 0x076F size: 8 bit */
 3615           SIUL_GPDO_8B_tag GPDO368;      /* offset: 0x0770 size: 8 bit */
 3616           SIUL_GPDO_8B_tag GPDO369;      /* offset: 0x0771 size: 8 bit */
 3617           SIUL_GPDO_8B_tag GPDO370;      /* offset: 0x0772 size: 8 bit */
 3618           SIUL_GPDO_8B_tag GPDO371;      /* offset: 0x0773 size: 8 bit */
 3619           SIUL_GPDO_8B_tag GPDO372;      /* offset: 0x0774 size: 8 bit */
 3620           SIUL_GPDO_8B_tag GPDO373;      /* offset: 0x0775 size: 8 bit */
 3621           SIUL_GPDO_8B_tag GPDO374;      /* offset: 0x0776 size: 8 bit */
 3622           SIUL_GPDO_8B_tag GPDO375;      /* offset: 0x0777 size: 8 bit */
 3623           SIUL_GPDO_8B_tag GPDO376;      /* offset: 0x0778 size: 8 bit */
 3624           SIUL_GPDO_8B_tag GPDO377;      /* offset: 0x0779 size: 8 bit */
 3625           SIUL_GPDO_8B_tag GPDO378;      /* offset: 0x077A size: 8 bit */
 3626           SIUL_GPDO_8B_tag GPDO379;      /* offset: 0x077B size: 8 bit */
 3627           SIUL_GPDO_8B_tag GPDO380;      /* offset: 0x077C size: 8 bit */
 3628           SIUL_GPDO_8B_tag GPDO381;      /* offset: 0x077D size: 8 bit */
 3629           SIUL_GPDO_8B_tag GPDO382;      /* offset: 0x077E size: 8 bit */
 3630           SIUL_GPDO_8B_tag GPDO383;      /* offset: 0x077F size: 8 bit */
 3631           SIUL_GPDO_8B_tag GPDO384;      /* offset: 0x0780 size: 8 bit */
 3632           SIUL_GPDO_8B_tag GPDO385;      /* offset: 0x0781 size: 8 bit */
 3633           SIUL_GPDO_8B_tag GPDO386;      /* offset: 0x0782 size: 8 bit */
 3634           SIUL_GPDO_8B_tag GPDO387;      /* offset: 0x0783 size: 8 bit */
 3635           SIUL_GPDO_8B_tag GPDO388;      /* offset: 0x0784 size: 8 bit */
 3636           SIUL_GPDO_8B_tag GPDO389;      /* offset: 0x0785 size: 8 bit */
 3637           SIUL_GPDO_8B_tag GPDO390;      /* offset: 0x0786 size: 8 bit */
 3638           SIUL_GPDO_8B_tag GPDO391;      /* offset: 0x0787 size: 8 bit */
 3639           SIUL_GPDO_8B_tag GPDO392;      /* offset: 0x0788 size: 8 bit */
 3640           SIUL_GPDO_8B_tag GPDO393;      /* offset: 0x0789 size: 8 bit */
 3641           SIUL_GPDO_8B_tag GPDO394;      /* offset: 0x078A size: 8 bit */
 3642           SIUL_GPDO_8B_tag GPDO395;      /* offset: 0x078B size: 8 bit */
 3643           SIUL_GPDO_8B_tag GPDO396;      /* offset: 0x078C size: 8 bit */
 3644           SIUL_GPDO_8B_tag GPDO397;      /* offset: 0x078D size: 8 bit */
 3645           SIUL_GPDO_8B_tag GPDO398;      /* offset: 0x078E size: 8 bit */
 3646           SIUL_GPDO_8B_tag GPDO399;      /* offset: 0x078F size: 8 bit */
 3647           SIUL_GPDO_8B_tag GPDO400;      /* offset: 0x0790 size: 8 bit */
 3648           SIUL_GPDO_8B_tag GPDO401;      /* offset: 0x0791 size: 8 bit */
 3649           SIUL_GPDO_8B_tag GPDO402;      /* offset: 0x0792 size: 8 bit */
 3650           SIUL_GPDO_8B_tag GPDO403;      /* offset: 0x0793 size: 8 bit */
 3651           SIUL_GPDO_8B_tag GPDO404;      /* offset: 0x0794 size: 8 bit */
 3652           SIUL_GPDO_8B_tag GPDO405;      /* offset: 0x0795 size: 8 bit */
 3653           SIUL_GPDO_8B_tag GPDO406;      /* offset: 0x0796 size: 8 bit */
 3654           SIUL_GPDO_8B_tag GPDO407;      /* offset: 0x0797 size: 8 bit */
 3655           SIUL_GPDO_8B_tag GPDO408;      /* offset: 0x0798 size: 8 bit */
 3656           SIUL_GPDO_8B_tag GPDO409;      /* offset: 0x0799 size: 8 bit */
 3657           SIUL_GPDO_8B_tag GPDO410;      /* offset: 0x079A size: 8 bit */
 3658           SIUL_GPDO_8B_tag GPDO411;      /* offset: 0x079B size: 8 bit */
 3659           SIUL_GPDO_8B_tag GPDO412;      /* offset: 0x079C size: 8 bit */
 3660           SIUL_GPDO_8B_tag GPDO413;      /* offset: 0x079D size: 8 bit */
 3661           SIUL_GPDO_8B_tag GPDO414;      /* offset: 0x079E size: 8 bit */
 3662           SIUL_GPDO_8B_tag GPDO415;      /* offset: 0x079F size: 8 bit */
 3663           SIUL_GPDO_8B_tag GPDO416;      /* offset: 0x07A0 size: 8 bit */
 3664           SIUL_GPDO_8B_tag GPDO417;      /* offset: 0x07A1 size: 8 bit */
 3665           SIUL_GPDO_8B_tag GPDO418;      /* offset: 0x07A2 size: 8 bit */
 3666           SIUL_GPDO_8B_tag GPDO419;      /* offset: 0x07A3 size: 8 bit */
 3667           SIUL_GPDO_8B_tag GPDO420;      /* offset: 0x07A4 size: 8 bit */
 3668           SIUL_GPDO_8B_tag GPDO421;      /* offset: 0x07A5 size: 8 bit */
 3669           SIUL_GPDO_8B_tag GPDO422;      /* offset: 0x07A6 size: 8 bit */
 3670           SIUL_GPDO_8B_tag GPDO423;      /* offset: 0x07A7 size: 8 bit */
 3671           SIUL_GPDO_8B_tag GPDO424;      /* offset: 0x07A8 size: 8 bit */
 3672           SIUL_GPDO_8B_tag GPDO425;      /* offset: 0x07A9 size: 8 bit */
 3673           SIUL_GPDO_8B_tag GPDO426;      /* offset: 0x07AA size: 8 bit */
 3674           SIUL_GPDO_8B_tag GPDO427;      /* offset: 0x07AB size: 8 bit */
 3675           SIUL_GPDO_8B_tag GPDO428;      /* offset: 0x07AC size: 8 bit */
 3676           SIUL_GPDO_8B_tag GPDO429;      /* offset: 0x07AD size: 8 bit */
 3677           SIUL_GPDO_8B_tag GPDO430;      /* offset: 0x07AE size: 8 bit */
 3678           SIUL_GPDO_8B_tag GPDO431;      /* offset: 0x07AF size: 8 bit */
 3679           SIUL_GPDO_8B_tag GPDO432;      /* offset: 0x07B0 size: 8 bit */
 3680           SIUL_GPDO_8B_tag GPDO433;      /* offset: 0x07B1 size: 8 bit */
 3681           SIUL_GPDO_8B_tag GPDO434;      /* offset: 0x07B2 size: 8 bit */
 3682           SIUL_GPDO_8B_tag GPDO435;      /* offset: 0x07B3 size: 8 bit */
 3683           SIUL_GPDO_8B_tag GPDO436;      /* offset: 0x07B4 size: 8 bit */
 3684           SIUL_GPDO_8B_tag GPDO437;      /* offset: 0x07B5 size: 8 bit */
 3685           SIUL_GPDO_8B_tag GPDO438;      /* offset: 0x07B6 size: 8 bit */
 3686           SIUL_GPDO_8B_tag GPDO439;      /* offset: 0x07B7 size: 8 bit */
 3687           SIUL_GPDO_8B_tag GPDO440;      /* offset: 0x07B8 size: 8 bit */
 3688           SIUL_GPDO_8B_tag GPDO441;      /* offset: 0x07B9 size: 8 bit */
 3689           SIUL_GPDO_8B_tag GPDO442;      /* offset: 0x07BA size: 8 bit */
 3690           SIUL_GPDO_8B_tag GPDO443;      /* offset: 0x07BB size: 8 bit */
 3691           SIUL_GPDO_8B_tag GPDO444;      /* offset: 0x07BC size: 8 bit */
 3692           SIUL_GPDO_8B_tag GPDO445;      /* offset: 0x07BD size: 8 bit */
 3693           SIUL_GPDO_8B_tag GPDO446;      /* offset: 0x07BE size: 8 bit */
 3694           SIUL_GPDO_8B_tag GPDO447;      /* offset: 0x07BF size: 8 bit */
 3695           SIUL_GPDO_8B_tag GPDO448;      /* offset: 0x07C0 size: 8 bit */
 3696           SIUL_GPDO_8B_tag GPDO449;      /* offset: 0x07C1 size: 8 bit */
 3697           SIUL_GPDO_8B_tag GPDO450;      /* offset: 0x07C2 size: 8 bit */
 3698           SIUL_GPDO_8B_tag GPDO451;      /* offset: 0x07C3 size: 8 bit */
 3699           SIUL_GPDO_8B_tag GPDO452;      /* offset: 0x07C4 size: 8 bit */
 3700           SIUL_GPDO_8B_tag GPDO453;      /* offset: 0x07C5 size: 8 bit */
 3701           SIUL_GPDO_8B_tag GPDO454;      /* offset: 0x07C6 size: 8 bit */
 3702           SIUL_GPDO_8B_tag GPDO455;      /* offset: 0x07C7 size: 8 bit */
 3703           SIUL_GPDO_8B_tag GPDO456;      /* offset: 0x07C8 size: 8 bit */
 3704           SIUL_GPDO_8B_tag GPDO457;      /* offset: 0x07C9 size: 8 bit */
 3705           SIUL_GPDO_8B_tag GPDO458;      /* offset: 0x07CA size: 8 bit */
 3706           SIUL_GPDO_8B_tag GPDO459;      /* offset: 0x07CB size: 8 bit */
 3707           SIUL_GPDO_8B_tag GPDO460;      /* offset: 0x07CC size: 8 bit */
 3708           SIUL_GPDO_8B_tag GPDO461;      /* offset: 0x07CD size: 8 bit */
 3709           SIUL_GPDO_8B_tag GPDO462;      /* offset: 0x07CE size: 8 bit */
 3710           SIUL_GPDO_8B_tag GPDO463;      /* offset: 0x07CF size: 8 bit */
 3711           SIUL_GPDO_8B_tag GPDO464;      /* offset: 0x07D0 size: 8 bit */
 3712           SIUL_GPDO_8B_tag GPDO465;      /* offset: 0x07D1 size: 8 bit */
 3713           SIUL_GPDO_8B_tag GPDO466;      /* offset: 0x07D2 size: 8 bit */
 3714           SIUL_GPDO_8B_tag GPDO467;      /* offset: 0x07D3 size: 8 bit */
 3715           SIUL_GPDO_8B_tag GPDO468;      /* offset: 0x07D4 size: 8 bit */
 3716           SIUL_GPDO_8B_tag GPDO469;      /* offset: 0x07D5 size: 8 bit */
 3717           SIUL_GPDO_8B_tag GPDO470;      /* offset: 0x07D6 size: 8 bit */
 3718           SIUL_GPDO_8B_tag GPDO471;      /* offset: 0x07D7 size: 8 bit */
 3719           SIUL_GPDO_8B_tag GPDO472;      /* offset: 0x07D8 size: 8 bit */
 3720           SIUL_GPDO_8B_tag GPDO473;      /* offset: 0x07D9 size: 8 bit */
 3721           SIUL_GPDO_8B_tag GPDO474;      /* offset: 0x07DA size: 8 bit */
 3722           SIUL_GPDO_8B_tag GPDO475;      /* offset: 0x07DB size: 8 bit */
 3723           SIUL_GPDO_8B_tag GPDO476;      /* offset: 0x07DC size: 8 bit */
 3724           SIUL_GPDO_8B_tag GPDO477;      /* offset: 0x07DD size: 8 bit */
 3725           SIUL_GPDO_8B_tag GPDO478;      /* offset: 0x07DE size: 8 bit */
 3726           SIUL_GPDO_8B_tag GPDO479;      /* offset: 0x07DF size: 8 bit */
 3727           SIUL_GPDO_8B_tag GPDO480;      /* offset: 0x07E0 size: 8 bit */
 3728           SIUL_GPDO_8B_tag GPDO481;      /* offset: 0x07E1 size: 8 bit */
 3729           SIUL_GPDO_8B_tag GPDO482;      /* offset: 0x07E2 size: 8 bit */
 3730           SIUL_GPDO_8B_tag GPDO483;      /* offset: 0x07E3 size: 8 bit */
 3731           SIUL_GPDO_8B_tag GPDO484;      /* offset: 0x07E4 size: 8 bit */
 3732           SIUL_GPDO_8B_tag GPDO485;      /* offset: 0x07E5 size: 8 bit */
 3733           SIUL_GPDO_8B_tag GPDO486;      /* offset: 0x07E6 size: 8 bit */
 3734           SIUL_GPDO_8B_tag GPDO487;      /* offset: 0x07E7 size: 8 bit */
 3735           SIUL_GPDO_8B_tag GPDO488;      /* offset: 0x07E8 size: 8 bit */
 3736           SIUL_GPDO_8B_tag GPDO489;      /* offset: 0x07E9 size: 8 bit */
 3737           SIUL_GPDO_8B_tag GPDO490;      /* offset: 0x07EA size: 8 bit */
 3738           SIUL_GPDO_8B_tag GPDO491;      /* offset: 0x07EB size: 8 bit */
 3739           SIUL_GPDO_8B_tag GPDO492;      /* offset: 0x07EC size: 8 bit */
 3740           SIUL_GPDO_8B_tag GPDO493;      /* offset: 0x07ED size: 8 bit */
 3741           SIUL_GPDO_8B_tag GPDO494;      /* offset: 0x07EE size: 8 bit */
 3742           SIUL_GPDO_8B_tag GPDO495;      /* offset: 0x07EF size: 8 bit */
 3743           SIUL_GPDO_8B_tag GPDO496;      /* offset: 0x07F0 size: 8 bit */
 3744           SIUL_GPDO_8B_tag GPDO497;      /* offset: 0x07F1 size: 8 bit */
 3745           SIUL_GPDO_8B_tag GPDO498;      /* offset: 0x07F2 size: 8 bit */
 3746           SIUL_GPDO_8B_tag GPDO499;      /* offset: 0x07F3 size: 8 bit */
 3747           SIUL_GPDO_8B_tag GPDO500;      /* offset: 0x07F4 size: 8 bit */
 3748           SIUL_GPDO_8B_tag GPDO501;      /* offset: 0x07F5 size: 8 bit */
 3749           SIUL_GPDO_8B_tag GPDO502;      /* offset: 0x07F6 size: 8 bit */
 3750           SIUL_GPDO_8B_tag GPDO503;      /* offset: 0x07F7 size: 8 bit */
 3751           SIUL_GPDO_8B_tag GPDO504;      /* offset: 0x07F8 size: 8 bit */
 3752           SIUL_GPDO_8B_tag GPDO505;      /* offset: 0x07F9 size: 8 bit */
 3753           SIUL_GPDO_8B_tag GPDO506;      /* offset: 0x07FA size: 8 bit */
 3754           SIUL_GPDO_8B_tag GPDO507;      /* offset: 0x07FB size: 8 bit */
 3755           SIUL_GPDO_8B_tag GPDO508;      /* offset: 0x07FC size: 8 bit */
 3756           SIUL_GPDO_8B_tag GPDO509;      /* offset: 0x07FD size: 8 bit */
 3757           SIUL_GPDO_8B_tag GPDO510;      /* offset: 0x07FE size: 8 bit */
 3758           SIUL_GPDO_8B_tag GPDO511;      /* offset: 0x07FF size: 8 bit */
 3759         };
 3760       };
 3761   
 3762       union {
 3763         /* GPDI - GPIO Pad Data Input Register */
 3764         SIUL_GPDI_32B_tag GPDI_32B[128]; /* offset: 0x0800  (0x0004 x 128) */
 3765   
 3766         /* GPDI - GPIO Pad Data Input Register */
 3767         SIUL_GPDI_8B_tag GPDI[512];      /* offset: 0x0800  (0x0001 x 512) */
 3768         struct {
 3769           /* GPDI - GPIO Pad Data Input Register */
 3770           SIUL_GPDI_32B_tag GPDI0_3;     /* offset: 0x0800 size: 32 bit */
 3771           SIUL_GPDI_32B_tag GPDI4_7;     /* offset: 0x0804 size: 32 bit */
 3772           SIUL_GPDI_32B_tag GPDI8_11;    /* offset: 0x0808 size: 32 bit */
 3773           SIUL_GPDI_32B_tag GPDI12_15;   /* offset: 0x080C size: 32 bit */
 3774           SIUL_GPDI_32B_tag GPDI16_19;   /* offset: 0x0810 size: 32 bit */
 3775           SIUL_GPDI_32B_tag GPDI20_23;   /* offset: 0x0814 size: 32 bit */
 3776           SIUL_GPDI_32B_tag GPDI24_27;   /* offset: 0x0818 size: 32 bit */
 3777           SIUL_GPDI_32B_tag GPDI28_31;   /* offset: 0x081C size: 32 bit */
 3778           SIUL_GPDI_32B_tag GPDI32_35;   /* offset: 0x0820 size: 32 bit */
 3779           SIUL_GPDI_32B_tag GPDI36_39;   /* offset: 0x0824 size: 32 bit */
 3780           SIUL_GPDI_32B_tag GPDI40_43;   /* offset: 0x0828 size: 32 bit */
 3781           SIUL_GPDI_32B_tag GPDI44_47;   /* offset: 0x082C size: 32 bit */
 3782           SIUL_GPDI_32B_tag GPDI48_51;   /* offset: 0x0830 size: 32 bit */
 3783           SIUL_GPDI_32B_tag GPDI52_55;   /* offset: 0x0834 size: 32 bit */
 3784           SIUL_GPDI_32B_tag GPDI56_59;   /* offset: 0x0838 size: 32 bit */
 3785           SIUL_GPDI_32B_tag GPDI60_63;   /* offset: 0x083C size: 32 bit */
 3786           SIUL_GPDI_32B_tag GPDI64_67;   /* offset: 0x0840 size: 32 bit */
 3787           SIUL_GPDI_32B_tag GPDI68_71;   /* offset: 0x0844 size: 32 bit */
 3788           SIUL_GPDI_32B_tag GPDI72_75;   /* offset: 0x0848 size: 32 bit */
 3789           SIUL_GPDI_32B_tag GPDI76_79;   /* offset: 0x084C size: 32 bit */
 3790           SIUL_GPDI_32B_tag GPDI80_83;   /* offset: 0x0850 size: 32 bit */
 3791           SIUL_GPDI_32B_tag GPDI84_87;   /* offset: 0x0854 size: 32 bit */
 3792           SIUL_GPDI_32B_tag GPDI88_91;   /* offset: 0x0858 size: 32 bit */
 3793           SIUL_GPDI_32B_tag GPDI92_95;   /* offset: 0x085C size: 32 bit */
 3794           SIUL_GPDI_32B_tag GPDI96_99;   /* offset: 0x0860 size: 32 bit */
 3795           SIUL_GPDI_32B_tag GPDI100_103; /* offset: 0x0864 size: 32 bit */
 3796           SIUL_GPDI_32B_tag GPDI104_107; /* offset: 0x0868 size: 32 bit */
 3797           SIUL_GPDI_32B_tag GPDI108_111; /* offset: 0x086C size: 32 bit */
 3798           SIUL_GPDI_32B_tag GPDI112_115; /* offset: 0x0870 size: 32 bit */
 3799           SIUL_GPDI_32B_tag GPDI116_119; /* offset: 0x0874 size: 32 bit */
 3800           SIUL_GPDI_32B_tag GPDI120_123; /* offset: 0x0878 size: 32 bit */
 3801           SIUL_GPDI_32B_tag GPDI124_127; /* offset: 0x087C size: 32 bit */
 3802           SIUL_GPDI_32B_tag GPDI128_131; /* offset: 0x0880 size: 32 bit */
 3803           SIUL_GPDI_32B_tag GPDI132_135; /* offset: 0x0884 size: 32 bit */
 3804           SIUL_GPDI_32B_tag GPDI136_139; /* offset: 0x0888 size: 32 bit */
 3805           SIUL_GPDI_32B_tag GPDI140_143; /* offset: 0x088C size: 32 bit */
 3806           SIUL_GPDI_32B_tag GPDI144_147; /* offset: 0x0890 size: 32 bit */
 3807           SIUL_GPDI_32B_tag GPDI148_151; /* offset: 0x0894 size: 32 bit */
 3808           SIUL_GPDI_32B_tag GPDI152_155; /* offset: 0x0898 size: 32 bit */
 3809           SIUL_GPDI_32B_tag GPDI156_159; /* offset: 0x089C size: 32 bit */
 3810           SIUL_GPDI_32B_tag GPDI160_163; /* offset: 0x08A0 size: 32 bit */
 3811           SIUL_GPDI_32B_tag GPDI164_167; /* offset: 0x08A4 size: 32 bit */
 3812           SIUL_GPDI_32B_tag GPDI168_171; /* offset: 0x08A8 size: 32 bit */
 3813           SIUL_GPDI_32B_tag GPDI172_175; /* offset: 0x08AC size: 32 bit */
 3814           SIUL_GPDI_32B_tag GPDI176_179; /* offset: 0x08B0 size: 32 bit */
 3815           SIUL_GPDI_32B_tag GPDI180_183; /* offset: 0x08B4 size: 32 bit */
 3816           SIUL_GPDI_32B_tag GPDI184_187; /* offset: 0x08B8 size: 32 bit */
 3817           SIUL_GPDI_32B_tag GPDI188_191; /* offset: 0x08BC size: 32 bit */
 3818           SIUL_GPDI_32B_tag GPDI192_195; /* offset: 0x08C0 size: 32 bit */
 3819           SIUL_GPDI_32B_tag GPDI196_199; /* offset: 0x08C4 size: 32 bit */
 3820           SIUL_GPDI_32B_tag GPDI200_203; /* offset: 0x08C8 size: 32 bit */
 3821           SIUL_GPDI_32B_tag GPDI204_207; /* offset: 0x08CC size: 32 bit */
 3822           SIUL_GPDI_32B_tag GPDI208_211; /* offset: 0x08D0 size: 32 bit */
 3823           SIUL_GPDI_32B_tag GPDI212_215; /* offset: 0x08D4 size: 32 bit */
 3824           SIUL_GPDI_32B_tag GPDI216_219; /* offset: 0x08D8 size: 32 bit */
 3825           SIUL_GPDI_32B_tag GPDI220_223; /* offset: 0x08DC size: 32 bit */
 3826           SIUL_GPDI_32B_tag GPDI224_227; /* offset: 0x08E0 size: 32 bit */
 3827           SIUL_GPDI_32B_tag GPDI228_231; /* offset: 0x08E4 size: 32 bit */
 3828           SIUL_GPDI_32B_tag GPDI232_235; /* offset: 0x08E8 size: 32 bit */
 3829           SIUL_GPDI_32B_tag GPDI236_239; /* offset: 0x08EC size: 32 bit */
 3830           SIUL_GPDI_32B_tag GPDI240_243; /* offset: 0x08F0 size: 32 bit */
 3831           SIUL_GPDI_32B_tag GPDI244_247; /* offset: 0x08F4 size: 32 bit */
 3832           SIUL_GPDI_32B_tag GPDI248_251; /* offset: 0x08F8 size: 32 bit */
 3833           SIUL_GPDI_32B_tag GPDI252_255; /* offset: 0x08FC size: 32 bit */
 3834           SIUL_GPDI_32B_tag GPDI256_259; /* offset: 0x0900 size: 32 bit */
 3835           SIUL_GPDI_32B_tag GPDI260_263; /* offset: 0x0904 size: 32 bit */
 3836           SIUL_GPDI_32B_tag GPDI264_267; /* offset: 0x0908 size: 32 bit */
 3837           SIUL_GPDI_32B_tag GPDI268_271; /* offset: 0x090C size: 32 bit */
 3838           SIUL_GPDI_32B_tag GPDI272_275; /* offset: 0x0910 size: 32 bit */
 3839           SIUL_GPDI_32B_tag GPDI276_279; /* offset: 0x0914 size: 32 bit */
 3840           SIUL_GPDI_32B_tag GPDI280_283; /* offset: 0x0918 size: 32 bit */
 3841           SIUL_GPDI_32B_tag GPDI284_287; /* offset: 0x091C size: 32 bit */
 3842           SIUL_GPDI_32B_tag GPDI288_291; /* offset: 0x0920 size: 32 bit */
 3843           SIUL_GPDI_32B_tag GPDI292_295; /* offset: 0x0924 size: 32 bit */
 3844           SIUL_GPDI_32B_tag GPDI296_299; /* offset: 0x0928 size: 32 bit */
 3845           SIUL_GPDI_32B_tag GPDI300_303; /* offset: 0x092C size: 32 bit */
 3846           SIUL_GPDI_32B_tag GPDI304_307; /* offset: 0x0930 size: 32 bit */
 3847           SIUL_GPDI_32B_tag GPDI308_311; /* offset: 0x0934 size: 32 bit */
 3848           SIUL_GPDI_32B_tag GPDI312_315; /* offset: 0x0938 size: 32 bit */
 3849           SIUL_GPDI_32B_tag GPDI316_319; /* offset: 0x093C size: 32 bit */
 3850           SIUL_GPDI_32B_tag GPDI320_323; /* offset: 0x0940 size: 32 bit */
 3851           SIUL_GPDI_32B_tag GPDI324_327; /* offset: 0x0944 size: 32 bit */
 3852           SIUL_GPDI_32B_tag GPDI328_331; /* offset: 0x0948 size: 32 bit */
 3853           SIUL_GPDI_32B_tag GPDI332_335; /* offset: 0x094C size: 32 bit */
 3854           SIUL_GPDI_32B_tag GPDI336_339; /* offset: 0x0950 size: 32 bit */
 3855           SIUL_GPDI_32B_tag GPDI340_343; /* offset: 0x0954 size: 32 bit */
 3856           SIUL_GPDI_32B_tag GPDI344_347; /* offset: 0x0958 size: 32 bit */
 3857           SIUL_GPDI_32B_tag GPDI348_351; /* offset: 0x095C size: 32 bit */
 3858           SIUL_GPDI_32B_tag GPDI352_355; /* offset: 0x0960 size: 32 bit */
 3859           SIUL_GPDI_32B_tag GPDI356_359; /* offset: 0x0964 size: 32 bit */
 3860           SIUL_GPDI_32B_tag GPDI360_363; /* offset: 0x0968 size: 32 bit */
 3861           SIUL_GPDI_32B_tag GPDI364_367; /* offset: 0x096C size: 32 bit */
 3862           SIUL_GPDI_32B_tag GPDI368_371; /* offset: 0x0970 size: 32 bit */
 3863           SIUL_GPDI_32B_tag GPDI372_375; /* offset: 0x0974 size: 32 bit */
 3864           SIUL_GPDI_32B_tag GPDI376_379; /* offset: 0x0978 size: 32 bit */
 3865           SIUL_GPDI_32B_tag GPDI380_383; /* offset: 0x097C size: 32 bit */
 3866           SIUL_GPDI_32B_tag GPDI384_387; /* offset: 0x0980 size: 32 bit */
 3867           SIUL_GPDI_32B_tag GPDI388_391; /* offset: 0x0984 size: 32 bit */
 3868           SIUL_GPDI_32B_tag GPDI392_395; /* offset: 0x0988 size: 32 bit */
 3869           SIUL_GPDI_32B_tag GPDI396_399; /* offset: 0x098C size: 32 bit */
 3870           SIUL_GPDI_32B_tag GPDI400_403; /* offset: 0x0990 size: 32 bit */
 3871           SIUL_GPDI_32B_tag GPDI404_407; /* offset: 0x0994 size: 32 bit */
 3872           SIUL_GPDI_32B_tag GPDI408_411; /* offset: 0x0998 size: 32 bit */
 3873           SIUL_GPDI_32B_tag GPDI412_415; /* offset: 0x099C size: 32 bit */
 3874           SIUL_GPDI_32B_tag GPDI416_419; /* offset: 0x09A0 size: 32 bit */
 3875           SIUL_GPDI_32B_tag GPDI420_423; /* offset: 0x09A4 size: 32 bit */
 3876           SIUL_GPDI_32B_tag GPDI424_427; /* offset: 0x09A8 size: 32 bit */
 3877           SIUL_GPDI_32B_tag GPDI428_431; /* offset: 0x09AC size: 32 bit */
 3878           SIUL_GPDI_32B_tag GPDI432_435; /* offset: 0x09B0 size: 32 bit */
 3879           SIUL_GPDI_32B_tag GPDI436_439; /* offset: 0x09B4 size: 32 bit */
 3880           SIUL_GPDI_32B_tag GPDI440_443; /* offset: 0x09B8 size: 32 bit */
 3881           SIUL_GPDI_32B_tag GPDI444_447; /* offset: 0x09BC size: 32 bit */
 3882           SIUL_GPDI_32B_tag GPDI448_451; /* offset: 0x09C0 size: 32 bit */
 3883           SIUL_GPDI_32B_tag GPDI452_455; /* offset: 0x09C4 size: 32 bit */
 3884           SIUL_GPDI_32B_tag GPDI456_459; /* offset: 0x09C8 size: 32 bit */
 3885           SIUL_GPDI_32B_tag GPDI460_463; /* offset: 0x09CC size: 32 bit */
 3886           SIUL_GPDI_32B_tag GPDI464_467; /* offset: 0x09D0 size: 32 bit */
 3887           SIUL_GPDI_32B_tag GPDI468_471; /* offset: 0x09D4 size: 32 bit */
 3888           SIUL_GPDI_32B_tag GPDI472_475; /* offset: 0x09D8 size: 32 bit */
 3889           SIUL_GPDI_32B_tag GPDI476_479; /* offset: 0x09DC size: 32 bit */
 3890           SIUL_GPDI_32B_tag GPDI480_483; /* offset: 0x09E0 size: 32 bit */
 3891           SIUL_GPDI_32B_tag GPDI484_487; /* offset: 0x09E4 size: 32 bit */
 3892           SIUL_GPDI_32B_tag GPDI488_491; /* offset: 0x09E8 size: 32 bit */
 3893           SIUL_GPDI_32B_tag GPDI492_495; /* offset: 0x09EC size: 32 bit */
 3894           SIUL_GPDI_32B_tag GPDI496_499; /* offset: 0x09F0 size: 32 bit */
 3895           SIUL_GPDI_32B_tag GPDI500_503; /* offset: 0x09F4 size: 32 bit */
 3896           SIUL_GPDI_32B_tag GPDI504_507; /* offset: 0x09F8 size: 32 bit */
 3897           SIUL_GPDI_32B_tag GPDI508_511; /* offset: 0x09FC size: 32 bit */
 3898         };
 3899   
 3900         struct {
 3901           /* GPDI - GPIO Pad Data Input Register */
 3902           SIUL_GPDI_8B_tag GPDI0;        /* offset: 0x0800 size: 8 bit */
 3903           SIUL_GPDI_8B_tag GPDI1;        /* offset: 0x0801 size: 8 bit */
 3904           SIUL_GPDI_8B_tag GPDI2;        /* offset: 0x0802 size: 8 bit */
 3905           SIUL_GPDI_8B_tag GPDI3;        /* offset: 0x0803 size: 8 bit */
 3906           SIUL_GPDI_8B_tag GPDI4;        /* offset: 0x0804 size: 8 bit */
 3907           SIUL_GPDI_8B_tag GPDI5;        /* offset: 0x0805 size: 8 bit */
 3908           SIUL_GPDI_8B_tag GPDI6;        /* offset: 0x0806 size: 8 bit */
 3909           SIUL_GPDI_8B_tag GPDI7;        /* offset: 0x0807 size: 8 bit */
 3910           SIUL_GPDI_8B_tag GPDI8;        /* offset: 0x0808 size: 8 bit */
 3911           SIUL_GPDI_8B_tag GPDI9;        /* offset: 0x0809 size: 8 bit */
 3912           SIUL_GPDI_8B_tag GPDI10;       /* offset: 0x080A size: 8 bit */
 3913           SIUL_GPDI_8B_tag GPDI11;       /* offset: 0x080B size: 8 bit */
 3914           SIUL_GPDI_8B_tag GPDI12;       /* offset: 0x080C size: 8 bit */
 3915           SIUL_GPDI_8B_tag GPDI13;       /* offset: 0x080D size: 8 bit */
 3916           SIUL_GPDI_8B_tag GPDI14;       /* offset: 0x080E size: 8 bit */
 3917           SIUL_GPDI_8B_tag GPDI15;       /* offset: 0x080F size: 8 bit */
 3918           SIUL_GPDI_8B_tag GPDI16;       /* offset: 0x0810 size: 8 bit */
 3919           SIUL_GPDI_8B_tag GPDI17;       /* offset: 0x0811 size: 8 bit */
 3920           SIUL_GPDI_8B_tag GPDI18;       /* offset: 0x0812 size: 8 bit */
 3921           SIUL_GPDI_8B_tag GPDI19;       /* offset: 0x0813 size: 8 bit */
 3922           SIUL_GPDI_8B_tag GPDI20;       /* offset: 0x0814 size: 8 bit */
 3923           SIUL_GPDI_8B_tag GPDI21;       /* offset: 0x0815 size: 8 bit */
 3924           SIUL_GPDI_8B_tag GPDI22;       /* offset: 0x0816 size: 8 bit */
 3925           SIUL_GPDI_8B_tag GPDI23;       /* offset: 0x0817 size: 8 bit */
 3926           SIUL_GPDI_8B_tag GPDI24;       /* offset: 0x0818 size: 8 bit */
 3927           SIUL_GPDI_8B_tag GPDI25;       /* offset: 0x0819 size: 8 bit */
 3928           SIUL_GPDI_8B_tag GPDI26;       /* offset: 0x081A size: 8 bit */
 3929           SIUL_GPDI_8B_tag GPDI27;       /* offset: 0x081B size: 8 bit */
 3930           SIUL_GPDI_8B_tag GPDI28;       /* offset: 0x081C size: 8 bit */
 3931           SIUL_GPDI_8B_tag GPDI29;       /* offset: 0x081D size: 8 bit */
 3932           SIUL_GPDI_8B_tag GPDI30;       /* offset: 0x081E size: 8 bit */
 3933           SIUL_GPDI_8B_tag GPDI31;       /* offset: 0x081F size: 8 bit */
 3934           SIUL_GPDI_8B_tag GPDI32;       /* offset: 0x0820 size: 8 bit */
 3935           SIUL_GPDI_8B_tag GPDI33;       /* offset: 0x0821 size: 8 bit */
 3936           SIUL_GPDI_8B_tag GPDI34;       /* offset: 0x0822 size: 8 bit */
 3937           SIUL_GPDI_8B_tag GPDI35;       /* offset: 0x0823 size: 8 bit */
 3938           SIUL_GPDI_8B_tag GPDI36;       /* offset: 0x0824 size: 8 bit */
 3939           SIUL_GPDI_8B_tag GPDI37;       /* offset: 0x0825 size: 8 bit */
 3940           SIUL_GPDI_8B_tag GPDI38;       /* offset: 0x0826 size: 8 bit */
 3941           SIUL_GPDI_8B_tag GPDI39;       /* offset: 0x0827 size: 8 bit */
 3942           SIUL_GPDI_8B_tag GPDI40;       /* offset: 0x0828 size: 8 bit */
 3943           SIUL_GPDI_8B_tag GPDI41;       /* offset: 0x0829 size: 8 bit */
 3944           SIUL_GPDI_8B_tag GPDI42;       /* offset: 0x082A size: 8 bit */
 3945           SIUL_GPDI_8B_tag GPDI43;       /* offset: 0x082B size: 8 bit */
 3946           SIUL_GPDI_8B_tag GPDI44;       /* offset: 0x082C size: 8 bit */
 3947           SIUL_GPDI_8B_tag GPDI45;       /* offset: 0x082D size: 8 bit */
 3948           SIUL_GPDI_8B_tag GPDI46;       /* offset: 0x082E size: 8 bit */
 3949           SIUL_GPDI_8B_tag GPDI47;       /* offset: 0x082F size: 8 bit */
 3950           SIUL_GPDI_8B_tag GPDI48;       /* offset: 0x0830 size: 8 bit */
 3951           SIUL_GPDI_8B_tag GPDI49;       /* offset: 0x0831 size: 8 bit */
 3952           SIUL_GPDI_8B_tag GPDI50;       /* offset: 0x0832 size: 8 bit */
 3953           SIUL_GPDI_8B_tag GPDI51;       /* offset: 0x0833 size: 8 bit */
 3954           SIUL_GPDI_8B_tag GPDI52;       /* offset: 0x0834 size: 8 bit */
 3955           SIUL_GPDI_8B_tag GPDI53;       /* offset: 0x0835 size: 8 bit */
 3956           SIUL_GPDI_8B_tag GPDI54;       /* offset: 0x0836 size: 8 bit */
 3957           SIUL_GPDI_8B_tag GPDI55;       /* offset: 0x0837 size: 8 bit */
 3958           SIUL_GPDI_8B_tag GPDI56;       /* offset: 0x0838 size: 8 bit */
 3959           SIUL_GPDI_8B_tag GPDI57;       /* offset: 0x0839 size: 8 bit */
 3960           SIUL_GPDI_8B_tag GPDI58;       /* offset: 0x083A size: 8 bit */
 3961           SIUL_GPDI_8B_tag GPDI59;       /* offset: 0x083B size: 8 bit */
 3962           SIUL_GPDI_8B_tag GPDI60;       /* offset: 0x083C size: 8 bit */
 3963           SIUL_GPDI_8B_tag GPDI61;       /* offset: 0x083D size: 8 bit */
 3964           SIUL_GPDI_8B_tag GPDI62;       /* offset: 0x083E size: 8 bit */
 3965           SIUL_GPDI_8B_tag GPDI63;       /* offset: 0x083F size: 8 bit */
 3966           SIUL_GPDI_8B_tag GPDI64;       /* offset: 0x0840 size: 8 bit */
 3967           SIUL_GPDI_8B_tag GPDI65;       /* offset: 0x0841 size: 8 bit */
 3968           SIUL_GPDI_8B_tag GPDI66;       /* offset: 0x0842 size: 8 bit */
 3969           SIUL_GPDI_8B_tag GPDI67;       /* offset: 0x0843 size: 8 bit */
 3970           SIUL_GPDI_8B_tag GPDI68;       /* offset: 0x0844 size: 8 bit */
 3971           SIUL_GPDI_8B_tag GPDI69;       /* offset: 0x0845 size: 8 bit */
 3972           SIUL_GPDI_8B_tag GPDI70;       /* offset: 0x0846 size: 8 bit */
 3973           SIUL_GPDI_8B_tag GPDI71;       /* offset: 0x0847 size: 8 bit */
 3974           SIUL_GPDI_8B_tag GPDI72;       /* offset: 0x0848 size: 8 bit */
 3975           SIUL_GPDI_8B_tag GPDI73;       /* offset: 0x0849 size: 8 bit */
 3976           SIUL_GPDI_8B_tag GPDI74;       /* offset: 0x084A size: 8 bit */
 3977           SIUL_GPDI_8B_tag GPDI75;       /* offset: 0x084B size: 8 bit */
 3978           SIUL_GPDI_8B_tag GPDI76;       /* offset: 0x084C size: 8 bit */
 3979           SIUL_GPDI_8B_tag GPDI77;       /* offset: 0x084D size: 8 bit */
 3980           SIUL_GPDI_8B_tag GPDI78;       /* offset: 0x084E size: 8 bit */
 3981           SIUL_GPDI_8B_tag GPDI79;       /* offset: 0x084F size: 8 bit */
 3982           SIUL_GPDI_8B_tag GPDI80;       /* offset: 0x0850 size: 8 bit */
 3983           SIUL_GPDI_8B_tag GPDI81;       /* offset: 0x0851 size: 8 bit */
 3984           SIUL_GPDI_8B_tag GPDI82;       /* offset: 0x0852 size: 8 bit */
 3985           SIUL_GPDI_8B_tag GPDI83;       /* offset: 0x0853 size: 8 bit */
 3986           SIUL_GPDI_8B_tag GPDI84;       /* offset: 0x0854 size: 8 bit */
 3987           SIUL_GPDI_8B_tag GPDI85;       /* offset: 0x0855 size: 8 bit */
 3988           SIUL_GPDI_8B_tag GPDI86;       /* offset: 0x0856 size: 8 bit */
 3989           SIUL_GPDI_8B_tag GPDI87;       /* offset: 0x0857 size: 8 bit */
 3990           SIUL_GPDI_8B_tag GPDI88;       /* offset: 0x0858 size: 8 bit */
 3991           SIUL_GPDI_8B_tag GPDI89;       /* offset: 0x0859 size: 8 bit */
 3992           SIUL_GPDI_8B_tag GPDI90;       /* offset: 0x085A size: 8 bit */
 3993           SIUL_GPDI_8B_tag GPDI91;       /* offset: 0x085B size: 8 bit */
 3994           SIUL_GPDI_8B_tag GPDI92;       /* offset: 0x085C size: 8 bit */
 3995           SIUL_GPDI_8B_tag GPDI93;       /* offset: 0x085D size: 8 bit */
 3996           SIUL_GPDI_8B_tag GPDI94;       /* offset: 0x085E size: 8 bit */
 3997           SIUL_GPDI_8B_tag GPDI95;       /* offset: 0x085F size: 8 bit */
 3998           SIUL_GPDI_8B_tag GPDI96;       /* offset: 0x0860 size: 8 bit */
 3999           SIUL_GPDI_8B_tag GPDI97;       /* offset: 0x0861 size: 8 bit */
 4000           SIUL_GPDI_8B_tag GPDI98;       /* offset: 0x0862 size: 8 bit */
 4001           SIUL_GPDI_8B_tag GPDI99;       /* offset: 0x0863 size: 8 bit */
 4002           SIUL_GPDI_8B_tag GPDI100;      /* offset: 0x0864 size: 8 bit */
 4003           SIUL_GPDI_8B_tag GPDI101;      /* offset: 0x0865 size: 8 bit */
 4004           SIUL_GPDI_8B_tag GPDI102;      /* offset: 0x0866 size: 8 bit */
 4005           SIUL_GPDI_8B_tag GPDI103;      /* offset: 0x0867 size: 8 bit */
 4006           SIUL_GPDI_8B_tag GPDI104;      /* offset: 0x0868 size: 8 bit */
 4007           SIUL_GPDI_8B_tag GPDI105;      /* offset: 0x0869 size: 8 bit */
 4008           SIUL_GPDI_8B_tag GPDI106;      /* offset: 0x086A size: 8 bit */
 4009           SIUL_GPDI_8B_tag GPDI107;      /* offset: 0x086B size: 8 bit */
 4010           SIUL_GPDI_8B_tag GPDI108;      /* offset: 0x086C size: 8 bit */
 4011           SIUL_GPDI_8B_tag GPDI109;      /* offset: 0x086D size: 8 bit */
 4012           SIUL_GPDI_8B_tag GPDI110;      /* offset: 0x086E size: 8 bit */
 4013           SIUL_GPDI_8B_tag GPDI111;      /* offset: 0x086F size: 8 bit */
 4014           SIUL_GPDI_8B_tag GPDI112;      /* offset: 0x0870 size: 8 bit */
 4015           SIUL_GPDI_8B_tag GPDI113;      /* offset: 0x0871 size: 8 bit */
 4016           SIUL_GPDI_8B_tag GPDI114;      /* offset: 0x0872 size: 8 bit */
 4017           SIUL_GPDI_8B_tag GPDI115;      /* offset: 0x0873 size: 8 bit */
 4018           SIUL_GPDI_8B_tag GPDI116;      /* offset: 0x0874 size: 8 bit */
 4019           SIUL_GPDI_8B_tag GPDI117;      /* offset: 0x0875 size: 8 bit */
 4020           SIUL_GPDI_8B_tag GPDI118;      /* offset: 0x0876 size: 8 bit */
 4021           SIUL_GPDI_8B_tag GPDI119;      /* offset: 0x0877 size: 8 bit */
 4022           SIUL_GPDI_8B_tag GPDI120;      /* offset: 0x0878 size: 8 bit */
 4023           SIUL_GPDI_8B_tag GPDI121;      /* offset: 0x0879 size: 8 bit */
 4024           SIUL_GPDI_8B_tag GPDI122;      /* offset: 0x087A size: 8 bit */
 4025           SIUL_GPDI_8B_tag GPDI123;      /* offset: 0x087B size: 8 bit */
 4026           SIUL_GPDI_8B_tag GPDI124;      /* offset: 0x087C size: 8 bit */
 4027           SIUL_GPDI_8B_tag GPDI125;      /* offset: 0x087D size: 8 bit */
 4028           SIUL_GPDI_8B_tag GPDI126;      /* offset: 0x087E size: 8 bit */
 4029           SIUL_GPDI_8B_tag GPDI127;      /* offset: 0x087F size: 8 bit */
 4030           SIUL_GPDI_8B_tag GPDI128;      /* offset: 0x0880 size: 8 bit */
 4031           SIUL_GPDI_8B_tag GPDI129;      /* offset: 0x0881 size: 8 bit */
 4032           SIUL_GPDI_8B_tag GPDI130;      /* offset: 0x0882 size: 8 bit */
 4033           SIUL_GPDI_8B_tag GPDI131;      /* offset: 0x0883 size: 8 bit */
 4034           SIUL_GPDI_8B_tag GPDI132;      /* offset: 0x0884 size: 8 bit */
 4035           SIUL_GPDI_8B_tag GPDI133;      /* offset: 0x0885 size: 8 bit */
 4036           SIUL_GPDI_8B_tag GPDI134;      /* offset: 0x0886 size: 8 bit */
 4037           SIUL_GPDI_8B_tag GPDI135;      /* offset: 0x0887 size: 8 bit */
 4038           SIUL_GPDI_8B_tag GPDI136;      /* offset: 0x0888 size: 8 bit */
 4039           SIUL_GPDI_8B_tag GPDI137;      /* offset: 0x0889 size: 8 bit */
 4040           SIUL_GPDI_8B_tag GPDI138;      /* offset: 0x088A size: 8 bit */
 4041           SIUL_GPDI_8B_tag GPDI139;      /* offset: 0x088B size: 8 bit */
 4042           SIUL_GPDI_8B_tag GPDI140;      /* offset: 0x088C size: 8 bit */
 4043           SIUL_GPDI_8B_tag GPDI141;      /* offset: 0x088D size: 8 bit */
 4044           SIUL_GPDI_8B_tag GPDI142;      /* offset: 0x088E size: 8 bit */
 4045           SIUL_GPDI_8B_tag GPDI143;      /* offset: 0x088F size: 8 bit */
 4046           SIUL_GPDI_8B_tag GPDI144;      /* offset: 0x0890 size: 8 bit */
 4047           SIUL_GPDI_8B_tag GPDI145;      /* offset: 0x0891 size: 8 bit */
 4048           SIUL_GPDI_8B_tag GPDI146;      /* offset: 0x0892 size: 8 bit */
 4049           SIUL_GPDI_8B_tag GPDI147;      /* offset: 0x0893 size: 8 bit */
 4050           SIUL_GPDI_8B_tag GPDI148;      /* offset: 0x0894 size: 8 bit */
 4051           SIUL_GPDI_8B_tag GPDI149;      /* offset: 0x0895 size: 8 bit */
 4052           SIUL_GPDI_8B_tag GPDI150;      /* offset: 0x0896 size: 8 bit */
 4053           SIUL_GPDI_8B_tag GPDI151;      /* offset: 0x0897 size: 8 bit */
 4054           SIUL_GPDI_8B_tag GPDI152;      /* offset: 0x0898 size: 8 bit */
 4055           SIUL_GPDI_8B_tag GPDI153;      /* offset: 0x0899 size: 8 bit */
 4056           SIUL_GPDI_8B_tag GPDI154;      /* offset: 0x089A size: 8 bit */
 4057           SIUL_GPDI_8B_tag GPDI155;      /* offset: 0x089B size: 8 bit */
 4058           SIUL_GPDI_8B_tag GPDI156;      /* offset: 0x089C size: 8 bit */
 4059           SIUL_GPDI_8B_tag GPDI157;      /* offset: 0x089D size: 8 bit */
 4060           SIUL_GPDI_8B_tag GPDI158;      /* offset: 0x089E size: 8 bit */
 4061           SIUL_GPDI_8B_tag GPDI159;      /* offset: 0x089F size: 8 bit */
 4062           SIUL_GPDI_8B_tag GPDI160;      /* offset: 0x08A0 size: 8 bit */
 4063           SIUL_GPDI_8B_tag GPDI161;      /* offset: 0x08A1 size: 8 bit */
 4064           SIUL_GPDI_8B_tag GPDI162;      /* offset: 0x08A2 size: 8 bit */
 4065           SIUL_GPDI_8B_tag GPDI163;      /* offset: 0x08A3 size: 8 bit */
 4066           SIUL_GPDI_8B_tag GPDI164;      /* offset: 0x08A4 size: 8 bit */
 4067           SIUL_GPDI_8B_tag GPDI165;      /* offset: 0x08A5 size: 8 bit */
 4068           SIUL_GPDI_8B_tag GPDI166;      /* offset: 0x08A6 size: 8 bit */
 4069           SIUL_GPDI_8B_tag GPDI167;      /* offset: 0x08A7 size: 8 bit */
 4070           SIUL_GPDI_8B_tag GPDI168;      /* offset: 0x08A8 size: 8 bit */
 4071           SIUL_GPDI_8B_tag GPDI169;      /* offset: 0x08A9 size: 8 bit */
 4072           SIUL_GPDI_8B_tag GPDI170;      /* offset: 0x08AA size: 8 bit */
 4073           SIUL_GPDI_8B_tag GPDI171;      /* offset: 0x08AB size: 8 bit */
 4074           SIUL_GPDI_8B_tag GPDI172;      /* offset: 0x08AC size: 8 bit */
 4075           SIUL_GPDI_8B_tag GPDI173;      /* offset: 0x08AD size: 8 bit */
 4076           SIUL_GPDI_8B_tag GPDI174;      /* offset: 0x08AE size: 8 bit */
 4077           SIUL_GPDI_8B_tag GPDI175;      /* offset: 0x08AF size: 8 bit */
 4078           SIUL_GPDI_8B_tag GPDI176;      /* offset: 0x08B0 size: 8 bit */
 4079           SIUL_GPDI_8B_tag GPDI177;      /* offset: 0x08B1 size: 8 bit */
 4080           SIUL_GPDI_8B_tag GPDI178;      /* offset: 0x08B2 size: 8 bit */
 4081           SIUL_GPDI_8B_tag GPDI179;      /* offset: 0x08B3 size: 8 bit */
 4082           SIUL_GPDI_8B_tag GPDI180;      /* offset: 0x08B4 size: 8 bit */
 4083           SIUL_GPDI_8B_tag GPDI181;      /* offset: 0x08B5 size: 8 bit */
 4084           SIUL_GPDI_8B_tag GPDI182;      /* offset: 0x08B6 size: 8 bit */
 4085           SIUL_GPDI_8B_tag GPDI183;      /* offset: 0x08B7 size: 8 bit */
 4086           SIUL_GPDI_8B_tag GPDI184;      /* offset: 0x08B8 size: 8 bit */
 4087           SIUL_GPDI_8B_tag GPDI185;      /* offset: 0x08B9 size: 8 bit */
 4088           SIUL_GPDI_8B_tag GPDI186;      /* offset: 0x08BA size: 8 bit */
 4089           SIUL_GPDI_8B_tag GPDI187;      /* offset: 0x08BB size: 8 bit */
 4090           SIUL_GPDI_8B_tag GPDI188;      /* offset: 0x08BC size: 8 bit */
 4091           SIUL_GPDI_8B_tag GPDI189;      /* offset: 0x08BD size: 8 bit */
 4092           SIUL_GPDI_8B_tag GPDI190;      /* offset: 0x08BE size: 8 bit */
 4093           SIUL_GPDI_8B_tag GPDI191;      /* offset: 0x08BF size: 8 bit */
 4094           SIUL_GPDI_8B_tag GPDI192;      /* offset: 0x08C0 size: 8 bit */
 4095           SIUL_GPDI_8B_tag GPDI193;      /* offset: 0x08C1 size: 8 bit */
 4096           SIUL_GPDI_8B_tag GPDI194;      /* offset: 0x08C2 size: 8 bit */
 4097           SIUL_GPDI_8B_tag GPDI195;      /* offset: 0x08C3 size: 8 bit */
 4098           SIUL_GPDI_8B_tag GPDI196;      /* offset: 0x08C4 size: 8 bit */
 4099           SIUL_GPDI_8B_tag GPDI197;      /* offset: 0x08C5 size: 8 bit */
 4100           SIUL_GPDI_8B_tag GPDI198;      /* offset: 0x08C6 size: 8 bit */
 4101           SIUL_GPDI_8B_tag GPDI199;      /* offset: 0x08C7 size: 8 bit */
 4102           SIUL_GPDI_8B_tag GPDI200;      /* offset: 0x08C8 size: 8 bit */
 4103           SIUL_GPDI_8B_tag GPDI201;      /* offset: 0x08C9 size: 8 bit */
 4104           SIUL_GPDI_8B_tag GPDI202;      /* offset: 0x08CA size: 8 bit */
 4105           SIUL_GPDI_8B_tag GPDI203;      /* offset: 0x08CB size: 8 bit */
 4106           SIUL_GPDI_8B_tag GPDI204;      /* offset: 0x08CC size: 8 bit */
 4107           SIUL_GPDI_8B_tag GPDI205;      /* offset: 0x08CD size: 8 bit */
 4108           SIUL_GPDI_8B_tag GPDI206;      /* offset: 0x08CE size: 8 bit */
 4109           SIUL_GPDI_8B_tag GPDI207;      /* offset: 0x08CF size: 8 bit */
 4110           SIUL_GPDI_8B_tag GPDI208;      /* offset: 0x08D0 size: 8 bit */
 4111           SIUL_GPDI_8B_tag GPDI209;      /* offset: 0x08D1 size: 8 bit */
 4112           SIUL_GPDI_8B_tag GPDI210;      /* offset: 0x08D2 size: 8 bit */
 4113           SIUL_GPDI_8B_tag GPDI211;      /* offset: 0x08D3 size: 8 bit */
 4114           SIUL_GPDI_8B_tag GPDI212;      /* offset: 0x08D4 size: 8 bit */
 4115           SIUL_GPDI_8B_tag GPDI213;      /* offset: 0x08D5 size: 8 bit */
 4116           SIUL_GPDI_8B_tag GPDI214;      /* offset: 0x08D6 size: 8 bit */
 4117           SIUL_GPDI_8B_tag GPDI215;      /* offset: 0x08D7 size: 8 bit */
 4118           SIUL_GPDI_8B_tag GPDI216;      /* offset: 0x08D8 size: 8 bit */
 4119           SIUL_GPDI_8B_tag GPDI217;      /* offset: 0x08D9 size: 8 bit */
 4120           SIUL_GPDI_8B_tag GPDI218;      /* offset: 0x08DA size: 8 bit */
 4121           SIUL_GPDI_8B_tag GPDI219;      /* offset: 0x08DB size: 8 bit */
 4122           SIUL_GPDI_8B_tag GPDI220;      /* offset: 0x08DC size: 8 bit */
 4123           SIUL_GPDI_8B_tag GPDI221;      /* offset: 0x08DD size: 8 bit */
 4124           SIUL_GPDI_8B_tag GPDI222;      /* offset: 0x08DE size: 8 bit */
 4125           SIUL_GPDI_8B_tag GPDI223;      /* offset: 0x08DF size: 8 bit */
 4126           SIUL_GPDI_8B_tag GPDI224;      /* offset: 0x08E0 size: 8 bit */
 4127           SIUL_GPDI_8B_tag GPDI225;      /* offset: 0x08E1 size: 8 bit */
 4128           SIUL_GPDI_8B_tag GPDI226;      /* offset: 0x08E2 size: 8 bit */
 4129           SIUL_GPDI_8B_tag GPDI227;      /* offset: 0x08E3 size: 8 bit */
 4130           SIUL_GPDI_8B_tag GPDI228;      /* offset: 0x08E4 size: 8 bit */
 4131           SIUL_GPDI_8B_tag GPDI229;      /* offset: 0x08E5 size: 8 bit */
 4132           SIUL_GPDI_8B_tag GPDI230;      /* offset: 0x08E6 size: 8 bit */
 4133           SIUL_GPDI_8B_tag GPDI231;      /* offset: 0x08E7 size: 8 bit */
 4134           SIUL_GPDI_8B_tag GPDI232;      /* offset: 0x08E8 size: 8 bit */
 4135           SIUL_GPDI_8B_tag GPDI233;      /* offset: 0x08E9 size: 8 bit */
 4136           SIUL_GPDI_8B_tag GPDI234;      /* offset: 0x08EA size: 8 bit */
 4137           SIUL_GPDI_8B_tag GPDI235;      /* offset: 0x08EB size: 8 bit */
 4138           SIUL_GPDI_8B_tag GPDI236;      /* offset: 0x08EC size: 8 bit */
 4139           SIUL_GPDI_8B_tag GPDI237;      /* offset: 0x08ED size: 8 bit */
 4140           SIUL_GPDI_8B_tag GPDI238;      /* offset: 0x08EE size: 8 bit */
 4141           SIUL_GPDI_8B_tag GPDI239;      /* offset: 0x08EF size: 8 bit */
 4142           SIUL_GPDI_8B_tag GPDI240;      /* offset: 0x08F0 size: 8 bit */
 4143           SIUL_GPDI_8B_tag GPDI241;      /* offset: 0x08F1 size: 8 bit */
 4144           SIUL_GPDI_8B_tag GPDI242;      /* offset: 0x08F2 size: 8 bit */
 4145           SIUL_GPDI_8B_tag GPDI243;      /* offset: 0x08F3 size: 8 bit */
 4146           SIUL_GPDI_8B_tag GPDI244;      /* offset: 0x08F4 size: 8 bit */
 4147           SIUL_GPDI_8B_tag GPDI245;      /* offset: 0x08F5 size: 8 bit */
 4148           SIUL_GPDI_8B_tag GPDI246;      /* offset: 0x08F6 size: 8 bit */
 4149           SIUL_GPDI_8B_tag GPDI247;      /* offset: 0x08F7 size: 8 bit */
 4150           SIUL_GPDI_8B_tag GPDI248;      /* offset: 0x08F8 size: 8 bit */
 4151           SIUL_GPDI_8B_tag GPDI249;      /* offset: 0x08F9 size: 8 bit */
 4152           SIUL_GPDI_8B_tag GPDI250;      /* offset: 0x08FA size: 8 bit */
 4153           SIUL_GPDI_8B_tag GPDI251;      /* offset: 0x08FB size: 8 bit */
 4154           SIUL_GPDI_8B_tag GPDI252;      /* offset: 0x08FC size: 8 bit */
 4155           SIUL_GPDI_8B_tag GPDI253;      /* offset: 0x08FD size: 8 bit */
 4156           SIUL_GPDI_8B_tag GPDI254;      /* offset: 0x08FE size: 8 bit */
 4157           SIUL_GPDI_8B_tag GPDI255;      /* offset: 0x08FF size: 8 bit */
 4158           SIUL_GPDI_8B_tag GPDI256;      /* offset: 0x0900 size: 8 bit */
 4159           SIUL_GPDI_8B_tag GPDI257;      /* offset: 0x0901 size: 8 bit */
 4160           SIUL_GPDI_8B_tag GPDI258;      /* offset: 0x0902 size: 8 bit */
 4161           SIUL_GPDI_8B_tag GPDI259;      /* offset: 0x0903 size: 8 bit */
 4162           SIUL_GPDI_8B_tag GPDI260;      /* offset: 0x0904 size: 8 bit */
 4163           SIUL_GPDI_8B_tag GPDI261;      /* offset: 0x0905 size: 8 bit */
 4164           SIUL_GPDI_8B_tag GPDI262;      /* offset: 0x0906 size: 8 bit */
 4165           SIUL_GPDI_8B_tag GPDI263;      /* offset: 0x0907 size: 8 bit */
 4166           SIUL_GPDI_8B_tag GPDI264;      /* offset: 0x0908 size: 8 bit */
 4167           SIUL_GPDI_8B_tag GPDI265;      /* offset: 0x0909 size: 8 bit */
 4168           SIUL_GPDI_8B_tag GPDI266;      /* offset: 0x090A size: 8 bit */
 4169           SIUL_GPDI_8B_tag GPDI267;      /* offset: 0x090B size: 8 bit */
 4170           SIUL_GPDI_8B_tag GPDI268;      /* offset: 0x090C size: 8 bit */
 4171           SIUL_GPDI_8B_tag GPDI269;      /* offset: 0x090D size: 8 bit */
 4172           SIUL_GPDI_8B_tag GPDI270;      /* offset: 0x090E size: 8 bit */
 4173           SIUL_GPDI_8B_tag GPDI271;      /* offset: 0x090F size: 8 bit */
 4174           SIUL_GPDI_8B_tag GPDI272;      /* offset: 0x0910 size: 8 bit */
 4175           SIUL_GPDI_8B_tag GPDI273;      /* offset: 0x0911 size: 8 bit */
 4176           SIUL_GPDI_8B_tag GPDI274;      /* offset: 0x0912 size: 8 bit */
 4177           SIUL_GPDI_8B_tag GPDI275;      /* offset: 0x0913 size: 8 bit */
 4178           SIUL_GPDI_8B_tag GPDI276;      /* offset: 0x0914 size: 8 bit */
 4179           SIUL_GPDI_8B_tag GPDI277;      /* offset: 0x0915 size: 8 bit */
 4180           SIUL_GPDI_8B_tag GPDI278;      /* offset: 0x0916 size: 8 bit */
 4181           SIUL_GPDI_8B_tag GPDI279;      /* offset: 0x0917 size: 8 bit */
 4182           SIUL_GPDI_8B_tag GPDI280;      /* offset: 0x0918 size: 8 bit */
 4183           SIUL_GPDI_8B_tag GPDI281;      /* offset: 0x0919 size: 8 bit */
 4184           SIUL_GPDI_8B_tag GPDI282;      /* offset: 0x091A size: 8 bit */
 4185           SIUL_GPDI_8B_tag GPDI283;      /* offset: 0x091B size: 8 bit */
 4186           SIUL_GPDI_8B_tag GPDI284;      /* offset: 0x091C size: 8 bit */
 4187           SIUL_GPDI_8B_tag GPDI285;      /* offset: 0x091D size: 8 bit */
 4188           SIUL_GPDI_8B_tag GPDI286;      /* offset: 0x091E size: 8 bit */
 4189           SIUL_GPDI_8B_tag GPDI287;      /* offset: 0x091F size: 8 bit */
 4190           SIUL_GPDI_8B_tag GPDI288;      /* offset: 0x0920 size: 8 bit */
 4191           SIUL_GPDI_8B_tag GPDI289;      /* offset: 0x0921 size: 8 bit */
 4192           SIUL_GPDI_8B_tag GPDI290;      /* offset: 0x0922 size: 8 bit */
 4193           SIUL_GPDI_8B_tag GPDI291;      /* offset: 0x0923 size: 8 bit */
 4194           SIUL_GPDI_8B_tag GPDI292;      /* offset: 0x0924 size: 8 bit */
 4195           SIUL_GPDI_8B_tag GPDI293;      /* offset: 0x0925 size: 8 bit */
 4196           SIUL_GPDI_8B_tag GPDI294;      /* offset: 0x0926 size: 8 bit */
 4197           SIUL_GPDI_8B_tag GPDI295;      /* offset: 0x0927 size: 8 bit */
 4198           SIUL_GPDI_8B_tag GPDI296;      /* offset: 0x0928 size: 8 bit */
 4199           SIUL_GPDI_8B_tag GPDI297;      /* offset: 0x0929 size: 8 bit */
 4200           SIUL_GPDI_8B_tag GPDI298;      /* offset: 0x092A size: 8 bit */
 4201           SIUL_GPDI_8B_tag GPDI299;      /* offset: 0x092B size: 8 bit */
 4202           SIUL_GPDI_8B_tag GPDI300;      /* offset: 0x092C size: 8 bit */
 4203           SIUL_GPDI_8B_tag GPDI301;      /* offset: 0x092D size: 8 bit */
 4204           SIUL_GPDI_8B_tag GPDI302;      /* offset: 0x092E size: 8 bit */
 4205           SIUL_GPDI_8B_tag GPDI303;      /* offset: 0x092F size: 8 bit */
 4206           SIUL_GPDI_8B_tag GPDI304;      /* offset: 0x0930 size: 8 bit */
 4207           SIUL_GPDI_8B_tag GPDI305;      /* offset: 0x0931 size: 8 bit */
 4208           SIUL_GPDI_8B_tag GPDI306;      /* offset: 0x0932 size: 8 bit */
 4209           SIUL_GPDI_8B_tag GPDI307;      /* offset: 0x0933 size: 8 bit */
 4210           SIUL_GPDI_8B_tag GPDI308;      /* offset: 0x0934 size: 8 bit */
 4211           SIUL_GPDI_8B_tag GPDI309;      /* offset: 0x0935 size: 8 bit */
 4212           SIUL_GPDI_8B_tag GPDI310;      /* offset: 0x0936 size: 8 bit */
 4213           SIUL_GPDI_8B_tag GPDI311;      /* offset: 0x0937 size: 8 bit */
 4214           SIUL_GPDI_8B_tag GPDI312;      /* offset: 0x0938 size: 8 bit */
 4215           SIUL_GPDI_8B_tag GPDI313;      /* offset: 0x0939 size: 8 bit */
 4216           SIUL_GPDI_8B_tag GPDI314;      /* offset: 0x093A size: 8 bit */
 4217           SIUL_GPDI_8B_tag GPDI315;      /* offset: 0x093B size: 8 bit */
 4218           SIUL_GPDI_8B_tag GPDI316;      /* offset: 0x093C size: 8 bit */
 4219           SIUL_GPDI_8B_tag GPDI317;      /* offset: 0x093D size: 8 bit */
 4220           SIUL_GPDI_8B_tag GPDI318;      /* offset: 0x093E size: 8 bit */
 4221           SIUL_GPDI_8B_tag GPDI319;      /* offset: 0x093F size: 8 bit */
 4222           SIUL_GPDI_8B_tag GPDI320;      /* offset: 0x0940 size: 8 bit */
 4223           SIUL_GPDI_8B_tag GPDI321;      /* offset: 0x0941 size: 8 bit */
 4224           SIUL_GPDI_8B_tag GPDI322;      /* offset: 0x0942 size: 8 bit */
 4225           SIUL_GPDI_8B_tag GPDI323;      /* offset: 0x0943 size: 8 bit */
 4226           SIUL_GPDI_8B_tag GPDI324;      /* offset: 0x0944 size: 8 bit */
 4227           SIUL_GPDI_8B_tag GPDI325;      /* offset: 0x0945 size: 8 bit */
 4228           SIUL_GPDI_8B_tag GPDI326;      /* offset: 0x0946 size: 8 bit */
 4229           SIUL_GPDI_8B_tag GPDI327;      /* offset: 0x0947 size: 8 bit */
 4230           SIUL_GPDI_8B_tag GPDI328;      /* offset: 0x0948 size: 8 bit */
 4231           SIUL_GPDI_8B_tag GPDI329;      /* offset: 0x0949 size: 8 bit */
 4232           SIUL_GPDI_8B_tag GPDI330;      /* offset: 0x094A size: 8 bit */
 4233           SIUL_GPDI_8B_tag GPDI331;      /* offset: 0x094B size: 8 bit */
 4234           SIUL_GPDI_8B_tag GPDI332;      /* offset: 0x094C size: 8 bit */
 4235           SIUL_GPDI_8B_tag GPDI333;      /* offset: 0x094D size: 8 bit */
 4236           SIUL_GPDI_8B_tag GPDI334;      /* offset: 0x094E size: 8 bit */
 4237           SIUL_GPDI_8B_tag GPDI335;      /* offset: 0x094F size: 8 bit */
 4238           SIUL_GPDI_8B_tag GPDI336;      /* offset: 0x0950 size: 8 bit */
 4239           SIUL_GPDI_8B_tag GPDI337;      /* offset: 0x0951 size: 8 bit */
 4240           SIUL_GPDI_8B_tag GPDI338;      /* offset: 0x0952 size: 8 bit */
 4241           SIUL_GPDI_8B_tag GPDI339;      /* offset: 0x0953 size: 8 bit */
 4242           SIUL_GPDI_8B_tag GPDI340;      /* offset: 0x0954 size: 8 bit */
 4243           SIUL_GPDI_8B_tag GPDI341;      /* offset: 0x0955 size: 8 bit */
 4244           SIUL_GPDI_8B_tag GPDI342;      /* offset: 0x0956 size: 8 bit */
 4245           SIUL_GPDI_8B_tag GPDI343;      /* offset: 0x0957 size: 8 bit */
 4246           SIUL_GPDI_8B_tag GPDI344;      /* offset: 0x0958 size: 8 bit */
 4247           SIUL_GPDI_8B_tag GPDI345;      /* offset: 0x0959 size: 8 bit */
 4248           SIUL_GPDI_8B_tag GPDI346;      /* offset: 0x095A size: 8 bit */
 4249           SIUL_GPDI_8B_tag GPDI347;      /* offset: 0x095B size: 8 bit */
 4250           SIUL_GPDI_8B_tag GPDI348;      /* offset: 0x095C size: 8 bit */
 4251           SIUL_GPDI_8B_tag GPDI349;      /* offset: 0x095D size: 8 bit */
 4252           SIUL_GPDI_8B_tag GPDI350;      /* offset: 0x095E size: 8 bit */
 4253           SIUL_GPDI_8B_tag GPDI351;      /* offset: 0x095F size: 8 bit */
 4254           SIUL_GPDI_8B_tag GPDI352;      /* offset: 0x0960 size: 8 bit */
 4255           SIUL_GPDI_8B_tag GPDI353;      /* offset: 0x0961 size: 8 bit */
 4256           SIUL_GPDI_8B_tag GPDI354;      /* offset: 0x0962 size: 8 bit */
 4257           SIUL_GPDI_8B_tag GPDI355;      /* offset: 0x0963 size: 8 bit */
 4258           SIUL_GPDI_8B_tag GPDI356;      /* offset: 0x0964 size: 8 bit */
 4259           SIUL_GPDI_8B_tag GPDI357;      /* offset: 0x0965 size: 8 bit */
 4260           SIUL_GPDI_8B_tag GPDI358;      /* offset: 0x0966 size: 8 bit */
 4261           SIUL_GPDI_8B_tag GPDI359;      /* offset: 0x0967 size: 8 bit */
 4262           SIUL_GPDI_8B_tag GPDI360;      /* offset: 0x0968 size: 8 bit */
 4263           SIUL_GPDI_8B_tag GPDI361;      /* offset: 0x0969 size: 8 bit */
 4264           SIUL_GPDI_8B_tag GPDI362;      /* offset: 0x096A size: 8 bit */
 4265           SIUL_GPDI_8B_tag GPDI363;      /* offset: 0x096B size: 8 bit */
 4266           SIUL_GPDI_8B_tag GPDI364;      /* offset: 0x096C size: 8 bit */
 4267           SIUL_GPDI_8B_tag GPDI365;      /* offset: 0x096D size: 8 bit */
 4268           SIUL_GPDI_8B_tag GPDI366;      /* offset: 0x096E size: 8 bit */
 4269           SIUL_GPDI_8B_tag GPDI367;      /* offset: 0x096F size: 8 bit */
 4270           SIUL_GPDI_8B_tag GPDI368;      /* offset: 0x0970 size: 8 bit */
 4271           SIUL_GPDI_8B_tag GPDI369;      /* offset: 0x0971 size: 8 bit */
 4272           SIUL_GPDI_8B_tag GPDI370;      /* offset: 0x0972 size: 8 bit */
 4273           SIUL_GPDI_8B_tag GPDI371;      /* offset: 0x0973 size: 8 bit */
 4274           SIUL_GPDI_8B_tag GPDI372;      /* offset: 0x0974 size: 8 bit */
 4275           SIUL_GPDI_8B_tag GPDI373;      /* offset: 0x0975 size: 8 bit */
 4276           SIUL_GPDI_8B_tag GPDI374;      /* offset: 0x0976 size: 8 bit */
 4277           SIUL_GPDI_8B_tag GPDI375;      /* offset: 0x0977 size: 8 bit */
 4278           SIUL_GPDI_8B_tag GPDI376;      /* offset: 0x0978 size: 8 bit */
 4279           SIUL_GPDI_8B_tag GPDI377;      /* offset: 0x0979 size: 8 bit */
 4280           SIUL_GPDI_8B_tag GPDI378;      /* offset: 0x097A size: 8 bit */
 4281           SIUL_GPDI_8B_tag GPDI379;      /* offset: 0x097B size: 8 bit */
 4282           SIUL_GPDI_8B_tag GPDI380;      /* offset: 0x097C size: 8 bit */
 4283           SIUL_GPDI_8B_tag GPDI381;      /* offset: 0x097D size: 8 bit */
 4284           SIUL_GPDI_8B_tag GPDI382;      /* offset: 0x097E size: 8 bit */
 4285           SIUL_GPDI_8B_tag GPDI383;      /* offset: 0x097F size: 8 bit */
 4286           SIUL_GPDI_8B_tag GPDI384;      /* offset: 0x0980 size: 8 bit */
 4287           SIUL_GPDI_8B_tag GPDI385;      /* offset: 0x0981 size: 8 bit */
 4288           SIUL_GPDI_8B_tag GPDI386;      /* offset: 0x0982 size: 8 bit */
 4289           SIUL_GPDI_8B_tag GPDI387;      /* offset: 0x0983 size: 8 bit */
 4290           SIUL_GPDI_8B_tag GPDI388;      /* offset: 0x0984 size: 8 bit */
 4291           SIUL_GPDI_8B_tag GPDI389;      /* offset: 0x0985 size: 8 bit */
 4292           SIUL_GPDI_8B_tag GPDI390;      /* offset: 0x0986 size: 8 bit */
 4293           SIUL_GPDI_8B_tag GPDI391;      /* offset: 0x0987 size: 8 bit */
 4294           SIUL_GPDI_8B_tag GPDI392;      /* offset: 0x0988 size: 8 bit */
 4295           SIUL_GPDI_8B_tag GPDI393;      /* offset: 0x0989 size: 8 bit */
 4296           SIUL_GPDI_8B_tag GPDI394;      /* offset: 0x098A size: 8 bit */
 4297           SIUL_GPDI_8B_tag GPDI395;      /* offset: 0x098B size: 8 bit */
 4298           SIUL_GPDI_8B_tag GPDI396;      /* offset: 0x098C size: 8 bit */
 4299           SIUL_GPDI_8B_tag GPDI397;      /* offset: 0x098D size: 8 bit */
 4300           SIUL_GPDI_8B_tag GPDI398;      /* offset: 0x098E size: 8 bit */
 4301           SIUL_GPDI_8B_tag GPDI399;      /* offset: 0x098F size: 8 bit */
 4302           SIUL_GPDI_8B_tag GPDI400;      /* offset: 0x0990 size: 8 bit */
 4303           SIUL_GPDI_8B_tag GPDI401;      /* offset: 0x0991 size: 8 bit */
 4304           SIUL_GPDI_8B_tag GPDI402;      /* offset: 0x0992 size: 8 bit */
 4305           SIUL_GPDI_8B_tag GPDI403;      /* offset: 0x0993 size: 8 bit */
 4306           SIUL_GPDI_8B_tag GPDI404;      /* offset: 0x0994 size: 8 bit */
 4307           SIUL_GPDI_8B_tag GPDI405;      /* offset: 0x0995 size: 8 bit */
 4308           SIUL_GPDI_8B_tag GPDI406;      /* offset: 0x0996 size: 8 bit */
 4309           SIUL_GPDI_8B_tag GPDI407;      /* offset: 0x0997 size: 8 bit */
 4310           SIUL_GPDI_8B_tag GPDI408;      /* offset: 0x0998 size: 8 bit */
 4311           SIUL_GPDI_8B_tag GPDI409;      /* offset: 0x0999 size: 8 bit */
 4312           SIUL_GPDI_8B_tag GPDI410;      /* offset: 0x099A size: 8 bit */
 4313           SIUL_GPDI_8B_tag GPDI411;      /* offset: 0x099B size: 8 bit */
 4314           SIUL_GPDI_8B_tag GPDI412;      /* offset: 0x099C size: 8 bit */
 4315           SIUL_GPDI_8B_tag GPDI413;      /* offset: 0x099D size: 8 bit */
 4316           SIUL_GPDI_8B_tag GPDI414;      /* offset: 0x099E size: 8 bit */
 4317           SIUL_GPDI_8B_tag GPDI415;      /* offset: 0x099F size: 8 bit */
 4318           SIUL_GPDI_8B_tag GPDI416;      /* offset: 0x09A0 size: 8 bit */
 4319           SIUL_GPDI_8B_tag GPDI417;      /* offset: 0x09A1 size: 8 bit */
 4320           SIUL_GPDI_8B_tag GPDI418;      /* offset: 0x09A2 size: 8 bit */
 4321           SIUL_GPDI_8B_tag GPDI419;      /* offset: 0x09A3 size: 8 bit */
 4322           SIUL_GPDI_8B_tag GPDI420;      /* offset: 0x09A4 size: 8 bit */
 4323           SIUL_GPDI_8B_tag GPDI421;      /* offset: 0x09A5 size: 8 bit */
 4324           SIUL_GPDI_8B_tag GPDI422;      /* offset: 0x09A6 size: 8 bit */
 4325           SIUL_GPDI_8B_tag GPDI423;      /* offset: 0x09A7 size: 8 bit */
 4326           SIUL_GPDI_8B_tag GPDI424;      /* offset: 0x09A8 size: 8 bit */
 4327           SIUL_GPDI_8B_tag GPDI425;      /* offset: 0x09A9 size: 8 bit */
 4328           SIUL_GPDI_8B_tag GPDI426;      /* offset: 0x09AA size: 8 bit */
 4329           SIUL_GPDI_8B_tag GPDI427;      /* offset: 0x09AB size: 8 bit */
 4330           SIUL_GPDI_8B_tag GPDI428;      /* offset: 0x09AC size: 8 bit */
 4331           SIUL_GPDI_8B_tag GPDI429;      /* offset: 0x09AD size: 8 bit */
 4332           SIUL_GPDI_8B_tag GPDI430;      /* offset: 0x09AE size: 8 bit */
 4333           SIUL_GPDI_8B_tag GPDI431;      /* offset: 0x09AF size: 8 bit */
 4334           SIUL_GPDI_8B_tag GPDI432;      /* offset: 0x09B0 size: 8 bit */
 4335           SIUL_GPDI_8B_tag GPDI433;      /* offset: 0x09B1 size: 8 bit */
 4336           SIUL_GPDI_8B_tag GPDI434;      /* offset: 0x09B2 size: 8 bit */
 4337           SIUL_GPDI_8B_tag GPDI435;      /* offset: 0x09B3 size: 8 bit */
 4338           SIUL_GPDI_8B_tag GPDI436;      /* offset: 0x09B4 size: 8 bit */
 4339           SIUL_GPDI_8B_tag GPDI437;      /* offset: 0x09B5 size: 8 bit */
 4340           SIUL_GPDI_8B_tag GPDI438;      /* offset: 0x09B6 size: 8 bit */
 4341           SIUL_GPDI_8B_tag GPDI439;      /* offset: 0x09B7 size: 8 bit */
 4342           SIUL_GPDI_8B_tag GPDI440;      /* offset: 0x09B8 size: 8 bit */
 4343           SIUL_GPDI_8B_tag GPDI441;      /* offset: 0x09B9 size: 8 bit */
 4344           SIUL_GPDI_8B_tag GPDI442;      /* offset: 0x09BA size: 8 bit */
 4345           SIUL_GPDI_8B_tag GPDI443;      /* offset: 0x09BB size: 8 bit */
 4346           SIUL_GPDI_8B_tag GPDI444;      /* offset: 0x09BC size: 8 bit */
 4347           SIUL_GPDI_8B_tag GPDI445;      /* offset: 0x09BD size: 8 bit */
 4348           SIUL_GPDI_8B_tag GPDI446;      /* offset: 0x09BE size: 8 bit */
 4349           SIUL_GPDI_8B_tag GPDI447;      /* offset: 0x09BF size: 8 bit */
 4350           SIUL_GPDI_8B_tag GPDI448;      /* offset: 0x09C0 size: 8 bit */
 4351           SIUL_GPDI_8B_tag GPDI449;      /* offset: 0x09C1 size: 8 bit */
 4352           SIUL_GPDI_8B_tag GPDI450;      /* offset: 0x09C2 size: 8 bit */
 4353           SIUL_GPDI_8B_tag GPDI451;      /* offset: 0x09C3 size: 8 bit */
 4354           SIUL_GPDI_8B_tag GPDI452;      /* offset: 0x09C4 size: 8 bit */
 4355           SIUL_GPDI_8B_tag GPDI453;      /* offset: 0x09C5 size: 8 bit */
 4356           SIUL_GPDI_8B_tag GPDI454;      /* offset: 0x09C6 size: 8 bit */
 4357           SIUL_GPDI_8B_tag GPDI455;      /* offset: 0x09C7 size: 8 bit */
 4358           SIUL_GPDI_8B_tag GPDI456;      /* offset: 0x09C8 size: 8 bit */
 4359           SIUL_GPDI_8B_tag GPDI457;      /* offset: 0x09C9 size: 8 bit */
 4360           SIUL_GPDI_8B_tag GPDI458;      /* offset: 0x09CA size: 8 bit */
 4361           SIUL_GPDI_8B_tag GPDI459;      /* offset: 0x09CB size: 8 bit */
 4362           SIUL_GPDI_8B_tag GPDI460;      /* offset: 0x09CC size: 8 bit */
 4363           SIUL_GPDI_8B_tag GPDI461;      /* offset: 0x09CD size: 8 bit */
 4364           SIUL_GPDI_8B_tag GPDI462;      /* offset: 0x09CE size: 8 bit */
 4365           SIUL_GPDI_8B_tag GPDI463;      /* offset: 0x09CF size: 8 bit */
 4366           SIUL_GPDI_8B_tag GPDI464;      /* offset: 0x09D0 size: 8 bit */
 4367           SIUL_GPDI_8B_tag GPDI465;      /* offset: 0x09D1 size: 8 bit */
 4368           SIUL_GPDI_8B_tag GPDI466;      /* offset: 0x09D2 size: 8 bit */
 4369           SIUL_GPDI_8B_tag GPDI467;      /* offset: 0x09D3 size: 8 bit */
 4370           SIUL_GPDI_8B_tag GPDI468;      /* offset: 0x09D4 size: 8 bit */
 4371           SIUL_GPDI_8B_tag GPDI469;      /* offset: 0x09D5 size: 8 bit */
 4372           SIUL_GPDI_8B_tag GPDI470;      /* offset: 0x09D6 size: 8 bit */
 4373           SIUL_GPDI_8B_tag GPDI471;      /* offset: 0x09D7 size: 8 bit */
 4374           SIUL_GPDI_8B_tag GPDI472;      /* offset: 0x09D8 size: 8 bit */
 4375           SIUL_GPDI_8B_tag GPDI473;      /* offset: 0x09D9 size: 8 bit */
 4376           SIUL_GPDI_8B_tag GPDI474;      /* offset: 0x09DA size: 8 bit */
 4377           SIUL_GPDI_8B_tag GPDI475;      /* offset: 0x09DB size: 8 bit */
 4378           SIUL_GPDI_8B_tag GPDI476;      /* offset: 0x09DC size: 8 bit */
 4379           SIUL_GPDI_8B_tag GPDI477;      /* offset: 0x09DD size: 8 bit */
 4380           SIUL_GPDI_8B_tag GPDI478;      /* offset: 0x09DE size: 8 bit */
 4381           SIUL_GPDI_8B_tag GPDI479;      /* offset: 0x09DF size: 8 bit */
 4382           SIUL_GPDI_8B_tag GPDI480;      /* offset: 0x09E0 size: 8 bit */
 4383           SIUL_GPDI_8B_tag GPDI481;      /* offset: 0x09E1 size: 8 bit */
 4384           SIUL_GPDI_8B_tag GPDI482;      /* offset: 0x09E2 size: 8 bit */
 4385           SIUL_GPDI_8B_tag GPDI483;      /* offset: 0x09E3 size: 8 bit */
 4386           SIUL_GPDI_8B_tag GPDI484;      /* offset: 0x09E4 size: 8 bit */
 4387           SIUL_GPDI_8B_tag GPDI485;      /* offset: 0x09E5 size: 8 bit */
 4388           SIUL_GPDI_8B_tag GPDI486;      /* offset: 0x09E6 size: 8 bit */
 4389           SIUL_GPDI_8B_tag GPDI487;      /* offset: 0x09E7 size: 8 bit */
 4390           SIUL_GPDI_8B_tag GPDI488;      /* offset: 0x09E8 size: 8 bit */
 4391           SIUL_GPDI_8B_tag GPDI489;      /* offset: 0x09E9 size: 8 bit */
 4392           SIUL_GPDI_8B_tag GPDI490;      /* offset: 0x09EA size: 8 bit */
 4393           SIUL_GPDI_8B_tag GPDI491;      /* offset: 0x09EB size: 8 bit */
 4394           SIUL_GPDI_8B_tag GPDI492;      /* offset: 0x09EC size: 8 bit */
 4395           SIUL_GPDI_8B_tag GPDI493;      /* offset: 0x09ED size: 8 bit */
 4396           SIUL_GPDI_8B_tag GPDI494;      /* offset: 0x09EE size: 8 bit */
 4397           SIUL_GPDI_8B_tag GPDI495;      /* offset: 0x09EF size: 8 bit */
 4398           SIUL_GPDI_8B_tag GPDI496;      /* offset: 0x09F0 size: 8 bit */
 4399           SIUL_GPDI_8B_tag GPDI497;      /* offset: 0x09F1 size: 8 bit */
 4400           SIUL_GPDI_8B_tag GPDI498;      /* offset: 0x09F2 size: 8 bit */
 4401           SIUL_GPDI_8B_tag GPDI499;      /* offset: 0x09F3 size: 8 bit */
 4402           SIUL_GPDI_8B_tag GPDI500;      /* offset: 0x09F4 size: 8 bit */
 4403           SIUL_GPDI_8B_tag GPDI501;      /* offset: 0x09F5 size: 8 bit */
 4404           SIUL_GPDI_8B_tag GPDI502;      /* offset: 0x09F6 size: 8 bit */
 4405           SIUL_GPDI_8B_tag GPDI503;      /* offset: 0x09F7 size: 8 bit */
 4406           SIUL_GPDI_8B_tag GPDI504;      /* offset: 0x09F8 size: 8 bit */
 4407           SIUL_GPDI_8B_tag GPDI505;      /* offset: 0x09F9 size: 8 bit */
 4408           SIUL_GPDI_8B_tag GPDI506;      /* offset: 0x09FA size: 8 bit */
 4409           SIUL_GPDI_8B_tag GPDI507;      /* offset: 0x09FB size: 8 bit */
 4410           SIUL_GPDI_8B_tag GPDI508;      /* offset: 0x09FC size: 8 bit */
 4411           SIUL_GPDI_8B_tag GPDI509;      /* offset: 0x09FD size: 8 bit */
 4412           SIUL_GPDI_8B_tag GPDI510;      /* offset: 0x09FE size: 8 bit */
 4413           SIUL_GPDI_8B_tag GPDI511;      /* offset: 0x09FF size: 8 bit */
 4414         };
 4415       };
 4416   
 4417       int8_t SIUL_reserved_0A00[512];
 4418       union {
 4419         /* PGPDO - Parallel GPIO Pad Data Out Register */
 4420         SIUL_PGPDO_16B_tag PGPDO[32];    /* offset: 0x0C00  (0x0002 x 32) */
 4421         struct {
 4422           /* PGPDO - Parallel GPIO Pad Data Out Register */
 4423           SIUL_PGPDO_16B_tag PGPDO0;     /* offset: 0x0C00 size: 16 bit */
 4424           SIUL_PGPDO_16B_tag PGPDO1;     /* offset: 0x0C02 size: 16 bit */
 4425           SIUL_PGPDO_16B_tag PGPDO2;     /* offset: 0x0C04 size: 16 bit */
 4426           SIUL_PGPDO_16B_tag PGPDO3;     /* offset: 0x0C06 size: 16 bit */
 4427           SIUL_PGPDO_16B_tag PGPDO4;     /* offset: 0x0C08 size: 16 bit */
 4428           SIUL_PGPDO_16B_tag PGPDO5;     /* offset: 0x0C0A size: 16 bit */
 4429           SIUL_PGPDO_16B_tag PGPDO6;     /* offset: 0x0C0C size: 16 bit */
 4430           SIUL_PGPDO_16B_tag PGPDO7;     /* offset: 0x0C0E size: 16 bit */
 4431           SIUL_PGPDO_16B_tag PGPDO8;     /* offset: 0x0C10 size: 16 bit */
 4432           SIUL_PGPDO_16B_tag PGPDO9;     /* offset: 0x0C12 size: 16 bit */
 4433           SIUL_PGPDO_16B_tag PGPDO10;    /* offset: 0x0C14 size: 16 bit */
 4434           SIUL_PGPDO_16B_tag PGPDO11;    /* offset: 0x0C16 size: 16 bit */
 4435           SIUL_PGPDO_16B_tag PGPDO12;    /* offset: 0x0C18 size: 16 bit */
 4436           SIUL_PGPDO_16B_tag PGPDO13;    /* offset: 0x0C1A size: 16 bit */
 4437           SIUL_PGPDO_16B_tag PGPDO14;    /* offset: 0x0C1C size: 16 bit */
 4438           SIUL_PGPDO_16B_tag PGPDO15;    /* offset: 0x0C1E size: 16 bit */
 4439           SIUL_PGPDO_16B_tag PGPDO16;    /* offset: 0x0C20 size: 16 bit */
 4440           SIUL_PGPDO_16B_tag PGPDO17;    /* offset: 0x0C22 size: 16 bit */
 4441           SIUL_PGPDO_16B_tag PGPDO18;    /* offset: 0x0C24 size: 16 bit */
 4442           SIUL_PGPDO_16B_tag PGPDO19;    /* offset: 0x0C26 size: 16 bit */
 4443           SIUL_PGPDO_16B_tag PGPDO20;    /* offset: 0x0C28 size: 16 bit */
 4444           SIUL_PGPDO_16B_tag PGPDO21;    /* offset: 0x0C2A size: 16 bit */
 4445           SIUL_PGPDO_16B_tag PGPDO22;    /* offset: 0x0C2C size: 16 bit */
 4446           SIUL_PGPDO_16B_tag PGPDO23;    /* offset: 0x0C2E size: 16 bit */
 4447           SIUL_PGPDO_16B_tag PGPDO24;    /* offset: 0x0C30 size: 16 bit */
 4448           SIUL_PGPDO_16B_tag PGPDO25;    /* offset: 0x0C32 size: 16 bit */
 4449           SIUL_PGPDO_16B_tag PGPDO26;    /* offset: 0x0C34 size: 16 bit */
 4450           SIUL_PGPDO_16B_tag PGPDO27;    /* offset: 0x0C36 size: 16 bit */
 4451           SIUL_PGPDO_16B_tag PGPDO28;    /* offset: 0x0C38 size: 16 bit */
 4452           SIUL_PGPDO_16B_tag PGPDO29;    /* offset: 0x0C3A size: 16 bit */
 4453           SIUL_PGPDO_16B_tag PGPDO30;    /* offset: 0x0C3C size: 16 bit */
 4454           SIUL_PGPDO_16B_tag PGPDO31;    /* offset: 0x0C3E size: 16 bit */
 4455         };
 4456       };
 4457   
 4458       union {
 4459         /* PGPDI - Parallel GPIO Pad Data In Register */
 4460         SIUL_PGPDI_16B_tag PGPDI[32];    /* offset: 0x0C40  (0x0002 x 32) */
 4461         struct {
 4462           /* PGPDI - Parallel GPIO Pad Data In Register */
 4463           SIUL_PGPDI_16B_tag PGPDI0;     /* offset: 0x0C40 size: 16 bit */
 4464           SIUL_PGPDI_16B_tag PGPDI1;     /* offset: 0x0C42 size: 16 bit */
 4465           SIUL_PGPDI_16B_tag PGPDI2;     /* offset: 0x0C44 size: 16 bit */
 4466           SIUL_PGPDI_16B_tag PGPDI3;     /* offset: 0x0C46 size: 16 bit */
 4467           SIUL_PGPDI_16B_tag PGPDI4;     /* offset: 0x0C48 size: 16 bit */
 4468           SIUL_PGPDI_16B_tag PGPDI5;     /* offset: 0x0C4A size: 16 bit */
 4469           SIUL_PGPDI_16B_tag PGPDI6;     /* offset: 0x0C4C size: 16 bit */
 4470           SIUL_PGPDI_16B_tag PGPDI7;     /* offset: 0x0C4E size: 16 bit */
 4471           SIUL_PGPDI_16B_tag PGPDI8;     /* offset: 0x0C50 size: 16 bit */
 4472           SIUL_PGPDI_16B_tag PGPDI9;     /* offset: 0x0C52 size: 16 bit */
 4473           SIUL_PGPDI_16B_tag PGPDI10;    /* offset: 0x0C54 size: 16 bit */
 4474           SIUL_PGPDI_16B_tag PGPDI11;    /* offset: 0x0C56 size: 16 bit */
 4475           SIUL_PGPDI_16B_tag PGPDI12;    /* offset: 0x0C58 size: 16 bit */
 4476           SIUL_PGPDI_16B_tag PGPDI13;    /* offset: 0x0C5A size: 16 bit */
 4477           SIUL_PGPDI_16B_tag PGPDI14;    /* offset: 0x0C5C size: 16 bit */
 4478           SIUL_PGPDI_16B_tag PGPDI15;    /* offset: 0x0C5E size: 16 bit */
 4479           SIUL_PGPDI_16B_tag PGPDI16;    /* offset: 0x0C60 size: 16 bit */
 4480           SIUL_PGPDI_16B_tag PGPDI17;    /* offset: 0x0C62 size: 16 bit */
 4481           SIUL_PGPDI_16B_tag PGPDI18;    /* offset: 0x0C64 size: 16 bit */
 4482           SIUL_PGPDI_16B_tag PGPDI19;    /* offset: 0x0C66 size: 16 bit */
 4483           SIUL_PGPDI_16B_tag PGPDI20;    /* offset: 0x0C68 size: 16 bit */
 4484           SIUL_PGPDI_16B_tag PGPDI21;    /* offset: 0x0C6A size: 16 bit */
 4485           SIUL_PGPDI_16B_tag PGPDI22;    /* offset: 0x0C6C size: 16 bit */
 4486           SIUL_PGPDI_16B_tag PGPDI23;    /* offset: 0x0C6E size: 16 bit */
 4487           SIUL_PGPDI_16B_tag PGPDI24;    /* offset: 0x0C70 size: 16 bit */
 4488           SIUL_PGPDI_16B_tag PGPDI25;    /* offset: 0x0C72 size: 16 bit */
 4489           SIUL_PGPDI_16B_tag PGPDI26;    /* offset: 0x0C74 size: 16 bit */
 4490           SIUL_PGPDI_16B_tag PGPDI27;    /* offset: 0x0C76 size: 16 bit */
 4491           SIUL_PGPDI_16B_tag PGPDI28;    /* offset: 0x0C78 size: 16 bit */
 4492           SIUL_PGPDI_16B_tag PGPDI29;    /* offset: 0x0C7A size: 16 bit */
 4493           SIUL_PGPDI_16B_tag PGPDI30;    /* offset: 0x0C7C size: 16 bit */
 4494           SIUL_PGPDI_16B_tag PGPDI31;    /* offset: 0x0C7E size: 16 bit */
 4495         };
 4496       };
 4497   
 4498       union {
 4499         /* MPGPDO - Masked Parallel GPIO Pad Data Out Register */
 4500         SIUL_MPGPDO_32B_tag MPGPDO[32];  /* offset: 0x0C80  (0x0004 x 32) */
 4501         struct {
 4502           /* MPGPDO - Masked Parallel GPIO Pad Data Out Register */
 4503           SIUL_MPGPDO_32B_tag MPGPDO0;   /* offset: 0x0C80 size: 32 bit */
 4504           SIUL_MPGPDO_32B_tag MPGPDO1;   /* offset: 0x0C84 size: 32 bit */
 4505           SIUL_MPGPDO_32B_tag MPGPDO2;   /* offset: 0x0C88 size: 32 bit */
 4506           SIUL_MPGPDO_32B_tag MPGPDO3;   /* offset: 0x0C8C size: 32 bit */
 4507           SIUL_MPGPDO_32B_tag MPGPDO4;   /* offset: 0x0C90 size: 32 bit */
 4508           SIUL_MPGPDO_32B_tag MPGPDO5;   /* offset: 0x0C94 size: 32 bit */
 4509           SIUL_MPGPDO_32B_tag MPGPDO6;   /* offset: 0x0C98 size: 32 bit */
 4510           SIUL_MPGPDO_32B_tag MPGPDO7;   /* offset: 0x0C9C size: 32 bit */
 4511           SIUL_MPGPDO_32B_tag MPGPDO8;   /* offset: 0x0CA0 size: 32 bit */
 4512           SIUL_MPGPDO_32B_tag MPGPDO9;   /* offset: 0x0CA4 size: 32 bit */
 4513           SIUL_MPGPDO_32B_tag MPGPDO10;  /* offset: 0x0CA8 size: 32 bit */
 4514           SIUL_MPGPDO_32B_tag MPGPDO11;  /* offset: 0x0CAC size: 32 bit */
 4515           SIUL_MPGPDO_32B_tag MPGPDO12;  /* offset: 0x0CB0 size: 32 bit */
 4516           SIUL_MPGPDO_32B_tag MPGPDO13;  /* offset: 0x0CB4 size: 32 bit */
 4517           SIUL_MPGPDO_32B_tag MPGPDO14;  /* offset: 0x0CB8 size: 32 bit */
 4518           SIUL_MPGPDO_32B_tag MPGPDO15;  /* offset: 0x0CBC size: 32 bit */
 4519           SIUL_MPGPDO_32B_tag MPGPDO16;  /* offset: 0x0CC0 size: 32 bit */
 4520           SIUL_MPGPDO_32B_tag MPGPDO17;  /* offset: 0x0CC4 size: 32 bit */
 4521           SIUL_MPGPDO_32B_tag MPGPDO18;  /* offset: 0x0CC8 size: 32 bit */
 4522           SIUL_MPGPDO_32B_tag MPGPDO19;  /* offset: 0x0CCC size: 32 bit */
 4523           SIUL_MPGPDO_32B_tag MPGPDO20;  /* offset: 0x0CD0 size: 32 bit */
 4524           SIUL_MPGPDO_32B_tag MPGPDO21;  /* offset: 0x0CD4 size: 32 bit */
 4525           SIUL_MPGPDO_32B_tag MPGPDO22;  /* offset: 0x0CD8 size: 32 bit */
 4526           SIUL_MPGPDO_32B_tag MPGPDO23;  /* offset: 0x0CDC size: 32 bit */
 4527           SIUL_MPGPDO_32B_tag MPGPDO24;  /* offset: 0x0CE0 size: 32 bit */
 4528           SIUL_MPGPDO_32B_tag MPGPDO25;  /* offset: 0x0CE4 size: 32 bit */
 4529           SIUL_MPGPDO_32B_tag MPGPDO26;  /* offset: 0x0CE8 size: 32 bit */
 4530           SIUL_MPGPDO_32B_tag MPGPDO27;  /* offset: 0x0CEC size: 32 bit */
 4531           SIUL_MPGPDO_32B_tag MPGPDO28;  /* offset: 0x0CF0 size: 32 bit */
 4532           SIUL_MPGPDO_32B_tag MPGPDO29;  /* offset: 0x0CF4 size: 32 bit */
 4533           SIUL_MPGPDO_32B_tag MPGPDO30;  /* offset: 0x0CF8 size: 32 bit */
 4534           SIUL_MPGPDO_32B_tag MPGPDO31;  /* offset: 0x0CFC size: 32 bit */
 4535         };
 4536       };
 4537   
 4538       int8_t SIUL_reserved_0D00[768];
 4539       union {
 4540         /* IFMC - Interrupt Filter Maximum Counter Register */
 4541         SIUL_IFMC_32B_tag IFMC[32];      /* offset: 0x1000  (0x0004 x 32) */
 4542         struct {
 4543           /* IFMC - Interrupt Filter Maximum Counter Register */
 4544           SIUL_IFMC_32B_tag IFMC0;       /* offset: 0x1000 size: 32 bit */
 4545           SIUL_IFMC_32B_tag IFMC1;       /* offset: 0x1004 size: 32 bit */
 4546           SIUL_IFMC_32B_tag IFMC2;       /* offset: 0x1008 size: 32 bit */
 4547           SIUL_IFMC_32B_tag IFMC3;       /* offset: 0x100C size: 32 bit */
 4548           SIUL_IFMC_32B_tag IFMC4;       /* offset: 0x1010 size: 32 bit */
 4549           SIUL_IFMC_32B_tag IFMC5;       /* offset: 0x1014 size: 32 bit */
 4550           SIUL_IFMC_32B_tag IFMC6;       /* offset: 0x1018 size: 32 bit */
 4551           SIUL_IFMC_32B_tag IFMC7;       /* offset: 0x101C size: 32 bit */
 4552           SIUL_IFMC_32B_tag IFMC8;       /* offset: 0x1020 size: 32 bit */
 4553           SIUL_IFMC_32B_tag IFMC9;       /* offset: 0x1024 size: 32 bit */
 4554           SIUL_IFMC_32B_tag IFMC10;      /* offset: 0x1028 size: 32 bit */
 4555           SIUL_IFMC_32B_tag IFMC11;      /* offset: 0x102C size: 32 bit */
 4556           SIUL_IFMC_32B_tag IFMC12;      /* offset: 0x1030 size: 32 bit */
 4557           SIUL_IFMC_32B_tag IFMC13;      /* offset: 0x1034 size: 32 bit */
 4558           SIUL_IFMC_32B_tag IFMC14;      /* offset: 0x1038 size: 32 bit */
 4559           SIUL_IFMC_32B_tag IFMC15;      /* offset: 0x103C size: 32 bit */
 4560           SIUL_IFMC_32B_tag IFMC16;      /* offset: 0x1040 size: 32 bit */
 4561           SIUL_IFMC_32B_tag IFMC17;      /* offset: 0x1044 size: 32 bit */
 4562           SIUL_IFMC_32B_tag IFMC18;      /* offset: 0x1048 size: 32 bit */
 4563           SIUL_IFMC_32B_tag IFMC19;      /* offset: 0x104C size: 32 bit */
 4564           SIUL_IFMC_32B_tag IFMC20;      /* offset: 0x1050 size: 32 bit */
 4565           SIUL_IFMC_32B_tag IFMC21;      /* offset: 0x1054 size: 32 bit */
 4566           SIUL_IFMC_32B_tag IFMC22;      /* offset: 0x1058 size: 32 bit */
 4567           SIUL_IFMC_32B_tag IFMC23;      /* offset: 0x105C size: 32 bit */
 4568           SIUL_IFMC_32B_tag IFMC24;      /* offset: 0x1060 size: 32 bit */
 4569           SIUL_IFMC_32B_tag IFMC25;      /* offset: 0x1064 size: 32 bit */
 4570           SIUL_IFMC_32B_tag IFMC26;      /* offset: 0x1068 size: 32 bit */
 4571           SIUL_IFMC_32B_tag IFMC27;      /* offset: 0x106C size: 32 bit */
 4572           SIUL_IFMC_32B_tag IFMC28;      /* offset: 0x1070 size: 32 bit */
 4573           SIUL_IFMC_32B_tag IFMC29;      /* offset: 0x1074 size: 32 bit */
 4574           SIUL_IFMC_32B_tag IFMC30;      /* offset: 0x1078 size: 32 bit */
 4575           SIUL_IFMC_32B_tag IFMC31;      /* offset: 0x107C size: 32 bit */
 4576         };
 4577       };
 4578   
 4579       /* IFCPR - Inerrupt Filter Clock Prescaler Register */
 4580       SIUL_IFCPR_32B_tag IFCPR;          /* offset: 0x1080 size: 32 bit */
 4581       int8_t SIUL_reserved_1084[12156];
 4582     } SIUL_tag;
 4583   
 4584   #define SIUL                           (*(volatile SIUL_tag *) 0xC3F90000UL)
 4585   
 4586     /****************************************************************/
 4587     /*                                                              */
 4588     /* Module: WKPU  */
 4589     /*                                                              */
 4590     /****************************************************************/
 4591     typedef union {                      /* WKPU_NSR - NMI Status Flag Register */
 4592       vuint32_t R;
 4593       struct {
 4594         vuint32_t NIF0:1;                /* NMI Status Flag 0 */
 4595         vuint32_t NOVF0:1;               /* NMI Overrun Status Flag 0 */
 4596        vuint32_t:
 4597         30;
 4598       } B;
 4599     } WKPU_NSR_32B_tag;
 4600   
 4601     typedef union {                      /* WKPU_NCR - NMI Configuration Register */
 4602       vuint32_t R;
 4603       struct {
 4604         vuint32_t NLOCK0:1;              /* NMI Configuration Lock Register 0 */
 4605         vuint32_t NDSS0:2;               /* NMI Destination Source Select 0 */
 4606         vuint32_t NWRE0:1;               /* NMI Wakeup Request Enable 0 */
 4607        vuint32_t:
 4608         1;
 4609         vuint32_t NREE0:1;               /* NMI Rising Edge Events Enable 0 */
 4610         vuint32_t NFEE0:1;               /* NMI Falling Edge Events Enable 0 */
 4611         vuint32_t NFE0:1;                /* NMI Filter Enable 0 */
 4612        vuint32_t:
 4613         24;
 4614       } B;
 4615     } WKPU_NCR_32B_tag;
 4616   
 4617     typedef struct WKPU_struct_tag {
 4618       /* WKPU_NSR - NMI Status Flag Register */
 4619       WKPU_NSR_32B_tag NSR;              /* offset: 0x0000 size: 32 bit */
 4620       int8_t WKPU_reserved_0004[4];
 4621   
 4622       /* WKPU_NCR - NMI Configuration Register */
 4623       WKPU_NCR_32B_tag NCR;              /* offset: 0x0008 size: 32 bit */
 4624       int8_t WKPU_reserved_000C[16372];
 4625     } WKPU_tag;
 4626   
 4627   #define WKPU                           (*(volatile WKPU_tag *) 0xC3F94000UL)
 4628   
 4629     /****************************************************************/
 4630     /*                                                              */
 4631     /* Module: SSCM  */
 4632     /*                                                              */
 4633     /****************************************************************/
 4634     typedef union {                      /* SSCM_STATUS - System Status Register */
 4635       vuint16_t R;
 4636       struct {
 4637         vuint16_t LSM:1;                 /* Lock Step Mode */
 4638         vuint16_t CER:1;                 /* Configuration Error */
 4639        vuint16_t:
 4640         1;
 4641         vuint16_t NXEN1:1;               /* Processor 1 Nexus enabled */
 4642         vuint16_t NXEN:1;                /* Processor 0 Nexus enabled */
 4643         vuint16_t PUB:1;                 /* Public Serial Access Status */
 4644         vuint16_t SEC:1;                 /* Security Status */
 4645        vuint16_t:
 4646         1;
 4647         vuint16_t BMODE:3;               /* Device Boot Mode */
 4648         vuint16_t VLE:1;                 /* Variable Length Instruction Mode */
 4649         vuint16_t ABD:1;                 /* Autobaud detection */
 4650        vuint16_t:
 4651         3;
 4652       } B;
 4653     } SSCM_STATUS_16B_tag;
 4654   
 4655     typedef union {                      /* SSCM_MEMCONFIG - System Memory Configuration Register */
 4656       vuint16_t R;
 4657       struct {
 4658         vuint16_t JPIN:10;               /* JTAG Part ID Number */
 4659         vuint16_t IVLD:1;                /* Instruction Flash Valid */
 4660         vuint16_t MREV:4;                /* Minor Mask Revision */
 4661         vuint16_t DVLD:1;                /* Data Flash Valid */
 4662       } B;
 4663     } SSCM_MEMCONFIG_16B_tag;
 4664   
 4665     typedef union {                      /* SSCM_ERROR - Error Configuration */
 4666       vuint16_t R;
 4667       struct {
 4668        vuint16_t:
 4669         14;
 4670         vuint16_t PAE:1;                 /* Peripheral Bus Abort Enable */
 4671         vuint16_t RAE:1;                 /* Register Bus Abort Enable */
 4672       } B;
 4673     } SSCM_ERROR_16B_tag;
 4674   
 4675     typedef union {                      /* SSCM_DEBUGPORT - Debug Status Port Register */
 4676       vuint16_t R;
 4677       struct {
 4678        vuint16_t:
 4679         13;
 4680         vuint16_t DEBUG_MODE:3;          /* Debug Status Port Mode */
 4681       } B;
 4682     } SSCM_DEBUGPORT_16B_tag;
 4683   
 4684     typedef union {                      /* SSCM_PWCMPH - Password Comparison Register High */
 4685       vuint32_t R;
 4686       struct {
 4687         vuint32_t PWD_HI:32;             /* Password High */
 4688       } B;
 4689     } SSCM_PWCMPH_32B_tag;
 4690   
 4691     typedef union {                      /* SSCM_PWCMPL - Password Comparison Register Low */
 4692       vuint32_t R;
 4693       struct {
 4694         vuint32_t PWD_LO:32;             /* Password Low */
 4695       } B;
 4696     } SSCM_PWCMPL_32B_tag;
 4697   
 4698     typedef union {                      /* SSCM_DPMBOOT - Decoupled Parallel Boot Register */
 4699       vuint32_t R;
 4700       struct {
 4701         vuint32_t P2BOOT:30;             /* boot location 2nd processor */
 4702         vuint32_t DVLE:1;                /* VLE mode for 2nd processor */
 4703        vuint32_t:
 4704         1;
 4705       } B;
 4706     } SSCM_DPMBOOT_32B_tag;
 4707   
 4708     typedef union {                      /* SSCM_DPMKEY - Boot Key Register */
 4709       vuint32_t R;
 4710       struct {
 4711         vuint32_t KEY:32;                /* Boot Control Key */
 4712       } B;
 4713     } SSCM_DPMKEY_32B_tag;
 4714   
 4715     typedef union {                      /* SSCM_UOPS - User Option Status Register */
 4716       vuint32_t R;
 4717       struct {
 4718         vuint32_t UOPT:32;               /* User Option Bits */
 4719       } B;
 4720     } SSCM_UOPS_32B_tag;
 4721   
 4722     typedef union {                      /* SSCM_SCTR - SSCM Control Register */
 4723       vuint32_t R;
 4724       struct {
 4725        vuint32_t:
 4726         29;
 4727         vuint32_t TFE:1;                 /* Test Flash Enable */
 4728         vuint32_t DSL:1;                 /* Disable Software-Controlled MBIST */
 4729         vuint32_t DSM:1;                 /* Disable Software-Controlled LBIST */
 4730       } B;
 4731     } SSCM_SCTR_32B_tag;
 4732   
 4733     typedef union {                      /* SSCM_PSA - Processor Start Address Register */
 4734       vuint32_t R;
 4735       struct {
 4736         vuint32_t SADR:32;               /* Start Address */
 4737       } B;
 4738     } SSCM_PSA_32B_tag;
 4739   
 4740     typedef union {                      /* SSCM_CLEN - Code Length Register */
 4741       vuint32_t R;
 4742       struct {
 4743         vuint32_t CL:32;                 /* Length of the code for the identified boot sector */
 4744       } B;
 4745     } SSCM_CLEN_32B_tag;
 4746   
 4747     typedef struct SSCM_struct_tag {
 4748       /* SSCM_STATUS - System Status Register */
 4749       SSCM_STATUS_16B_tag STATUS;        /* offset: 0x0000 size: 16 bit */
 4750   
 4751       /* SSCM_MEMCONFIG - System Memory Configuration Register */
 4752       SSCM_MEMCONFIG_16B_tag MEMCONFIG;  /* offset: 0x0002 size: 16 bit */
 4753       int8_t SSCM_reserved_0004[2];
 4754   
 4755       /* SSCM_ERROR - Error Configuration */
 4756       SSCM_ERROR_16B_tag ERROR;          /* offset: 0x0006 size: 16 bit */
 4757   
 4758       /* SSCM_DEBUGPORT - Debug Status Port Register */
 4759       SSCM_DEBUGPORT_16B_tag DEBUGPORT;  /* offset: 0x0008 size: 16 bit */
 4760       int8_t SSCM_reserved_000A[2];
 4761   
 4762       /* SSCM_PWCMPH - Password Comparison Register High */
 4763       SSCM_PWCMPH_32B_tag PWCMPH;        /* offset: 0x000C size: 32 bit */
 4764   
 4765       /* SSCM_PWCMPL - Password Comparison Register Low */
 4766       SSCM_PWCMPL_32B_tag PWCMPL;        /* offset: 0x0010 size: 32 bit */
 4767       int8_t SSCM_reserved_0014[4];
 4768   
 4769       /* SSCM_DPMBOOT - Decoupled Parallel Boot Register */
 4770       SSCM_DPMBOOT_32B_tag DPMBOOT;      /* offset: 0x0018 size: 32 bit */
 4771   
 4772       /* SSCM_DPMKEY - Boot Key Register */
 4773       SSCM_DPMKEY_32B_tag DPMKEY;        /* offset: 0x001C size: 32 bit */
 4774   
 4775       /* SSCM_UOPS - User Option Status Register */
 4776       SSCM_UOPS_32B_tag UOPS;            /* offset: 0x0020 size: 32 bit */
 4777   
 4778       /* SSCM_SCTR - SSCM Control Register */
 4779       SSCM_SCTR_32B_tag SCTR;            /* offset: 0x0024 size: 32 bit */
 4780   
 4781       /* SSCM_PSA - Processor Start Address Register */
 4782       SSCM_PSA_32B_tag PSA;              /* offset: 0x0028 size: 32 bit */
 4783   
 4784       /* SSCM_CLEN - Code Length Register */
 4785       SSCM_CLEN_32B_tag CLEN;            /* offset: 0x002C size: 32 bit */
 4786       int8_t SSCM_reserved_0030[16336];
 4787     } SSCM_tag;
 4788   
 4789   #define SSCM                           (*(volatile SSCM_tag *) 0xC3FD8000UL)
 4790   
 4791     /****************************************************************/
 4792     /*                                                              */
 4793     /* Module: ME  */
 4794     /*                                                              */
 4795     /****************************************************************/
 4796     typedef union {                      /* ME_GS - Global Status Register */
 4797       vuint32_t R;
 4798       struct {
 4799   
 4800   #ifndef USE_FIELD_ALIASES_ME
 4801   
 4802         vuint32_t S_CURRENT_MODE:4;      /* Current device mode status */
 4803   
 4804   #else
 4805   
 4806         vuint32_t S_CURRENTMODE:4;       /* deprecated name - please avoid */
 4807   
 4808   #endif
 4809   
 4810         vuint32_t S_MTRANS:1;            /* Mode transition status */
 4811        vuint32_t:
 4812         3;
 4813         vuint32_t S_PDO:1;               /* Output power-down status */
 4814        vuint32_t:
 4815         2;
 4816         vuint32_t S_MVR:1;               /* Main voltage regulator status */
 4817        vuint32_t:
 4818         2;
 4819   
 4820   #ifndef USE_FIELD_ALIASES_ME
 4821   
 4822         vuint32_t S_FLA:2;               /* Flash availability status */
 4823   
 4824   #else
 4825   
 4826         vuint32_t S_CFLA:2;              /* deprecated name - please avoid */
 4827   
 4828   #endif
 4829   
 4830        vuint32_t:
 4831         8;
 4832         vuint32_t S_PLL1:1;              /* Secondary PLL status */
 4833         vuint32_t S_PLL0:1;              /* System PLL status */
 4834   
 4835   #ifndef USE_FIELD_ALIASES_ME
 4836   
 4837         vuint32_t S_XOSC:1;              /* System crystal oscillator status */
 4838   
 4839   #else
 4840   
 4841         vuint32_t S_OSC:1;               /* deprecated name - please avoid */
 4842   
 4843   #endif
 4844   
 4845   #ifndef USE_FIELD_ALIASES_ME
 4846   
 4847         vuint32_t S_IRCOSC:1;            /* System RC oscillator status */
 4848   
 4849   #else
 4850   
 4851         vuint32_t S_RC:1;                /* deprecated name - please avoid */
 4852   
 4853   #endif
 4854   
 4855         vuint32_t S_SYSCLK:4;            /* System clock switch status */
 4856       } B;
 4857     } ME_GS_32B_tag;
 4858   
 4859     typedef union {                      /* ME_MCTL - Mode Control Register */
 4860       vuint32_t R;
 4861       struct {
 4862         vuint32_t TARGET_MODE:4;         /* Target device mode */
 4863        vuint32_t:
 4864         12;
 4865         vuint32_t KEY:16;                /* Control key */
 4866       } B;
 4867     } ME_MCTL_32B_tag;
 4868   
 4869     typedef union {                      /* ME_MEN - Mode Enable Register */
 4870       vuint32_t R;
 4871       struct {
 4872        vuint32_t:
 4873         16;
 4874         vuint32_t RESET_DEST:1;          /* Destructive RESET mode enable */
 4875        vuint32_t:
 4876         4;
 4877         vuint32_t STOP0:1;               /* STOP0 mode enable */
 4878        vuint32_t:
 4879         1;
 4880         vuint32_t HALT0:1;               /* HALT0 mode enable */
 4881         vuint32_t RUN3:1;                /* RUN3 mode enable */
 4882         vuint32_t RUN2:1;                /* RUN2 mode enable */
 4883         vuint32_t RUN1:1;                /* RUN1 mode enable */
 4884         vuint32_t RUN0:1;                /* RUN0 mode enable */
 4885         vuint32_t DRUN:1;                /* DRUN mode enable */
 4886         vuint32_t SAFE:1;                /* SAFE mode enable */
 4887         vuint32_t TEST:1;                /* TEST mode enable */
 4888         vuint32_t RESET_FUNC:1;          /* Functional RESET mode enable */
 4889       } B;
 4890     } ME_MEN_32B_tag;
 4891   
 4892     typedef union {                      /* ME_IS - Interrupt Status Register */
 4893       vuint32_t R;
 4894       struct {
 4895        vuint32_t:
 4896         27;
 4897         vuint32_t I_ICONF_CU:1;          /* Invalid clock usage interrupt */
 4898   
 4899   #ifndef USE_FIELD_ALIASES_ME
 4900   
 4901         vuint32_t I_ICONF:1;             /* Invalid mode config interrupt */
 4902   
 4903   #else
 4904   
 4905         vuint32_t I_CONF:1;              /* deprecated name - please avoid */
 4906   
 4907   #endif
 4908   
 4909   #ifndef USE_FIELD_ALIASES_ME
 4910   
 4911         vuint32_t I_IMODE:1;             /* Invalid mode interrupt */
 4912   
 4913   #else
 4914   
 4915         vuint32_t I_MODE:1;              /* deprecated name - please avoid */
 4916   
 4917   #endif
 4918   
 4919         vuint32_t I_SAFE:1;              /* SAFE mode interrupt */
 4920   
 4921   #ifndef USE_FIELD_ALIASES_ME
 4922   
 4923         vuint32_t I_MTC:1;               /* Mode transition complete interrupt */
 4924   
 4925   #else
 4926   
 4927         vuint32_t I_TC:1;                /* deprecated name - please avoid */
 4928   
 4929   #endif
 4930   
 4931       } B;
 4932     } ME_IS_32B_tag;
 4933   
 4934     typedef union {                      /* ME_IM - Interrupt Mask Register */
 4935       vuint32_t R;
 4936       struct {
 4937        vuint32_t:
 4938         27;
 4939         vuint32_t M_ICONF_CU:1;          /* Invalid clock usage interrupt mask */
 4940   
 4941   #ifndef USE_FIELD_ALIASES_ME
 4942   
 4943         vuint32_t M_ICONF:1;             /* Invalid mode config interrupt mask */
 4944   
 4945   #else
 4946   
 4947         vuint32_t M_CONF:1;              /* deprecated name - please avoid */
 4948   
 4949   #endif
 4950   
 4951   #ifndef USE_FIELD_ALIASES_ME
 4952   
 4953         vuint32_t M_IMODE:1;             /* Invalid mode interrupt mask */
 4954   
 4955   #else
 4956   
 4957         vuint32_t M_MODE:1;              /* deprecated name - please avoid */
 4958   
 4959   #endif
 4960   
 4961         vuint32_t M_SAFE:1;              /* SAFE mode interrupt mask */
 4962   
 4963   #ifndef USE_FIELD_ALIASES_ME
 4964   
 4965         vuint32_t M_MTC:1;               /* Mode transition complete interrupt mask */
 4966   
 4967   #else
 4968   
 4969         vuint32_t M_TC:1;                /* deprecated name - please avoid */
 4970   
 4971   #endif
 4972   
 4973       } B;
 4974     } ME_IM_32B_tag;
 4975   
 4976     typedef union {                      /* ME_IMTS - Invalid Mode Transition Status Register */
 4977       vuint32_t R;
 4978       struct {
 4979        vuint32_t:
 4980         27;
 4981         vuint32_t S_MTI:1;               /* Mode Transition Illegal status */
 4982         vuint32_t S_MRI:1;               /* Mode Request Illegal status */
 4983         vuint32_t S_DMA:1;               /* Disabled Mode Access status */
 4984         vuint32_t S_NMA:1;               /* Non-existing Mode Access status */
 4985         vuint32_t S_SEA:1;               /* Safe Event Active status */
 4986       } B;
 4987     } ME_IMTS_32B_tag;
 4988   
 4989     typedef union {                      /* ME_DMTS - Debug Mode Transition Status Register */
 4990       vuint32_t R;
 4991       struct {
 4992         vuint32_t PREVIOUS_MODE:4;       /* Previous Device Mode */
 4993        vuint32_t:
 4994         4;
 4995         vuint32_t MPH_BUSY:1;            /* MC_ME/MC_PCU Handshake Busy Indicator */
 4996        vuint32_t:
 4997         2;
 4998         vuint32_t PMC_PROG:1;            /* MC_PCU Mode Change in Process Indicator */
 4999         vuint32_t CORE_DBG:1;            /* Processor is in Debug Mode Indicator */
 5000        vuint32_t:
 5001         2;
 5002         vuint32_t SMR:1;                 /* SAFE Mode Request */
 5003        vuint32_t:
 5004         1;
 5005         vuint32_t VREG_CSRC_SC:1;        /* Main VREG Clock Source State Change Indicator */
 5006         vuint32_t CSRC_CSRC_SC:1;        /* Other Clock Source State Change Indicator */
 5007         vuint32_t IRCOSC_SC:1;           /* IRCOSC State Change Indicator */
 5008         vuint32_t SCSRC_SC:1;            /* Secondary System Clock Sources State Change Indicator */
 5009         vuint32_t SYSCLK_SW:1;           /* System Clock Switching pending Status Indicator */
 5010        vuint32_t:
 5011         1;
 5012         vuint32_t FLASH_SC:1;            /* FLASH State Change Indicator */
 5013         vuint32_t CDP_PRPH_0_143:1;      /* Clock Disable Process Pending Status for Periph. 0-143 */
 5014        vuint32_t:
 5015         4;
 5016         vuint32_t CDP_PRPH_64_95:1;      /* Clock Disable Process Pending Status for Periph. 64-95 */
 5017         vuint32_t CDP_PRPH_32_63:1;      /* Clock Disable Process Pending Status for Periph. 32-63 */
 5018         vuint32_t CDP_PRPH_0_31:1;       /* Clock Disable Process Pending Status for Periph. 0-31 */
 5019       } B;
 5020     } ME_DMTS_32B_tag;
 5021   
 5022     typedef union {                      /* ME_RESET_MC - RESET Mode Configuration Register */
 5023       vuint32_t R;
 5024       struct {
 5025        vuint32_t:
 5026         8;
 5027         vuint32_t PDO:1;                 /* IOs output power-down control */
 5028        vuint32_t:
 5029         2;
 5030         vuint32_t MVRON:1;               /* Main voltage regulator control */
 5031        vuint32_t:
 5032         2;
 5033         vuint32_t FLAON:2;               /* Flash power-down control */
 5034        vuint32_t:
 5035         8;
 5036   
 5037   #ifndef USE_FIELD_ALIASES_ME
 5038   
 5039         vuint32_t PLL1ON:1;              /* Secondary system clock source [8..0] control */
 5040   
 5041   #else
 5042   
 5043         vuint32_t PLL2ON:1;              /* deprecated name - please avoid */
 5044   
 5045   #endif
 5046   
 5047   #ifndef USE_FIELD_ALIASES_ME
 5048   
 5049         vuint32_t PLL0ON:1;              /* System PLL control */
 5050   
 5051   #else
 5052   
 5053         vuint32_t PLL1ON:1;              /* deprecated name - please avoid */
 5054   
 5055   #endif
 5056   
 5057   #ifndef USE_FIELD_ALIASES_ME
 5058   
 5059         vuint32_t XOSCON:1;              /* System crystal oscillator control */
 5060   
 5061   #else
 5062   
 5063         vuint32_t XOSC0ON:1;             /* deprecated name - please avoid */
 5064   
 5065   #endif
 5066   
 5067   #ifndef USE_FIELD_ALIASES_ME
 5068   
 5069         vuint32_t IRCOSCON:1;            /* System RC oscillator control */
 5070   
 5071   #else
 5072   
 5073         vuint32_t IRCON:1;               /* deprecated name - please avoid */
 5074   
 5075   #endif
 5076   
 5077         vuint32_t SYSCLK:4;              /* System clock switch control */
 5078       } B;
 5079     } ME_RESET_MC_32B_tag;
 5080   
 5081     typedef union {                      /* ME_TEST_MC - TEST Mode Configuration Register */
 5082       vuint32_t R;
 5083       struct {
 5084        vuint32_t:
 5085         8;
 5086         vuint32_t PDO:1;                 /* IOs output power-down control */
 5087        vuint32_t:
 5088         2;
 5089         vuint32_t MVRON:1;               /* Main voltage regulator control */
 5090        vuint32_t:
 5091         2;
 5092         vuint32_t FLAON:2;               /* Flash power-down control */
 5093        vuint32_t:
 5094         8;
 5095   
 5096   #ifndef USE_FIELD_ALIASES_ME
 5097   
 5098         vuint32_t PLL1ON:1;              /* Secondary system clock source [8..0] control */
 5099   
 5100   #else
 5101   
 5102         vuint32_t PLL2ON:1;              /* deprecated name - please avoid */
 5103   
 5104   #endif
 5105   
 5106   #ifndef USE_FIELD_ALIASES_ME
 5107   
 5108         vuint32_t PLL0ON:1;              /* System PLL control */
 5109   
 5110   #else
 5111   
 5112         vuint32_t PLL1ON:1;              /* deprecated name - please avoid */
 5113   
 5114   #endif
 5115   
 5116   #ifndef USE_FIELD_ALIASES_ME
 5117   
 5118         vuint32_t XOSCON:1;              /* System crystal oscillator control */
 5119   
 5120   #else
 5121   
 5122         vuint32_t XOSC0ON:1;             /* deprecated name - please avoid */
 5123   
 5124   #endif
 5125   
 5126   #ifndef USE_FIELD_ALIASES_ME
 5127   
 5128         vuint32_t IRCOSCON:1;            /* System RC oscillator control */
 5129   
 5130   #else
 5131   
 5132         vuint32_t IRCON:1;               /* deprecated name - please avoid */
 5133   
 5134   #endif
 5135   
 5136         vuint32_t SYSCLK:4;              /* System clock switch control */
 5137       } B;
 5138     } ME_TEST_MC_32B_tag;
 5139   
 5140     typedef union {                      /* ME_SAFE_MC - Mode Configuration Register */
 5141       vuint32_t R;
 5142       struct {
 5143        vuint32_t:
 5144         8;
 5145         vuint32_t PDO:1;                 /* IOs output power-down control */
 5146        vuint32_t:
 5147         2;
 5148         vuint32_t MVRON:1;               /* Main voltage regulator control */
 5149        vuint32_t:
 5150         2;
 5151         vuint32_t FLAON:2;               /* Flash power-down control */
 5152        vuint32_t:
 5153         8;
 5154   
 5155   #ifndef USE_FIELD_ALIASES_ME
 5156   
 5157         vuint32_t PLL1ON:1;              /* Secondary system clock source [8..0] control */
 5158   
 5159   #else
 5160   
 5161         vuint32_t PLL2ON:1;              /* deprecated name - please avoid */
 5162   
 5163   #endif
 5164   
 5165   #ifndef USE_FIELD_ALIASES_ME
 5166   
 5167         vuint32_t PLL0ON:1;              /* System PLL control */
 5168   
 5169   #else
 5170   
 5171         vuint32_t PLL1ON:1;              /* deprecated name - please avoid */
 5172   
 5173   #endif
 5174   
 5175   #ifndef USE_FIELD_ALIASES_ME
 5176   
 5177         vuint32_t XOSCON:1;              /* System crystal oscillator control */
 5178   
 5179   #else
 5180   
 5181         vuint32_t XOSC0ON:1;             /* deprecated name - please avoid */
 5182   
 5183   #endif
 5184   
 5185   #ifndef USE_FIELD_ALIASES_ME
 5186   
 5187         vuint32_t IRCOSCON:1;            /* System RC oscillator control */
 5188   
 5189   #else
 5190   
 5191         vuint32_t IRCON:1;               /* deprecated name - please avoid */
 5192   
 5193   #endif
 5194   
 5195         vuint32_t SYSCLK:4;              /* System clock switch control */
 5196       } B;
 5197     } ME_SAFE_MC_32B_tag;
 5198   
 5199     typedef union {                      /* ME_DRUN_MC - DRUN Mode Configuration Register */
 5200       vuint32_t R;
 5201       struct {
 5202        vuint32_t:
 5203         8;
 5204         vuint32_t PDO:1;                 /* IOs output power-down control */
 5205        vuint32_t:
 5206         2;
 5207         vuint32_t MVRON:1;               /* Main voltage regulator control */
 5208        vuint32_t:
 5209         2;
 5210         vuint32_t FLAON:2;               /* Flash power-down control */
 5211        vuint32_t:
 5212         8;
 5213   
 5214   #ifndef USE_FIELD_ALIASES_ME
 5215   
 5216         vuint32_t PLL1ON:1;              /* Secondary system clock source [8..0] control */
 5217   
 5218   #else
 5219   
 5220         vuint32_t PLL2ON:1;              /* deprecated name - please avoid */
 5221   
 5222   #endif
 5223   
 5224   #ifndef USE_FIELD_ALIASES_ME
 5225   
 5226         vuint32_t PLL0ON:1;              /* System PLL control */
 5227   
 5228   #else
 5229   
 5230         vuint32_t PLL1ON:1;              /* deprecated name - please avoid */
 5231   
 5232   #endif
 5233   
 5234   #ifndef USE_FIELD_ALIASES_ME
 5235   
 5236         vuint32_t XOSCON:1;              /* System crystal oscillator control */
 5237   
 5238   #else
 5239   
 5240         vuint32_t XOSC0ON:1;             /* deprecated name - please avoid */
 5241   
 5242   #endif
 5243   
 5244   #ifndef USE_FIELD_ALIASES_ME
 5245   
 5246         vuint32_t IRCOSCON:1;            /* System RC oscillator control */
 5247   
 5248   #else
 5249   
 5250         vuint32_t IRCON:1;               /* deprecated name - please avoid */
 5251   
 5252   #endif
 5253   
 5254         vuint32_t SYSCLK:4;              /* System clock switch control */
 5255       } B;
 5256     } ME_DRUN_MC_32B_tag;
 5257   
 5258     /* Register layout for all registers RUN_MC ... */
 5259     typedef union {                      /* ME_RUN[0..3]_MC - RUN[0..3] Mode Configuration Registers */
 5260       vuint32_t R;
 5261       struct {
 5262        vuint32_t:
 5263         8;
 5264         vuint32_t PDO:1;                 /* IOs output power-down control */
 5265        vuint32_t:
 5266         2;
 5267         vuint32_t MVRON:1;               /* Main voltage regulator control */
 5268        vuint32_t:
 5269         2;
 5270         vuint32_t FLAON:2;               /* Flash power-down control */
 5271        vuint32_t:
 5272         8;
 5273   
 5274   #ifndef USE_FIELD_ALIASES_ME
 5275   
 5276         vuint32_t PLL1ON:1;              /* Secondary system clock source [8..0] control */
 5277   
 5278   #else
 5279   
 5280         vuint32_t PLL2ON:1;              /* deprecated name - please avoid */
 5281   
 5282   #endif
 5283   
 5284   #ifndef USE_FIELD_ALIASES_ME
 5285   
 5286         vuint32_t PLL0ON:1;              /* System PLL control */
 5287   
 5288   #else
 5289   
 5290         vuint32_t PLL1ON:1;              /* deprecated name - please avoid */
 5291   
 5292   #endif
 5293   
 5294   #ifndef USE_FIELD_ALIASES_ME
 5295   
 5296         vuint32_t XOSCON:1;              /* System crystal oscillator control */
 5297   
 5298   #else
 5299   
 5300         vuint32_t XOSC0ON:1;             /* deprecated name - please avoid */
 5301   
 5302   #endif
 5303   
 5304   #ifndef USE_FIELD_ALIASES_ME
 5305   
 5306         vuint32_t IRCOSCON:1;            /* System RC oscillator control */
 5307   
 5308   #else
 5309   
 5310         vuint32_t IRCON:1;               /* deprecated name - please avoid */
 5311   
 5312   #endif
 5313   
 5314         vuint32_t SYSCLK:4;              /* System clock switch control */
 5315       } B;
 5316     } ME_RUN_MC_32B_tag;
 5317   
 5318     typedef union {                      /* ME_HALT0_MC - HALT0 Mode Configuration Register */
 5319       vuint32_t R;
 5320       struct {
 5321        vuint32_t:
 5322         8;
 5323         vuint32_t PDO:1;                 /* IOs output power-down control */
 5324        vuint32_t:
 5325         2;
 5326         vuint32_t MVRON:1;               /* Main voltage regulator control */
 5327        vuint32_t:
 5328         2;
 5329         vuint32_t FLAON:2;               /* Flash power-down control */
 5330        vuint32_t:
 5331         8;
 5332   
 5333   #ifndef USE_FIELD_ALIASES_ME
 5334   
 5335         vuint32_t PLL1ON:1;              /* Secondary system clock source [8..0] control */
 5336   
 5337   #else
 5338   
 5339         vuint32_t PLL2ON:1;              /* deprecated name - please avoid */
 5340   
 5341   #endif
 5342   
 5343   #ifndef USE_FIELD_ALIASES_ME
 5344   
 5345         vuint32_t PLL0ON:1;              /* System PLL control */
 5346   
 5347   #else
 5348   
 5349         vuint32_t PLL1ON:1;              /* deprecated name - please avoid */
 5350   
 5351   #endif
 5352   
 5353   #ifndef USE_FIELD_ALIASES_ME
 5354   
 5355         vuint32_t XOSCON:1;              /* System crystal oscillator control */
 5356   
 5357   #else
 5358   
 5359         vuint32_t XOSC0ON:1;             /* deprecated name - please avoid */
 5360   
 5361   #endif
 5362   
 5363   #ifndef USE_FIELD_ALIASES_ME
 5364   
 5365         vuint32_t IRCOSCON:1;            /* System RC oscillator control */
 5366   
 5367   #else
 5368   
 5369         vuint32_t IRCON:1;               /* deprecated name - please avoid */
 5370   
 5371   #endif
 5372   
 5373         vuint32_t SYSCLK:4;              /* System clock switch control */
 5374       } B;
 5375     } ME_HALT0_MC_32B_tag;
 5376   
 5377     typedef union {                      /* ME_STOP0_MC - STOP0 Mode Configration Register */
 5378       vuint32_t R;
 5379       struct {
 5380        vuint32_t:
 5381         8;
 5382         vuint32_t PDO:1;                 /* IOs output power-down control */
 5383        vuint32_t:
 5384         2;
 5385         vuint32_t MVRON:1;               /* Main voltage regulator control */
 5386        vuint32_t:
 5387         2;
 5388         vuint32_t FLAON:2;               /* Flash power-down control */
 5389        vuint32_t:
 5390         8;
 5391   
 5392   #ifndef USE_FIELD_ALIASES_ME
 5393   
 5394         vuint32_t PLL1ON:1;              /* Secondary system clock source [8..0] control */
 5395   
 5396   #else
 5397   
 5398         vuint32_t PLL2ON:1;              /* deprecated name - please avoid */
 5399   
 5400   #endif
 5401   
 5402   #ifndef USE_FIELD_ALIASES_ME
 5403   
 5404         vuint32_t PLL0ON:1;              /* System PLL control */
 5405   
 5406   #else
 5407   
 5408         vuint32_t PLL1ON:1;              /* deprecated name - please avoid */
 5409   
 5410   #endif
 5411   
 5412   #ifndef USE_FIELD_ALIASES_ME
 5413   
 5414         vuint32_t XOSCON:1;              /* System crystal oscillator control */
 5415   
 5416   #else
 5417   
 5418         vuint32_t XOSC0ON:1;             /* deprecated name - please avoid */
 5419   
 5420   #endif
 5421   
 5422   #ifndef USE_FIELD_ALIASES_ME
 5423   
 5424         vuint32_t IRCOSCON:1;            /* System RC oscillator control */
 5425   
 5426   #else
 5427   
 5428         vuint32_t IRCON:1;               /* deprecated name - please avoid */
 5429   
 5430   #endif
 5431   
 5432         vuint32_t SYSCLK:4;              /* System clock switch control */
 5433       } B;
 5434     } ME_STOP0_MC_32B_tag;
 5435   
 5436     typedef union {                      /* ME_PS0 - Peripheral Status Register 0 */
 5437       vuint32_t R;
 5438       struct {
 5439        vuint32_t:
 5440         7;
 5441         vuint32_t S_FLEXRAY:1;           /* FlexRay status */
 5442        vuint32_t:
 5443         6;
 5444         vuint32_t S_FLEXCAN1:1;          /* FlexCAN1 status */
 5445         vuint32_t S_FLEXCAN0:1;          /* FlexCAN0 status */
 5446        vuint32_t:
 5447         9;
 5448         vuint32_t S_DSPI2:1;             /* DSPI2 status */
 5449         vuint32_t S_DSPI1:1;             /* DSPI1 status */
 5450         vuint32_t S_DSPI0:1;             /* DSPI0 status */
 5451        vuint32_t:
 5452         4;
 5453       } B;
 5454     } ME_PS0_32B_tag;
 5455   
 5456     typedef union {                      /* ME_PS1 - Peripheral Status Register 1 */
 5457       vuint32_t R;
 5458       struct {
 5459        vuint32_t:
 5460         1;
 5461         vuint32_t S_SWG:1;               /* SWG status */
 5462        vuint32_t:
 5463         3;
 5464         vuint32_t S_CRC:1;               /* CRC status */
 5465        vuint32_t:
 5466         8;
 5467         vuint32_t S_LIN_FLEX1:1;         /* LinFlex1 status */
 5468         vuint32_t S_LIN_FLEX0:1;         /* LinFlex0 status */
 5469        vuint32_t:
 5470         5;
 5471         vuint32_t S_FLEXPWM1:1;          /* FlexPWM1 status */
 5472         vuint32_t S_FLEXPWM0:1;          /* FlexPWM0 status */
 5473         vuint32_t S_ETIMER2:1;           /* eTimer2 status */
 5474         vuint32_t S_ETIMER1:1;           /* eTimer1 status */
 5475         vuint32_t S_ETIMER0:1;           /* eTimer0 status */
 5476        vuint32_t:
 5477         2;
 5478         vuint32_t S_CTU:1;               /* CTU status */
 5479        vuint32_t:
 5480         1;
 5481         vuint32_t S_ADC1:1;              /* ADC1 status */
 5482         vuint32_t S_ADC0:1;              /* ADC0 status */
 5483       } B;
 5484     } ME_PS1_32B_tag;
 5485   
 5486     typedef union {                      /* ME_PS2 - Peripheral Status Register 2 */
 5487       vuint32_t R;
 5488       struct {
 5489        vuint32_t:
 5490         3;
 5491         vuint32_t S_PIT:1;               /* PIT status */
 5492        vuint32_t:
 5493         28;
 5494       } B;
 5495     } ME_PS2_32B_tag;
 5496   
 5497     /* Register layout for all registers RUN_PC ... */
 5498     typedef union {                      /* ME_RUN_PC[0...7] - RUN Peripheral Configuration Registers */
 5499       vuint32_t R;
 5500       struct {
 5501        vuint32_t:
 5502         24;
 5503         vuint32_t RUN3:1;                /* Peripheral control during RUN3 */
 5504         vuint32_t RUN2:1;                /* Peripheral control during RUN2 */
 5505         vuint32_t RUN1:1;                /* Peripheral control during RUN1 */
 5506         vuint32_t RUN0:1;                /* Peripheral control during RUN0 */
 5507         vuint32_t DRUN:1;                /* Peripheral control during DRUN */
 5508         vuint32_t SAFE:1;                /* Peripheral control during SAFE */
 5509         vuint32_t TEST:1;                /* Peripheral control during TEST */
 5510         vuint32_t RESET:1;               /* Peripheral control during RESET */
 5511       } B;
 5512     } ME_RUN_PC_32B_tag;
 5513   
 5514     /* Register layout for all registers LP_PC ... */
 5515     typedef union {                      /* ME_LP_PC[0...7] - Low Power Peripheral Configuration Registers */
 5516       vuint32_t R;
 5517       struct {
 5518        vuint32_t:
 5519         21;
 5520         vuint32_t STOP0:1;               /* Peripheral control during STOP0 */
 5521        vuint32_t:
 5522         1;
 5523         vuint32_t HALT0:1;               /* Peripheral control during HALT0 */
 5524        vuint32_t:
 5525         8;
 5526       } B;
 5527     } ME_LP_PC_32B_tag;
 5528   
 5529     /* Register layout for all registers PCTL ... */
 5530     typedef union {                      /* ME_PCTL[0...143] - Peripheral Control Registers */
 5531       vuint8_t R;
 5532       struct {
 5533        vuint8_t:
 5534         1;
 5535         vuint8_t DBG_F:1;                /* Peripheral control in debug mode */
 5536         vuint8_t LP_CFG:3;               /* Peripheral configuration select for non-RUN modes */
 5537         vuint8_t RUN_CFG:3;              /* Peripheral configuration select for RUN modes */
 5538       } B;
 5539     } ME_PCTL_8B_tag;
 5540   
 5541     /* Register layout for generated register(s) PS... */
 5542     typedef union {                      /*  */
 5543       vuint32_t R;
 5544     } ME_PS_32B_tag;
 5545   
 5546     typedef struct ME_struct_tag {
 5547       /* ME_GS - Global Status Register */
 5548       ME_GS_32B_tag GS;                  /* offset: 0x0000 size: 32 bit */
 5549   
 5550       /* ME_MCTL - Mode Control Register */
 5551       ME_MCTL_32B_tag MCTL;              /* offset: 0x0004 size: 32 bit */
 5552       union {
 5553         /* ME_MEN - Mode Enable Register */
 5554         ME_MEN_32B_tag MEN;              /* offset: 0x0008 size: 32 bit */
 5555         ME_MEN_32B_tag MER;              /* deprecated - please avoid */
 5556       };
 5557   
 5558       /* ME_IS - Interrupt Status Register */
 5559       ME_IS_32B_tag IS;                  /* offset: 0x000C size: 32 bit */
 5560   
 5561       /* ME_IM - Interrupt Mask Register */
 5562       ME_IM_32B_tag IM;                  /* offset: 0x0010 size: 32 bit */
 5563   
 5564       /* ME_IMTS - Invalid Mode Transition Status Register */
 5565       ME_IMTS_32B_tag IMTS;              /* offset: 0x0014 size: 32 bit */
 5566   
 5567       /* ME_DMTS - Debug Mode Transition Status Register */
 5568       ME_DMTS_32B_tag DMTS;              /* offset: 0x0018 size: 32 bit */
 5569       int8_t ME_reserved_001C[4];
 5570       union {
 5571         /* ME_RESET_MC - RESET Mode Configuration Register */
 5572         ME_RESET_MC_32B_tag RESET_MC;    /* offset: 0x0020 size: 32 bit */
 5573         ME_RESET_MC_32B_tag RESET;       /* deprecated - please avoid */
 5574       };
 5575   
 5576       union {
 5577         /* ME_TEST_MC - TEST Mode Configuration Register */
 5578         ME_TEST_MC_32B_tag TEST_MC;      /* offset: 0x0024 size: 32 bit */
 5579         ME_TEST_MC_32B_tag TEST;         /* deprecated - please avoid */
 5580       };
 5581   
 5582       union {
 5583         /* ME_SAFE_MC - Mode Configuration Register */
 5584         ME_SAFE_MC_32B_tag SAFE_MC;      /* offset: 0x0028 size: 32 bit */
 5585         ME_SAFE_MC_32B_tag SAFE;         /* deprecated - please avoid */
 5586       };
 5587   
 5588       union {
 5589         /* ME_DRUN_MC - DRUN Mode Configuration Register */
 5590         ME_DRUN_MC_32B_tag DRUN_MC;      /* offset: 0x002C size: 32 bit */
 5591         ME_DRUN_MC_32B_tag DRUN;         /* deprecated - please avoid */
 5592       };
 5593   
 5594       union {
 5595         /* ME_RUN[0..3]_MC - RUN[0..3] Mode Configuration Registers */
 5596         ME_RUN_MC_32B_tag RUN_MC[4];     /* offset: 0x0030  (0x0004 x 4) */
 5597         ME_RUN_MC_32B_tag RUN[4];        /* offset: 0x0030  (0x0004 x 4) */
 5598         struct {
 5599           /* ME_RUN[0..3]_MC - RUN[0..3] Mode Configuration Registers */
 5600           ME_RUN_MC_32B_tag RUN0_MC;     /* offset: 0x0030 size: 32 bit */
 5601           ME_RUN_MC_32B_tag RUN1_MC;     /* offset: 0x0034 size: 32 bit */
 5602           ME_RUN_MC_32B_tag RUN2_MC;     /* offset: 0x0038 size: 32 bit */
 5603           ME_RUN_MC_32B_tag RUN3_MC;     /* offset: 0x003C size: 32 bit */
 5604         };
 5605       };
 5606   
 5607       union {
 5608         /* ME_HALT0_MC - HALT0 Mode Configuration Register */
 5609         ME_HALT0_MC_32B_tag HALT0_MC;    /* offset: 0x0040 size: 32 bit */
 5610         ME_HALT0_MC_32B_tag HALT0;       /* deprecated - please avoid */
 5611       };
 5612   
 5613       int8_t ME_reserved_0044[4];
 5614       union {
 5615         /* ME_STOP0_MC - STOP0 Mode Configration Register */
 5616         ME_STOP0_MC_32B_tag STOP0_MC;    /* offset: 0x0048 size: 32 bit */
 5617         ME_STOP0_MC_32B_tag STOP0;       /* deprecated - please avoid */
 5618       };
 5619   
 5620       int8_t ME_reserved_004C[20];
 5621       union {
 5622         ME_PS_32B_tag PS[3];             /* offset: 0x0060  (0x0004 x 3) */
 5623         struct {
 5624           /* ME_PS0 - Peripheral Status Register 0 */
 5625           ME_PS0_32B_tag PS0;            /* offset: 0x0060 size: 32 bit */
 5626   
 5627           /* ME_PS1 - Peripheral Status Register 1 */
 5628           ME_PS1_32B_tag PS1;            /* offset: 0x0064 size: 32 bit */
 5629   
 5630           /* ME_PS2 - Peripheral Status Register 2 */
 5631           ME_PS2_32B_tag PS2;            /* offset: 0x0068 size: 32 bit */
 5632         };
 5633       };
 5634   
 5635       int8_t ME_reserved_006C[20];
 5636       union {
 5637         ME_RUN_PC_32B_tag RUNPC[8];      /* offset: 0x0080  (0x0004 x 8) */
 5638   
 5639         /* ME_RUN_PC[0...7] - RUN Peripheral Configuration Registers */
 5640         ME_RUN_PC_32B_tag RUN_PC[8];     /* offset: 0x0080  (0x0004 x 8) */
 5641         struct {
 5642           /* ME_RUN_PC[0...7] - RUN Peripheral Configuration Registers */
 5643           ME_RUN_PC_32B_tag RUN_PC0;     /* offset: 0x0080 size: 32 bit */
 5644           ME_RUN_PC_32B_tag RUN_PC1;     /* offset: 0x0084 size: 32 bit */
 5645           ME_RUN_PC_32B_tag RUN_PC2;     /* offset: 0x0088 size: 32 bit */
 5646           ME_RUN_PC_32B_tag RUN_PC3;     /* offset: 0x008C size: 32 bit */
 5647           ME_RUN_PC_32B_tag RUN_PC4;     /* offset: 0x0090 size: 32 bit */
 5648           ME_RUN_PC_32B_tag RUN_PC5;     /* offset: 0x0094 size: 32 bit */
 5649           ME_RUN_PC_32B_tag RUN_PC6;     /* offset: 0x0098 size: 32 bit */
 5650           ME_RUN_PC_32B_tag RUN_PC7;     /* offset: 0x009C size: 32 bit */
 5651         };
 5652       };
 5653   
 5654       union {
 5655         ME_LP_PC_32B_tag LPPC[8];        /* offset: 0x00A0  (0x0004 x 8) */
 5656   
 5657         /* ME_LP_PC[0...7] - Low Power Peripheral Configuration Registers */
 5658         ME_LP_PC_32B_tag LP_PC[8];       /* offset: 0x00A0  (0x0004 x 8) */
 5659         struct {
 5660           /* ME_LP_PC[0...7] - Low Power Peripheral Configuration Registers */
 5661           ME_LP_PC_32B_tag LP_PC0;       /* offset: 0x00A0 size: 32 bit */
 5662           ME_LP_PC_32B_tag LP_PC1;       /* offset: 0x00A4 size: 32 bit */
 5663           ME_LP_PC_32B_tag LP_PC2;       /* offset: 0x00A8 size: 32 bit */
 5664           ME_LP_PC_32B_tag LP_PC3;       /* offset: 0x00AC size: 32 bit */
 5665           ME_LP_PC_32B_tag LP_PC4;       /* offset: 0x00B0 size: 32 bit */
 5666           ME_LP_PC_32B_tag LP_PC5;       /* offset: 0x00B4 size: 32 bit */
 5667           ME_LP_PC_32B_tag LP_PC6;       /* offset: 0x00B8 size: 32 bit */
 5668           ME_LP_PC_32B_tag LP_PC7;       /* offset: 0x00BC size: 32 bit */
 5669         };
 5670       };
 5671   
 5672       union {
 5673         /* ME_PCTL[0...143] - Peripheral Control Registers */
 5674         ME_PCTL_8B_tag PCTL[144];        /* offset: 0x00C0  (0x0001 x 144) */
 5675         struct {
 5676           /* ME_PCTL[0...143] - Peripheral Control Registers */
 5677           ME_PCTL_8B_tag PCTL0;          /* offset: 0x00C0 size: 8 bit */
 5678           ME_PCTL_8B_tag PCTL1;          /* offset: 0x00C1 size: 8 bit */
 5679           ME_PCTL_8B_tag PCTL2;          /* offset: 0x00C2 size: 8 bit */
 5680           ME_PCTL_8B_tag PCTL3;          /* offset: 0x00C3 size: 8 bit */
 5681           ME_PCTL_8B_tag PCTL4;          /* offset: 0x00C4 size: 8 bit */
 5682           ME_PCTL_8B_tag PCTL5;          /* offset: 0x00C5 size: 8 bit */
 5683           ME_PCTL_8B_tag PCTL6;          /* offset: 0x00C6 size: 8 bit */
 5684           ME_PCTL_8B_tag PCTL7;          /* offset: 0x00C7 size: 8 bit */
 5685           ME_PCTL_8B_tag PCTL8;          /* offset: 0x00C8 size: 8 bit */
 5686           ME_PCTL_8B_tag PCTL9;          /* offset: 0x00C9 size: 8 bit */
 5687           ME_PCTL_8B_tag PCTL10;         /* offset: 0x00CA size: 8 bit */
 5688           ME_PCTL_8B_tag PCTL11;         /* offset: 0x00CB size: 8 bit */
 5689           ME_PCTL_8B_tag PCTL12;         /* offset: 0x00CC size: 8 bit */
 5690           ME_PCTL_8B_tag PCTL13;         /* offset: 0x00CD size: 8 bit */
 5691           ME_PCTL_8B_tag PCTL14;         /* offset: 0x00CE size: 8 bit */
 5692           ME_PCTL_8B_tag PCTL15;         /* offset: 0x00CF size: 8 bit */
 5693           ME_PCTL_8B_tag PCTL16;         /* offset: 0x00D0 size: 8 bit */
 5694           ME_PCTL_8B_tag PCTL17;         /* offset: 0x00D1 size: 8 bit */
 5695           ME_PCTL_8B_tag PCTL18;         /* offset: 0x00D2 size: 8 bit */
 5696           ME_PCTL_8B_tag PCTL19;         /* offset: 0x00D3 size: 8 bit */
 5697           ME_PCTL_8B_tag PCTL20;         /* offset: 0x00D4 size: 8 bit */
 5698           ME_PCTL_8B_tag PCTL21;         /* offset: 0x00D5 size: 8 bit */
 5699           ME_PCTL_8B_tag PCTL22;         /* offset: 0x00D6 size: 8 bit */
 5700           ME_PCTL_8B_tag PCTL23;         /* offset: 0x00D7 size: 8 bit */
 5701           ME_PCTL_8B_tag PCTL24;         /* offset: 0x00D8 size: 8 bit */
 5702           ME_PCTL_8B_tag PCTL25;         /* offset: 0x00D9 size: 8 bit */
 5703           ME_PCTL_8B_tag PCTL26;         /* offset: 0x00DA size: 8 bit */
 5704           ME_PCTL_8B_tag PCTL27;         /* offset: 0x00DB size: 8 bit */
 5705           ME_PCTL_8B_tag PCTL28;         /* offset: 0x00DC size: 8 bit */
 5706           ME_PCTL_8B_tag PCTL29;         /* offset: 0x00DD size: 8 bit */
 5707           ME_PCTL_8B_tag PCTL30;         /* offset: 0x00DE size: 8 bit */
 5708           ME_PCTL_8B_tag PCTL31;         /* offset: 0x00DF size: 8 bit */
 5709           ME_PCTL_8B_tag PCTL32;         /* offset: 0x00E0 size: 8 bit */
 5710           ME_PCTL_8B_tag PCTL33;         /* offset: 0x00E1 size: 8 bit */
 5711           ME_PCTL_8B_tag PCTL34;         /* offset: 0x00E2 size: 8 bit */
 5712           ME_PCTL_8B_tag PCTL35;         /* offset: 0x00E3 size: 8 bit */
 5713           ME_PCTL_8B_tag PCTL36;         /* offset: 0x00E4 size: 8 bit */
 5714           ME_PCTL_8B_tag PCTL37;         /* offset: 0x00E5 size: 8 bit */
 5715           ME_PCTL_8B_tag PCTL38;         /* offset: 0x00E6 size: 8 bit */
 5716           ME_PCTL_8B_tag PCTL39;         /* offset: 0x00E7 size: 8 bit */
 5717           ME_PCTL_8B_tag PCTL40;         /* offset: 0x00E8 size: 8 bit */
 5718           ME_PCTL_8B_tag PCTL41;         /* offset: 0x00E9 size: 8 bit */
 5719           ME_PCTL_8B_tag PCTL42;         /* offset: 0x00EA size: 8 bit */
 5720           ME_PCTL_8B_tag PCTL43;         /* offset: 0x00EB size: 8 bit */
 5721           ME_PCTL_8B_tag PCTL44;         /* offset: 0x00EC size: 8 bit */
 5722           ME_PCTL_8B_tag PCTL45;         /* offset: 0x00ED size: 8 bit */
 5723           ME_PCTL_8B_tag PCTL46;         /* offset: 0x00EE size: 8 bit */
 5724           ME_PCTL_8B_tag PCTL47;         /* offset: 0x00EF size: 8 bit */
 5725           ME_PCTL_8B_tag PCTL48;         /* offset: 0x00F0 size: 8 bit */
 5726           ME_PCTL_8B_tag PCTL49;         /* offset: 0x00F1 size: 8 bit */
 5727           ME_PCTL_8B_tag PCTL50;         /* offset: 0x00F2 size: 8 bit */
 5728           ME_PCTL_8B_tag PCTL51;         /* offset: 0x00F3 size: 8 bit */
 5729           ME_PCTL_8B_tag PCTL52;         /* offset: 0x00F4 size: 8 bit */
 5730           ME_PCTL_8B_tag PCTL53;         /* offset: 0x00F5 size: 8 bit */
 5731           ME_PCTL_8B_tag PCTL54;         /* offset: 0x00F6 size: 8 bit */
 5732           ME_PCTL_8B_tag PCTL55;         /* offset: 0x00F7 size: 8 bit */
 5733           ME_PCTL_8B_tag PCTL56;         /* offset: 0x00F8 size: 8 bit */
 5734           ME_PCTL_8B_tag PCTL57;         /* offset: 0x00F9 size: 8 bit */
 5735           ME_PCTL_8B_tag PCTL58;         /* offset: 0x00FA size: 8 bit */
 5736           ME_PCTL_8B_tag PCTL59;         /* offset: 0x00FB size: 8 bit */
 5737           ME_PCTL_8B_tag PCTL60;         /* offset: 0x00FC size: 8 bit */
 5738           ME_PCTL_8B_tag PCTL61;         /* offset: 0x00FD size: 8 bit */
 5739           ME_PCTL_8B_tag PCTL62;         /* offset: 0x00FE size: 8 bit */
 5740           ME_PCTL_8B_tag PCTL63;         /* offset: 0x00FF size: 8 bit */
 5741           ME_PCTL_8B_tag PCTL64;         /* offset: 0x0100 size: 8 bit */
 5742           ME_PCTL_8B_tag PCTL65;         /* offset: 0x0101 size: 8 bit */
 5743           ME_PCTL_8B_tag PCTL66;         /* offset: 0x0102 size: 8 bit */
 5744           ME_PCTL_8B_tag PCTL67;         /* offset: 0x0103 size: 8 bit */
 5745           ME_PCTL_8B_tag PCTL68;         /* offset: 0x0104 size: 8 bit */
 5746           ME_PCTL_8B_tag PCTL69;         /* offset: 0x0105 size: 8 bit */
 5747           ME_PCTL_8B_tag PCTL70;         /* offset: 0x0106 size: 8 bit */
 5748           ME_PCTL_8B_tag PCTL71;         /* offset: 0x0107 size: 8 bit */
 5749           ME_PCTL_8B_tag PCTL72;         /* offset: 0x0108 size: 8 bit */
 5750           ME_PCTL_8B_tag PCTL73;         /* offset: 0x0109 size: 8 bit */
 5751           ME_PCTL_8B_tag PCTL74;         /* offset: 0x010A size: 8 bit */
 5752           ME_PCTL_8B_tag PCTL75;         /* offset: 0x010B size: 8 bit */
 5753           ME_PCTL_8B_tag PCTL76;         /* offset: 0x010C size: 8 bit */
 5754           ME_PCTL_8B_tag PCTL77;         /* offset: 0x010D size: 8 bit */
 5755           ME_PCTL_8B_tag PCTL78;         /* offset: 0x010E size: 8 bit */
 5756           ME_PCTL_8B_tag PCTL79;         /* offset: 0x010F size: 8 bit */
 5757           ME_PCTL_8B_tag PCTL80;         /* offset: 0x0110 size: 8 bit */
 5758           ME_PCTL_8B_tag PCTL81;         /* offset: 0x0111 size: 8 bit */
 5759           ME_PCTL_8B_tag PCTL82;         /* offset: 0x0112 size: 8 bit */
 5760           ME_PCTL_8B_tag PCTL83;         /* offset: 0x0113 size: 8 bit */
 5761           ME_PCTL_8B_tag PCTL84;         /* offset: 0x0114 size: 8 bit */
 5762           ME_PCTL_8B_tag PCTL85;         /* offset: 0x0115 size: 8 bit */
 5763           ME_PCTL_8B_tag PCTL86;         /* offset: 0x0116 size: 8 bit */
 5764           ME_PCTL_8B_tag PCTL87;         /* offset: 0x0117 size: 8 bit */
 5765           ME_PCTL_8B_tag PCTL88;         /* offset: 0x0118 size: 8 bit */
 5766           ME_PCTL_8B_tag PCTL89;         /* offset: 0x0119 size: 8 bit */
 5767           ME_PCTL_8B_tag PCTL90;         /* offset: 0x011A size: 8 bit */
 5768           ME_PCTL_8B_tag PCTL91;         /* offset: 0x011B size: 8 bit */
 5769           ME_PCTL_8B_tag PCTL92;         /* offset: 0x011C size: 8 bit */
 5770           ME_PCTL_8B_tag PCTL93;         /* offset: 0x011D size: 8 bit */
 5771           ME_PCTL_8B_tag PCTL94;         /* offset: 0x011E size: 8 bit */
 5772           ME_PCTL_8B_tag PCTL95;         /* offset: 0x011F size: 8 bit */
 5773           ME_PCTL_8B_tag PCTL96;         /* offset: 0x0120 size: 8 bit */
 5774           ME_PCTL_8B_tag PCTL97;         /* offset: 0x0121 size: 8 bit */
 5775           ME_PCTL_8B_tag PCTL98;         /* offset: 0x0122 size: 8 bit */
 5776           ME_PCTL_8B_tag PCTL99;         /* offset: 0x0123 size: 8 bit */
 5777           ME_PCTL_8B_tag PCTL100;        /* offset: 0x0124 size: 8 bit */
 5778           ME_PCTL_8B_tag PCTL101;        /* offset: 0x0125 size: 8 bit */
 5779           ME_PCTL_8B_tag PCTL102;        /* offset: 0x0126 size: 8 bit */
 5780           ME_PCTL_8B_tag PCTL103;        /* offset: 0x0127 size: 8 bit */
 5781           ME_PCTL_8B_tag PCTL104;        /* offset: 0x0128 size: 8 bit */
 5782           ME_PCTL_8B_tag PCTL105;        /* offset: 0x0129 size: 8 bit */
 5783           ME_PCTL_8B_tag PCTL106;        /* offset: 0x012A size: 8 bit */
 5784           ME_PCTL_8B_tag PCTL107;        /* offset: 0x012B size: 8 bit */
 5785           ME_PCTL_8B_tag PCTL108;        /* offset: 0x012C size: 8 bit */
 5786           ME_PCTL_8B_tag PCTL109;        /* offset: 0x012D size: 8 bit */
 5787           ME_PCTL_8B_tag PCTL110;        /* offset: 0x012E size: 8 bit */
 5788           ME_PCTL_8B_tag PCTL111;        /* offset: 0x012F size: 8 bit */
 5789           ME_PCTL_8B_tag PCTL112;        /* offset: 0x0130 size: 8 bit */
 5790           ME_PCTL_8B_tag PCTL113;        /* offset: 0x0131 size: 8 bit */
 5791           ME_PCTL_8B_tag PCTL114;        /* offset: 0x0132 size: 8 bit */
 5792           ME_PCTL_8B_tag PCTL115;        /* offset: 0x0133 size: 8 bit */
 5793           ME_PCTL_8B_tag PCTL116;        /* offset: 0x0134 size: 8 bit */
 5794           ME_PCTL_8B_tag PCTL117;        /* offset: 0x0135 size: 8 bit */
 5795           ME_PCTL_8B_tag PCTL118;        /* offset: 0x0136 size: 8 bit */
 5796           ME_PCTL_8B_tag PCTL119;        /* offset: 0x0137 size: 8 bit */
 5797           ME_PCTL_8B_tag PCTL120;        /* offset: 0x0138 size: 8 bit */
 5798           ME_PCTL_8B_tag PCTL121;        /* offset: 0x0139 size: 8 bit */
 5799           ME_PCTL_8B_tag PCTL122;        /* offset: 0x013A size: 8 bit */
 5800           ME_PCTL_8B_tag PCTL123;        /* offset: 0x013B size: 8 bit */
 5801           ME_PCTL_8B_tag PCTL124;        /* offset: 0x013C size: 8 bit */
 5802           ME_PCTL_8B_tag PCTL125;        /* offset: 0x013D size: 8 bit */
 5803           ME_PCTL_8B_tag PCTL126;        /* offset: 0x013E size: 8 bit */
 5804           ME_PCTL_8B_tag PCTL127;        /* offset: 0x013F size: 8 bit */
 5805           ME_PCTL_8B_tag PCTL128;        /* offset: 0x0140 size: 8 bit */
 5806           ME_PCTL_8B_tag PCTL129;        /* offset: 0x0141 size: 8 bit */
 5807           ME_PCTL_8B_tag PCTL130;        /* offset: 0x0142 size: 8 bit */
 5808           ME_PCTL_8B_tag PCTL131;        /* offset: 0x0143 size: 8 bit */
 5809           ME_PCTL_8B_tag PCTL132;        /* offset: 0x0144 size: 8 bit */
 5810           ME_PCTL_8B_tag PCTL133;        /* offset: 0x0145 size: 8 bit */
 5811           ME_PCTL_8B_tag PCTL134;        /* offset: 0x0146 size: 8 bit */
 5812           ME_PCTL_8B_tag PCTL135;        /* offset: 0x0147 size: 8 bit */
 5813           ME_PCTL_8B_tag PCTL136;        /* offset: 0x0148 size: 8 bit */
 5814           ME_PCTL_8B_tag PCTL137;        /* offset: 0x0149 size: 8 bit */
 5815           ME_PCTL_8B_tag PCTL138;        /* offset: 0x014A size: 8 bit */
 5816           ME_PCTL_8B_tag PCTL139;        /* offset: 0x014B size: 8 bit */
 5817           ME_PCTL_8B_tag PCTL140;        /* offset: 0x014C size: 8 bit */
 5818           ME_PCTL_8B_tag PCTL141;        /* offset: 0x014D size: 8 bit */
 5819           ME_PCTL_8B_tag PCTL142;        /* offset: 0x014E size: 8 bit */
 5820           ME_PCTL_8B_tag PCTL143;        /* offset: 0x014F size: 8 bit */
 5821         };
 5822       };
 5823   
 5824       int8_t ME_reserved_0150[16048];
 5825     } ME_tag;
 5826   
 5827   #define ME                             (*(volatile ME_tag *) 0xC3FDC000UL)
 5828   
 5829     /****************************************************************/
 5830     /*                                                              */
 5831     /* Module: OSC  */
 5832     /*                                                              */
 5833     /****************************************************************/
 5834     typedef union {                      /* OSC_CTL - Control Register */
 5835       vuint32_t R;
 5836       struct {
 5837         vuint32_t OSCBYP:1;              /* High Frequency Oscillator Bypass */
 5838        vuint32_t:
 5839         7;
 5840         vuint32_t EOCV:8;                /* End of Count Value */
 5841         vuint32_t M_OSC:1;               /* High Frequency Oscillator Clock Interrupt Mask */
 5842        vuint32_t:
 5843         2;
 5844         vuint32_t OSCDIV:5;              /* High Frequency Oscillator Division Factor */
 5845         vuint32_t I_OSC:1;               /* High Frequency Oscillator Clock Interrupt */
 5846   
 5847   #if 0
 5848   
 5849         /* MJR Edited */
 5850        vuint32_t:
 5851         7;
 5852   
 5853   #else
 5854   
 5855        vuint32_t:
 5856         5;                               /* MJR BUG bits are not generated from IP-XACT */
 5857         vuint32_t S_OSC:1;
 5858         vuint32_t OSCON:1;
 5859   
 5860   #endif
 5861   
 5862       } B;
 5863     } OSC_CTL_32B_tag;
 5864   
 5865     typedef struct OSC_struct_tag {
 5866       /* OSC_CTL - Control Register */
 5867       OSC_CTL_32B_tag CTL;               /* offset: 0x0000 size: 32 bit */
 5868       int8_t OSC_reserved_0004[92];
 5869     } OSC_tag;
 5870   
 5871   #define OSC                            (*(volatile OSC_tag *) 0xC3FE0000UL)
 5872   
 5873     /****************************************************************/
 5874     /*                                                              */
 5875     /* Module: RC  */
 5876     /*                                                              */
 5877     /****************************************************************/
 5878     typedef union {                      /* RC_CTL - Control Register */
 5879       vuint32_t R;
 5880       struct {
 5881        vuint32_t:
 5882         10;
 5883         vuint32_t RCTRIM:6;              /* Main RC Trimming Bits */
 5884        vuint32_t:
 5885         3;
 5886         vuint32_t RCDIV:5;               /* Main RC Clock Division Factor */
 5887        vuint32_t:
 5888         2;
 5889         vuint32_t S_RC_STDBY:1;          /* MRC Oscillator Powerdown Status */
 5890        vuint32_t:
 5891         5;
 5892       } B;
 5893     } RC_CTL_32B_tag;
 5894   
 5895     typedef struct RC_struct_tag {
 5896       /* RC_CTL - Control Register */
 5897       RC_CTL_32B_tag CTL;                /* offset: 0x0000 size: 32 bit */
 5898       int8_t RC_reserved_0004[16380];
 5899     } RC_tag;
 5900   
 5901   #define RC                             (*(volatile RC_tag *) 0xC3FE0060UL)
 5902   
 5903     /****************************************************************/
 5904     /*                                                              */
 5905     /* Module: PLLD  */
 5906     /*                                                              */
 5907     /****************************************************************/
 5908     typedef union {                      /* PLLD_CR - Control Register */
 5909       vuint32_t R;
 5910       struct {
 5911        vuint32_t:
 5912         2;
 5913         vuint32_t IDF:4;                 /* PLL Input Division Factor */
 5914         vuint32_t ODF:2;                 /* PLL Output Division Factor */
 5915        vuint32_t:
 5916         1;
 5917         vuint32_t NDIV:7;                /* PLL Loop Division Factor */
 5918        vuint32_t:
 5919         7;
 5920         vuint32_t EN_PLL_SW:1;           /* Enable Progressive Clock Switching */
 5921         vuint32_t MODE:1;                /* Activate 1:1 Mode */
 5922         vuint32_t UNLOCK_ONCE:1;         /* PLL Loss of Lock */
 5923         vuint32_t M_LOCK:1;              /* Mask for the i_lock Output Interrupt */
 5924         vuint32_t I_LOCK:1;              /* PLL Lock Signal Toggle Indicator */
 5925         vuint32_t S_LOCK:1;              /* PLL has Aquired Lock */
 5926         vuint32_t PLL_FAIL_MASK:1;       /* PLL Fail Mask */
 5927         vuint32_t PLL_FAIL_FLAG:1;       /* PLL Fail Flag */
 5928        vuint32_t:
 5929         1;
 5930       } B;
 5931     } PLLD_CR_32B_tag;
 5932   
 5933     typedef union {                      /* PLLD_MR - PLLD Modulation Register */
 5934       vuint32_t R;
 5935       struct {
 5936         vuint32_t STRB_BYPASS:1;         /* Strobe Bypass */
 5937        vuint32_t:
 5938         1;
 5939         vuint32_t SPRD_SEL:1;            /* Spread Type Selection */
 5940         vuint32_t MOD_PERIOD:13;         /* Modulation Period */
 5941   
 5942   #ifndef USE_FIELD_ALIASES_PLLD
 5943   
 5944         vuint32_t SSCG_EN:1;             /* Spread Spectrum Clock Generation Enable */
 5945   
 5946   #else
 5947   
 5948         vuint32_t FM_EN:1;               /* deprecated name - please avoid */
 5949   
 5950   #endif
 5951   
 5952         vuint32_t INC_STEP:15;           /* Increment Step */
 5953       } B;
 5954     } PLLD_MR_32B_tag;
 5955   
 5956     typedef struct PLLD_struct_tag {
 5957       /* PLLD_CR - Control Register */
 5958       PLLD_CR_32B_tag CR;                /* offset: 0x0000 size: 32 bit */
 5959   
 5960       /* PLLD_MR - PLLD Modulation Register */
 5961       PLLD_MR_32B_tag MR;                /* offset: 0x0004 size: 32 bit */
 5962       int8_t PLLD_reserved_0008[24];
 5963     } PLLD_tag;
 5964   
 5965   #define PLLD0                          (*(volatile PLLD_tag *) 0xC3FE00A0UL)
 5966   #define PLLD1                          (*(volatile PLLD_tag *) 0xC3FE00C0UL)
 5967   
 5968     /****************************************************************/
 5969     /*                                                              */
 5970     /* Module: CMU  */
 5971     /*                                                              */
 5972     /****************************************************************/
 5973     typedef union {                      /* CMU_CSR - Control Status Register */
 5974       vuint32_t R;
 5975       struct {
 5976        vuint32_t:
 5977         8;
 5978         vuint32_t SFM:1;                 /* Start Frequency Measure */
 5979        vuint32_t:
 5980         13;
 5981   
 5982   #ifndef USE_FIELD_ALIASES_CMU
 5983   
 5984         vuint32_t CKSEL1:2;              /* RC Oscillator(s) Selection Bit */
 5985   
 5986   #else
 5987   
 5988         vuint32_t CLKSEL1:2;             /* deprecated name - please avoid */
 5989   
 5990   #endif
 5991   
 5992        vuint32_t:
 5993         5;
 5994         vuint32_t RCDIV:2;               /* RCfast Clock Division Factor */
 5995         vuint32_t CME_A:1;               /* PLL_A Clock Monitor Enable */
 5996       } B;
 5997     } CMU_CSR_32B_tag;
 5998   
 5999     typedef union {                      /* CMU_FDR - Frequency Display Register */
 6000       vuint32_t R;
 6001       struct {
 6002        vuint32_t:
 6003         12;
 6004         vuint32_t FD:20;                 /* Measured Frequency Bits */
 6005       } B;
 6006     } CMU_FDR_32B_tag;
 6007   
 6008     typedef union {                      /* CMU_HFREFR_A - High Frequency Reference Register */
 6009       vuint32_t R;
 6010       struct {
 6011        vuint32_t:
 6012         20;
 6013         vuint32_t HFREF_A:12;            /* High Frequency Reference Value */
 6014       } B;
 6015     } CMU_HFREFR_A_32B_tag;
 6016   
 6017     typedef union {                      /* CMU_LFREFR_A - Low Frequency Reference Register */
 6018       vuint32_t R;
 6019       struct {
 6020        vuint32_t:
 6021         20;
 6022         vuint32_t LFREF_A:12;            /* Low Frequency Reference Value */
 6023       } B;
 6024     } CMU_LFREFR_A_32B_tag;
 6025   
 6026     typedef union {                      /* CMU_ISR - Interrupt Status Register */
 6027       vuint32_t R;
 6028       struct {
 6029        vuint32_t:
 6030         28;
 6031         vuint32_t FLCI_A:1;              /* PLL_A Clock Frequency less than Reference Clock Interrupt */
 6032   
 6033   #ifndef USE_FIELD_ALIASES_CMU
 6034   
 6035         vuint32_t FHH_AI:1;              /* PLL_A Clock Frequency higher than high Reference Interrupt */
 6036   
 6037   #else
 6038   
 6039         vuint32_t FHHI_A:1;              /* deprecated name - please avoid */
 6040   
 6041   #endif
 6042   
 6043         vuint32_t FLLI_A:1;              /* PLL_A Clock Frequency less than low Reference Interrupt */
 6044         vuint32_t OLRI:1;                /* Oscillator Frequency less than RC Frequency Interrupt */
 6045       } B;
 6046     } CMU_ISR_32B_tag;
 6047   
 6048     typedef union {                      /* CMU_IMR - Interrupt Mask Register */
 6049       vuint32_t R;
 6050     } CMU_IMR_32B_tag;
 6051   
 6052     typedef union {                      /* CMU_MDR - Measurement Duration Register */
 6053       vuint32_t R;
 6054       struct {
 6055        vuint32_t:
 6056         12;
 6057         vuint32_t MD:20;                 /* Measurment Duration Bits */
 6058       } B;
 6059     } CMU_MDR_32B_tag;
 6060   
 6061     typedef struct CMU_struct_tag {
 6062       /* CMU_CSR - Control Status Register */
 6063       CMU_CSR_32B_tag CSR;               /* offset: 0x0000 size: 32 bit */
 6064   
 6065       /* CMU_FDR - Frequency Display Register */
 6066       CMU_FDR_32B_tag FDR;               /* offset: 0x0004 size: 32 bit */
 6067   
 6068       /* CMU_HFREFR_A - High Frequency Reference Register */
 6069       CMU_HFREFR_A_32B_tag HFREFR_A;     /* offset: 0x0008 size: 32 bit */
 6070   
 6071       /* CMU_LFREFR_A - Low Frequency Reference Register */
 6072       CMU_LFREFR_A_32B_tag LFREFR_A;     /* offset: 0x000C size: 32 bit */
 6073   
 6074       /* CMU_ISR - Interrupt Status Register */
 6075       CMU_ISR_32B_tag ISR;               /* offset: 0x0010 size: 32 bit */
 6076   
 6077       /* CMU_IMR - Interrupt Mask Register */
 6078       CMU_IMR_32B_tag IMR;               /* offset: 0x0014 size: 32 bit */
 6079   
 6080       /* CMU_MDR - Measurement Duration Register */
 6081       CMU_MDR_32B_tag MDR;               /* offset: 0x0018 size: 32 bit */
 6082       int8_t CMU_reserved_001C[16356];
 6083     } CMU_tag;
 6084   
 6085   #define CMU0                           (*(volatile CMU_tag *) 0xC3FE0100UL)
 6086   #define CMU1                           (*(volatile CMU_tag *) 0xC3FE0120UL)
 6087   #define CMU2                           (*(volatile CMU_tag *) 0xC3FE0140UL)
 6088   
 6089     /****************************************************************/
 6090     /*                                                              */
 6091     /* Module: CGM  */
 6092     /*                                                              */
 6093     /****************************************************************/
 6094     typedef union {                      /* Output Clock Enable Register */
 6095       vuint32_t R;
 6096       vuint8_t BYTE[4];                  /* individual bytes can be accessed */
 6097       vuint16_t HALF[2];                 /* individual halfwords can be accessed */
 6098       vuint32_t WORD;                    /* individual words can be accessed */
 6099       struct {
 6100        vuint32_t:
 6101         31;
 6102         vuint32_t EN:1;                  /* Clock Enable Bit */
 6103       } B;
 6104     } CGM_OC_EN_32B_tag;
 6105   
 6106     typedef union {                      /* Output Clock Division Select Register */
 6107       vuint32_t R;
 6108       vuint8_t BYTE[4];                  /* individual bytes can be accessed */
 6109       vuint16_t HALF[2];                 /* individual halfwords can be accessed */
 6110       vuint32_t WORD;                    /* individual words can be accessed */
 6111       struct {
 6112        vuint32_t:
 6113         2;
 6114         vuint32_t SELDIV:2;              /* Output Clock Division Select */
 6115         vuint32_t SELCTL:4;              /* Output Clock Source Selection Control */
 6116        vuint32_t:
 6117         24;
 6118       } B;
 6119     } CGM_OCDS_SC_32B_tag;
 6120   
 6121     typedef union {                      /* System Clock Select Status Register */
 6122       vuint32_t R;
 6123       vuint8_t BYTE[4];                  /* individual bytes can be accessed */
 6124       vuint16_t HALF[2];                 /* individual halfwords can be accessed */
 6125       vuint32_t WORD;                    /* individual words can be accessed */
 6126       struct {
 6127        vuint32_t:
 6128         4;
 6129         vuint32_t SELSTAT:4;             /* System Clock Source Selection Status */
 6130        vuint32_t:
 6131         24;
 6132       } B;
 6133     } CGM_SC_SS_32B_tag;
 6134   
 6135     typedef union {                      /* System Clock Divider Configuration Register */
 6136       vuint32_t R;
 6137       vuint8_t BYTE[4];                  /* individual bytes can be accessed */
 6138       vuint16_t HALF[2];                 /* individual halfwords can be accessed */
 6139       vuint32_t WORD;                    /* individual words can be accessed */
 6140       struct {
 6141         vuint32_t DE0:1;                 /* Divider 0 Enable */
 6142        vuint32_t:
 6143         3;
 6144         vuint32_t DIV0:4;                /* Divider 0 Value */
 6145        vuint32_t:
 6146         24;
 6147       } B;
 6148     } CGM_SC_DC0_3_32B_tag;
 6149   
 6150     /* Register layout for all registers SC_DC ... */
 6151     typedef union {                      /* System Clock Divider Configuration Register */
 6152       vuint8_t R;
 6153       struct {
 6154         vuint8_t DE:1;                   /* Divider Enable */
 6155        vuint8_t:
 6156         3;
 6157         vuint8_t DIV:4;                  /* Divider Division Value */
 6158       } B;
 6159     } CGM_SC_DC_8B_tag;
 6160   
 6161     /* Register layout for all registers AC_SC ... */
 6162     typedef union {                      /* Auxiliary Clock Select Control Registers */
 6163       vuint32_t R;
 6164       vuint8_t BYTE[4];                  /* individual bytes can be accessed */
 6165       vuint16_t HALF[2];                 /* individual halfwords can be accessed */
 6166       vuint32_t WORD;                    /* individual words can be accessed */
 6167       struct {
 6168        vuint32_t:
 6169         4;
 6170         vuint32_t SELCTL:4;              /* Auxliary Clock Source Selection Control */
 6171        vuint32_t:
 6172         24;
 6173       } B;
 6174     } CGM_AC_SC_32B_tag;
 6175   
 6176     /* Register layout for all registers AC_DC0_3 ... */
 6177     typedef union {                      /* Auxiliary Clock Divider Configuration Registers */
 6178       vuint32_t R;
 6179       struct {
 6180         vuint32_t DE0:1;                 /* Divider 0 Enable */
 6181        vuint32_t:
 6182         3;
 6183         vuint32_t DIV0:4;                /* Divider 0 Value */
 6184         vuint32_t DE1:1;                 /* Divider 1 Enable */
 6185        vuint32_t:
 6186         3;
 6187         vuint32_t DIV1:4;                /* Divider 1 Value */
 6188        vuint32_t:
 6189         16;
 6190       } B;
 6191     } CGM_AC_DC0_3_32B_tag;
 6192   
 6193     typedef union {                      /*  */
 6194       vuint8_t R;
 6195       struct {
 6196         vuint8_t DE:1;                   /* Divider Enable */
 6197        vuint8_t:
 6198         3;
 6199         vuint8_t DIV:4;                  /* Divider Value */
 6200       } B;
 6201     } CGM_AC_DC_8B_tag;
 6202   
 6203     typedef struct CGM_AUXCLK_struct_tag {
 6204       /* Auxiliary Clock Select Control Registers */
 6205       CGM_AC_SC_32B_tag AC_SC;           /* relative offset: 0x0000 */
 6206   
 6207       /* Auxiliary Clock Divider Configuration Registers */
 6208       CGM_AC_DC0_3_32B_tag AC_DC0_3;     /* relative offset: 0x0004 */
 6209     } CGM_AUXCLK_tag;
 6210   
 6211     typedef struct CGM_struct_tag {
 6212       OSC_CTL_32B_tag OSC_CTL;           /* offset: 0x0000 size: 32 bit */
 6213       int8_t CGM_reserved_0004[92];
 6214       RC_CTL_32B_tag RC_CTL;             /* offset: 0x0060 size: 32 bit */
 6215       int8_t CGM_reserved_0064[60];
 6216       PLLD_tag FMPLL[2];                 /* offset: 0x00A0  (0x0020 x 2) */
 6217       int8_t CGM_reserved_00E0[32];
 6218       CMU_CSR_32B_tag CMU_0_CSR;         /* offset: 0x0100 size: 32 bit */
 6219       CMU_FDR_32B_tag CMU_0_FDR;         /* offset: 0x0104 size: 32 bit */
 6220       CMU_HFREFR_A_32B_tag CMU_0_HFREFR_A;/* offset: 0x0108 size: 32 bit */
 6221       CMU_LFREFR_A_32B_tag CMU_0_LFREFR_A;/* offset: 0x010C size: 32 bit */
 6222       CMU_ISR_32B_tag CMU_0_ISR;         /* offset: 0x0110 size: 32 bit */
 6223       CMU_IMR_32B_tag CMU_0_IMR;         /* offset: 0x0114 size: 32 bit */
 6224       CMU_MDR_32B_tag CMU_0_MDR;         /* offset: 0x0118 size: 32 bit */
 6225       int8_t CGM_reserved_011C[4];
 6226       CMU_CSR_32B_tag CMU_1_CSR;         /* offset: 0x0120 size: 32 bit */
 6227       int8_t CGM_reserved_0124[4];
 6228       CMU_HFREFR_A_32B_tag CMU_1_HFREFR_A;/* offset: 0x0128 size: 32 bit */
 6229       CMU_LFREFR_A_32B_tag CMU_1_LFREFR_A;/* offset: 0x012C size: 32 bit */
 6230       CMU_ISR_32B_tag CMU_1_ISR;         /* offset: 0x0130 size: 32 bit */
 6231       int8_t CGM_reserved_0134[572];
 6232       union {
 6233         /* Output Clock Enable Register */
 6234         CGM_OC_EN_32B_tag OC_EN;         /* offset: 0x0370 size: 32 bit */
 6235         CGM_OC_EN_32B_tag OCEN;          /* deprecated - please avoid */
 6236       };
 6237   
 6238       union {
 6239         /* Output Clock Division Select Register */
 6240         CGM_OCDS_SC_32B_tag OCDS_SC;     /* offset: 0x0374 size: 32 bit */
 6241         CGM_OCDS_SC_32B_tag OCDSSC;      /* deprecated - please avoid */
 6242       };
 6243   
 6244       union {
 6245         /* System Clock Select Status Register */
 6246         CGM_SC_SS_32B_tag SC_SS;         /* offset: 0x0378 size: 32 bit */
 6247         CGM_SC_SS_32B_tag SCSS;          /* deprecated - please avoid */
 6248       };
 6249   
 6250       union {
 6251         struct {
 6252           /* System Clock Divider Configuration Register */
 6253           CGM_SC_DC_8B_tag SC_DC;        /* offset: 0x037C  (0x0001 x 1) */
 6254           int8_t CGM_reserved_037D_E0[3];
 6255         };
 6256   
 6257         struct {
 6258           /* System Clock Divider Configuration Register */
 6259           CGM_SC_DC_8B_tag SC_DC0;       /* offset: 0x037C size: 8 bit */
 6260           int8_t CGM_reserved_037D_E1[3];
 6261         };
 6262   
 6263         /* System Clock Divider Configuration Register */
 6264         CGM_SC_DC0_3_32B_tag SC_DC0_3;   /* offset: 0x037C size: 32 bit */
 6265         CGM_SC_DC0_3_32B_tag SCDC;       /* deprecated - please avoid */
 6266       };
 6267   
 6268       union {
 6269         /*  Register set AUXCLK */
 6270         CGM_AUXCLK_tag AUXCLK[6];        /* offset: 0x0380  (0x0008 x 6) */
 6271         struct {
 6272           /* Auxiliary Clock Select Control Registers */
 6273           CGM_AC_SC_32B_tag AC0_SC;      /* offset: 0x0380 size: 32 bit */
 6274   
 6275           /* Auxiliary Clock Divider Configuration Registers */
 6276           CGM_AC_DC0_3_32B_tag AC0_DC0_3;/* offset: 0x0384 size: 32 bit */
 6277   
 6278           /* Auxiliary Clock Select Control Registers */
 6279           CGM_AC_SC_32B_tag AC1_SC;      /* offset: 0x0388 size: 32 bit */
 6280   
 6281           /* Auxiliary Clock Divider Configuration Registers */
 6282           CGM_AC_DC0_3_32B_tag AC1_DC0_3;/* offset: 0x038C size: 32 bit */
 6283   
 6284           /* Auxiliary Clock Select Control Registers */
 6285           CGM_AC_SC_32B_tag AC2_SC;      /* offset: 0x0390 size: 32 bit */
 6286   
 6287           /* Auxiliary Clock Divider Configuration Registers */
 6288           CGM_AC_DC0_3_32B_tag AC2_DC0_3;/* offset: 0x0394 size: 32 bit */
 6289   
 6290           /* Auxiliary Clock Select Control Registers */
 6291           CGM_AC_SC_32B_tag AC3_SC;      /* offset: 0x0398 size: 32 bit */
 6292   
 6293           /* Auxiliary Clock Divider Configuration Registers */
 6294           CGM_AC_DC0_3_32B_tag AC3_DC0_3;/* offset: 0x039C size: 32 bit */
 6295   
 6296           /* Auxiliary Clock Select Control Registers */
 6297           CGM_AC_SC_32B_tag AC4_SC;      /* offset: 0x03A0 size: 32 bit */
 6298   
 6299           /* Auxiliary Clock Divider Configuration Registers */
 6300           CGM_AC_DC0_3_32B_tag AC4_DC0_3;/* offset: 0x03A4 size: 32 bit */
 6301   
 6302           /* Auxiliary Clock Select Control Registers */
 6303           CGM_AC_SC_32B_tag AC5_SC;      /* offset: 0x03A8 size: 32 bit */
 6304   
 6305           /* Auxiliary Clock Divider Configuration Registers */
 6306           CGM_AC_DC0_3_32B_tag AC5_DC0_3;/* offset: 0x03AC size: 32 bit */
 6307         };
 6308   
 6309         struct {
 6310           CGM_AC_SC_32B_tag AC0SC;       /* deprecated - please avoid */
 6311           CGM_AC_DC0_3_32B_tag AC0DC;    /* deprecated - please avoid */
 6312           CGM_AC_SC_32B_tag AC1SC;       /* deprecated - please avoid */
 6313           CGM_AC_DC0_3_32B_tag AC1DC;    /* deprecated - please avoid */
 6314           CGM_AC_SC_32B_tag AC2SC;       /* deprecated - please avoid */
 6315           CGM_AC_DC0_3_32B_tag AC2DC;    /* deprecated - please avoid */
 6316           CGM_AC_SC_32B_tag AC3SC;       /* deprecated - please avoid */
 6317           CGM_AC_DC0_3_32B_tag AC3DC;    /* deprecated - please avoid */
 6318           CGM_AC_SC_32B_tag AC4SC;       /* deprecated - please avoid */
 6319           CGM_AC_DC0_3_32B_tag AC4DC;    /* deprecated - please avoid */
 6320           CGM_AC_SC_32B_tag AC5SC;       /* deprecated - please avoid */
 6321           CGM_AC_DC0_3_32B_tag AC5DC;    /* deprecated - please avoid */
 6322         };
 6323   
 6324         struct {
 6325           int8_t CGM_reserved_0380_I3[4];
 6326           CGM_AC_DC_8B_tag AC0_DC0;      /* offset: 0x0384 size: 8 bit */
 6327           CGM_AC_DC_8B_tag AC0_DC1;      /* offset: 0x0385 size: 8 bit */
 6328           int8_t CGM_reserved_0386_I3[6];
 6329           CGM_AC_DC_8B_tag AC1_DC0;      /* offset: 0x038C size: 8 bit */
 6330           int8_t CGM_reserved_038D_I3[7];
 6331           CGM_AC_DC_8B_tag AC2_DC0;      /* offset: 0x0394 size: 8 bit */
 6332           int8_t CGM_reserved_0395_E3[27];
 6333         };
 6334       };
 6335   
 6336       int8_t CGM_reserved_03B0[15440];
 6337     } CGM_tag;
 6338   
 6339   #define CGM                            (*(volatile CGM_tag *) 0xC3FE0000UL)
 6340   
 6341     /****************************************************************/
 6342     /*                                                              */
 6343     /* Module: RGM  */
 6344     /*                                                              */
 6345     /****************************************************************/
 6346     typedef union {                      /* Functional Event Status Register */
 6347       vuint16_t R;
 6348       struct {
 6349         vuint16_t F_EXR:1;               /* Flag for external reset */
 6350         vuint16_t F_FCCU_HARD:1;         /* Flag for FCCU hard reaction request */
 6351         vuint16_t F_FCCU_SOFT:1;         /* Flag for FCCU soft reaction request */
 6352         vuint16_t F_ST_DONE:1;           /* Flag for self-test completed */
 6353   
 6354   #ifndef USE_FIELD_ALIASES_RGM
 6355   
 6356         vuint16_t F_CMU12_FHL:1;         /* Flag for motor control/FlexRay clock freq. too high/low */
 6357   
 6358   #else
 6359   
 6360         vuint16_t F_CMU1_FHL:1;          /* deprecated name - please avoid */
 6361   
 6362   #endif
 6363   
 6364         vuint16_t F_FL_ECC_RCC:1;        /* Flag for Flash, ECC, or lock-step error */
 6365         vuint16_t F_PLL1:1;              /* Flag for PLL1 fail */
 6366         vuint16_t F_SWT:1;               /* Flag for software watchdog timer */
 6367         vuint16_t F_FCCU_SAFE:1;         /* Flag for FCCU SAFE mode request */
 6368         vuint16_t F_CMU0_FHL:1;          /* Flag for system clock freq. too high/low */
 6369         vuint16_t F_CMU0_OLR:1;          /* Flag for XOSC freq. too low */
 6370         vuint16_t F_PLL0:1;              /* Flag for PLL0 fail */
 6371         vuint16_t F_CWD:1;               /* Flag for core watchdog reset */
 6372         vuint16_t F_SOFT_FUNC:1;         /* Flag for software 'functional' reset */
 6373         vuint16_t F_CORE:1;              /* Flag for core reset */
 6374         vuint16_t F_JTAG:1;              /* Flag for JTAG initiated reset */
 6375       } B;
 6376     } RGM_FES_16B_tag;
 6377   
 6378     typedef union {                      /* Destructive Event Status Register */
 6379       vuint16_t R;
 6380       struct {
 6381   
 6382   #ifndef USE_FIELD_ALIASES_RGM
 6383   
 6384         vuint16_t F_POR:1;               /* Flag for power-on reset */
 6385   
 6386   #else
 6387   
 6388         vuint16_t POR:1;                 /* deprecated name - please avoid */
 6389   
 6390   #endif
 6391   
 6392         vuint16_t F_SOFT_DEST:1;         /* Flag for software 'destructive' reset */
 6393        vuint16_t:
 6394         7;
 6395         vuint16_t F_LVD27_IO:1;          /* Flag for 2.7V low-voltage detected (IO) */
 6396         vuint16_t F_LVD27_FLASH:1;       /* Flag for 2.7V low-voltage detected (Flash) */
 6397         vuint16_t F_LVD27_VREG:1;        /* Flag for 2.7V low-voltage detected (VREG) */
 6398        vuint16_t:
 6399         2;
 6400         vuint16_t F_HVD12:1;             /* Flag for 1.2V high-voltage detected */
 6401   
 6402   #ifndef USE_FIELD_ALIASES_RGM
 6403   
 6404         vuint16_t F_LVD12:1;             /* Flag for 1.2V low-voltage detected */
 6405   
 6406   #else
 6407   
 6408         vuint16_t F_LVD12_PD0:1;         /* deprecated name - please avoid */
 6409   
 6410   #endif
 6411   
 6412       } B;
 6413     } RGM_DES_16B_tag;
 6414   
 6415     typedef union {                      /* Functional Event Reset Disable Register */
 6416       vuint16_t R;
 6417       struct {
 6418         vuint16_t D_EXR:1;               /* Disable external reset */
 6419         vuint16_t D_FCCU_HARD:1;         /* Disable FCCU hard reaction request */
 6420         vuint16_t D_FCCU_SOFT:1;         /* Disable FCCU soft reaction request */
 6421         vuint16_t D_ST_DONE:1;           /* Disable self-test completed */
 6422   
 6423   #ifndef USE_FIELD_ALIASES_RGM
 6424   
 6425         vuint16_t D_CMU12_FHL:1;         /* Disable motor control/FlexRay clock freq. too high/low */
 6426   
 6427   #else
 6428   
 6429         vuint16_t D_CMU1_FHL:1;          /* deprecated name - please avoid */
 6430   
 6431   #endif
 6432   
 6433         vuint16_t D_FL_ECC_RCC:1;        /* Disable Flash, ECC, or lock-step error */
 6434         vuint16_t D_PLL1:1;              /* Disable PLL1 fail */
 6435         vuint16_t D_SWT:1;               /* Disable software watchdog timer */
 6436         vuint16_t D_FCCU_SAFE:1;         /* Disable FCCU SAFE mode request */
 6437         vuint16_t D_CMU0_FHL:1;          /* Disable system clock freq. too high/low */
 6438         vuint16_t D_CMU0_OLR:1;          /* Disable XOSC freq. too low */
 6439         vuint16_t D_PLL0:1;              /* Disable PLL0 fail */
 6440         vuint16_t D_CWD:1;               /* Disable core watchdog reset */
 6441         vuint16_t D_SOFT_FUNC:1;         /* Disable software 'functional' reset */
 6442         vuint16_t D_CORE:1;              /* Disable core reset */
 6443         vuint16_t D_JTAG:1;              /* Disable JTAG initiated reset */
 6444       } B;
 6445     } RGM_FERD_16B_tag;
 6446   
 6447     typedef union {                      /* Destructive Event Reset Disable Register */
 6448       vuint16_t R;
 6449       struct {
 6450         vuint16_t D_POR:1;               /* Disable power-on reset */
 6451         vuint16_t D_SOFT_DEST:1;         /* Disable software 'destructive' reset */
 6452        vuint16_t:
 6453         7;
 6454         vuint16_t D_LVD27_IO:1;          /* Disable 2.7V low-voltage detected (IO) */
 6455         vuint16_t D_LVD27_FLASH:1;       /* Disable 2.7V low-voltage detected (Flash) */
 6456         vuint16_t D_LVD27_VREG:1;        /* Disable 2.7V low-voltage detected (VREG) */
 6457        vuint16_t:
 6458         2;
 6459         vuint16_t D_HVD12:1;             /* Disable 1.2V high-voltage detected */
 6460   
 6461   #ifndef USE_FIELD_ALIASES_RGM
 6462   
 6463         vuint16_t D_LVD12:1;             /* Disable 1.2V low-voltage detected */
 6464   
 6465   #else
 6466   
 6467         vuint16_t D_LVD12_PD0:1;         /* deprecated name - please avoid */
 6468   
 6469   #endif
 6470   
 6471       } B;
 6472     } RGM_DERD_16B_tag;
 6473   
 6474     typedef union {                      /* Functional Event Alternate Request Register */
 6475       vuint16_t R;
 6476       struct {
 6477         vuint16_t AR_EXR:1;              /* Alternate Request for external reset */
 6478         vuint16_t AR_FCCU_HARD:1;        /* Alternate Request for FCCU hard reaction request */
 6479         vuint16_t AR_FCCU_SOFT:1;        /* Alternate Request for FCCU soft reaction request */
 6480         vuint16_t AR_ST_DONE:1;          /* Alternate Request for self-test completed */
 6481   
 6482   #ifndef USE_FIELD_ALIASES_RGM
 6483   
 6484         vuint16_t AR_CMU12_FHL:1;        /* Alternate Request for motor control/FlexRay clock freq. too high/low */
 6485   
 6486   #else
 6487   
 6488         vuint16_t AR_CMU1_FHL:1;         /* deprecated name - please avoid */
 6489   
 6490   #endif
 6491   
 6492         vuint16_t AR_FL_ECC_RCC:1;       /* Alternate Request for Flash, ECC, or lock-step error */
 6493         vuint16_t AR_PLL1:1;             /* Alternate Request for PLL1 fail */
 6494         vuint16_t AR_SWT:1;              /* Alternate Request for software watchdog timer */
 6495         vuint16_t AR_FCCU_SAFE:1;        /* Alternate Request for FCCU SAFE mode request */
 6496         vuint16_t AR_CMU0_FHL:1;         /* Alternate Request for system clock freq. too high/low */
 6497         vuint16_t AR_CMU0_OLR:1;         /* Alternate Request for XOSC freq. too low */
 6498         vuint16_t AR_PLL0:1;             /* Alternate Request for PLL0 fail */
 6499         vuint16_t AR_CWD:1;              /* Alternate Request for core watchdog reset */
 6500         vuint16_t AR_SOFT_FUNC:1;        /* Alternate Request for software 'functional' reset */
 6501         vuint16_t AR_CORE:1;             /* Alternate Request for core reset */
 6502         vuint16_t AR_JTAG:1;             /* Alternate Request for JTAG initiated reset */
 6503       } B;
 6504     } RGM_FEAR_16B_tag;
 6505   
 6506     typedef union {                      /* Destructive Event Alternate Request Register */
 6507       vuint16_t R;
 6508       struct {
 6509         vuint16_t AR_POR:1;              /* Destructive Event Alternate Request for power-on reset */
 6510         vuint16_t AR_SOFT_DEST:1;        /* Destructive Event Alternate Request for software 'destructive' reset */
 6511        vuint16_t:
 6512         7;
 6513         vuint16_t AR_LVD27_IO:1;         /* Destructive Event Alternate Request for 2.7V low-voltage detected (IO) */
 6514         vuint16_t AR_LVD27_FLASH:1;      /* Destructive Event Alternate Request for 2.7V low-voltage detected (Flash) */
 6515         vuint16_t AR_LVD27_VREG:1;       /* Destructive Event Alternate Request for 2.7V low-voltage detected (VREG) */
 6516        vuint16_t:
 6517         2;
 6518         vuint16_t AR_HVD12:1;            /* Destructive Event Alternate Request for 1.2V high-voltage detected */
 6519         vuint16_t AR_LVD12:1;            /* Destructive Event Alternate Request for 1.2V low-voltage detected */
 6520       } B;
 6521     } RGM_DEAR_16B_tag;
 6522   
 6523     typedef union {                      /* Functional Event Short Sequence Register */
 6524       vuint16_t R;
 6525       struct {
 6526         vuint16_t SS_EXR:1;              /* Short Sequence for external reset */
 6527         vuint16_t SS_FCCU_HARD:1;        /* Short Sequence for FCCU hard reaction request */
 6528         vuint16_t SS_FCCU_SOFT:1;        /* Short Sequence for FCCU soft reaction request */
 6529         vuint16_t SS_ST_DONE:1;          /* Short Sequence for self-test completed */
 6530   
 6531   #ifndef USE_FIELD_ALIASES_RGM
 6532   
 6533         vuint16_t SS_CMU12_FHL:1;        /* Short Sequence for motor control/FlexRay clock freq. too high/low */
 6534   
 6535   #else
 6536   
 6537         vuint16_t SS_CMU1_FHL:1;         /* deprecated name - please avoid */
 6538   
 6539   #endif
 6540   
 6541         vuint16_t SS_FL_ECC_RCC:1;       /* Short Sequence for Flash, ECC, or lock-step error */
 6542         vuint16_t SS_PLL1:1;             /* Short Sequence for PLL1 fail */
 6543         vuint16_t SS_SWT:1;              /* Short Sequence for software watchdog timer */
 6544         vuint16_t SS_FCCU_SAFE:1;        /* Short Sequence for FCCU SAFE mode request */
 6545         vuint16_t SS_CMU0_FHL:1;         /* Short Sequence for system clock freq. too high/low */
 6546         vuint16_t SS_CMU0_OLR:1;         /* Short Sequence for XOSC freq. too low */
 6547         vuint16_t SS_PLL0:1;             /* Short Sequence for PLL0 fail */
 6548         vuint16_t SS_CWD:1;              /* Short Sequence for core watchdog reset */
 6549         vuint16_t SS_SOFT_FUNC:1;        /* Short Sequence for software 'functional' reset */
 6550         vuint16_t SS_CORE:1;             /* Short Sequence for core reset */
 6551         vuint16_t SS_JTAG:1;             /* Short Sequence for JTAG initiated reset */
 6552       } B;
 6553     } RGM_FESS_16B_tag;
 6554   
 6555     typedef union {                      /* Functional Bidirectional Reset Enable Register */
 6556       vuint16_t R;
 6557       struct {
 6558         vuint16_t BE_EXR:1;              /* Bidirectional Reset Enable for external reset */
 6559         vuint16_t BE_FCCU_HARD:1;        /* Bidirectional Reset Enable for FCCU hard reaction request */
 6560         vuint16_t BE_FCCU_SOFT:1;        /* Bidirectional Reset Enable for FCCU soft reaction request */
 6561         vuint16_t BE_ST_DONE:1;          /* Bidirectional Reset Enable for self-test completed */
 6562   
 6563   #ifndef USE_FIELD_ALIASES_RGM
 6564   
 6565         vuint16_t BE_CMU12_FHL:1;        /* Bidirectional Reset Enable for motor control/FlexRay clock freq. too high/low */
 6566   
 6567   #else
 6568   
 6569         vuint16_t BE_CMU1_FHL:1;         /* deprecated name - please avoid */
 6570   
 6571   #endif
 6572   
 6573         vuint16_t BE_FL_ECC_RCC:1;       /* Bidirectional Reset Enable for Flash, ECC, or lock-step error */
 6574         vuint16_t BE_PLL1:1;             /* Bidirectional Reset Enable for PLL1 fail */
 6575         vuint16_t BE_SWT:1;              /* Bidirectional Reset Enable for software watchdog timer */
 6576         vuint16_t BE_FCCU_SAFE:1;        /* Bidirectional Reset Enable for FCCU SAFE mode request */
 6577         vuint16_t BE_CMU0_FHL:1;         /* Bidirectional Reset Enable for system clock freq. too high/low */
 6578         vuint16_t BE_CMU0_OLR:1;         /* Bidirectional Reset Enable for XOSC freq. too low */
 6579         vuint16_t BE_PLL0:1;             /* Bidirectional Reset Enable for PLL0 fail */
 6580         vuint16_t BE_CWD:1;              /* Bidirectional Reset Enable for core watchdog reset */
 6581         vuint16_t BE_SOFT_FUNC:1;        /* Bidirectional Reset Enable for software 'functional' reset */
 6582         vuint16_t BE_CORE:1;             /* Bidirectional Reset Enable for core reset */
 6583         vuint16_t BE_JTAG:1;             /* Bidirectional Reset Enable for JTAG initiated reset */
 6584       } B;
 6585     } RGM_FBRE_16B_tag;
 6586   
 6587     typedef struct RGM_struct_tag {
 6588       /* Functional Event Status Register */
 6589       RGM_FES_16B_tag FES;               /* offset: 0x0000 size: 16 bit */
 6590   
 6591       /* Destructive Event Status Register */
 6592       RGM_DES_16B_tag DES;               /* offset: 0x0002 size: 16 bit */
 6593   
 6594       /* Functional Event Reset Disable Register */
 6595       RGM_FERD_16B_tag FERD;             /* offset: 0x0004 size: 16 bit */
 6596   
 6597       /* Destructive Event Reset Disable Register */
 6598       RGM_DERD_16B_tag DERD;             /* offset: 0x0006 size: 16 bit */
 6599       int8_t RGM_reserved_0008[8];
 6600   
 6601       /* Functional Event Alternate Request Register */
 6602       RGM_FEAR_16B_tag FEAR;             /* offset: 0x0010 size: 16 bit */
 6603   
 6604       /* Destructive Event Alternate Request Register */
 6605       RGM_DEAR_16B_tag DEAR;             /* offset: 0x0012 size: 16 bit */
 6606       int8_t RGM_reserved_0014[4];
 6607   
 6608       /* Functional Event Short Sequence Register */
 6609       RGM_FESS_16B_tag FESS;             /* offset: 0x0018 size: 16 bit */
 6610       int8_t RGM_reserved_001A[2];
 6611   
 6612       /* Functional Bidirectional Reset Enable Register */
 6613       RGM_FBRE_16B_tag FBRE;             /* offset: 0x001C size: 16 bit */
 6614       int8_t RGM_reserved_001E[16354];
 6615     } RGM_tag;
 6616   
 6617   #define RGM                            (*(volatile RGM_tag *) 0xC3FE4000UL)
 6618   
 6619     /****************************************************************/
 6620     /*                                                              */
 6621     /* Module: PCU  */
 6622     /*                                                              */
 6623     /****************************************************************/
 6624   
 6625     /* Register layout for all registers PCONF ... */
 6626     typedef union {                      /* PCU_PCONF[0..15] -  Power Domain #0..#15 Configuration Register */
 6627       vuint32_t R;
 6628       struct {
 6629        vuint32_t:
 6630         18;
 6631         vuint32_t STBY0:1;               /* Power domain control during STBY0 */
 6632        vuint32_t:
 6633         2;
 6634         vuint32_t STOP0:1;               /* Power domain control during STOP0 */
 6635        vuint32_t:
 6636         1;
 6637         vuint32_t HALT0:1;               /* Power domain control during HALT0 */
 6638         vuint32_t RUN3:1;                /* Power domain control during RUN3 */
 6639         vuint32_t RUN2:1;                /* Power domain control during RUN2 */
 6640         vuint32_t RUN1:1;                /* Power domain control during RUN1 */
 6641         vuint32_t RUN0:1;                /* Power domain control during RUN0 */
 6642         vuint32_t DRUN:1;                /* Power domain control during DRUN */
 6643         vuint32_t SAFE:1;                /* Power domain control during SAFE */
 6644         vuint32_t TEST:1;                /* Power domain control during TEST */
 6645         vuint32_t RST:1;                 /* Power domain control during RST */
 6646       } B;
 6647     } PCU_PCONF_32B_tag;
 6648   
 6649     typedef union {                      /* PCU_PSTAT - Power Domain Status Register */
 6650       vuint32_t R;
 6651       struct {
 6652        vuint32_t:
 6653         16;
 6654         vuint32_t PD15:1;                /* Power Status for Power Domain 15 */
 6655         vuint32_t PD14:1;                /* Power Status for Power Domain 14 */
 6656         vuint32_t PD13:1;                /* Power Status for Power Domain 13 */
 6657         vuint32_t PD12:1;                /* Power Status for Power Domain 12 */
 6658         vuint32_t PD11:1;                /* Power Status for Power Domain 11 */
 6659         vuint32_t PD10:1;                /* Power Status for Power Domain 10 */
 6660         vuint32_t PD9:1;                 /* Power Status for Power Domain 9 */
 6661         vuint32_t PD8:1;                 /* Power Status for Power Domain 8 */
 6662         vuint32_t PD7:1;                 /* Power Status for Power Domain 7 */
 6663         vuint32_t PD6:1;                 /* Power Status for Power Domain 6 */
 6664         vuint32_t PD5:1;                 /* Power Status for Power Domain 5 */
 6665         vuint32_t PD4:1;                 /* Power Status for Power Domain 4 */
 6666         vuint32_t PD3:1;                 /* Power Status for Power Domain 3 */
 6667         vuint32_t PD2:1;                 /* Power Status for Power Domain 2 */
 6668         vuint32_t PD1:1;                 /* Power Status for Power Domain 1 */
 6669         vuint32_t PD0:1;                 /* Power Status for Power Domain 0 */
 6670       } B;
 6671     } PCU_PSTAT_32B_tag;
 6672   
 6673     typedef struct PCU_struct_tag {
 6674       union {
 6675         /* PCU_PCONF[0..15] -  Power Domain #0..#15 Configuration Register */
 6676         PCU_PCONF_32B_tag PCONF[16];     /* offset: 0x0000  (0x0004 x 16) */
 6677         struct {
 6678           /* PCU_PCONF[0..15] -  Power Domain #0..#15 Configuration Register */
 6679           PCU_PCONF_32B_tag PCONF0;      /* offset: 0x0000 size: 32 bit */
 6680           PCU_PCONF_32B_tag PCONF1;      /* offset: 0x0004 size: 32 bit */
 6681           PCU_PCONF_32B_tag PCONF2;      /* offset: 0x0008 size: 32 bit */
 6682           PCU_PCONF_32B_tag PCONF3;      /* offset: 0x000C size: 32 bit */
 6683           PCU_PCONF_32B_tag PCONF4;      /* offset: 0x0010 size: 32 bit */
 6684           PCU_PCONF_32B_tag PCONF5;      /* offset: 0x0014 size: 32 bit */
 6685           PCU_PCONF_32B_tag PCONF6;      /* offset: 0x0018 size: 32 bit */
 6686           PCU_PCONF_32B_tag PCONF7;      /* offset: 0x001C size: 32 bit */
 6687           PCU_PCONF_32B_tag PCONF8;      /* offset: 0x0020 size: 32 bit */
 6688           PCU_PCONF_32B_tag PCONF9;      /* offset: 0x0024 size: 32 bit */
 6689           PCU_PCONF_32B_tag PCONF10;     /* offset: 0x0028 size: 32 bit */
 6690           PCU_PCONF_32B_tag PCONF11;     /* offset: 0x002C size: 32 bit */
 6691           PCU_PCONF_32B_tag PCONF12;     /* offset: 0x0030 size: 32 bit */
 6692           PCU_PCONF_32B_tag PCONF13;     /* offset: 0x0034 size: 32 bit */
 6693           PCU_PCONF_32B_tag PCONF14;     /* offset: 0x0038 size: 32 bit */
 6694           PCU_PCONF_32B_tag PCONF15;     /* offset: 0x003C size: 32 bit */
 6695         };
 6696       };
 6697   
 6698       /* PCU_PSTAT - Power Domain Status Register */
 6699       PCU_PSTAT_32B_tag PSTAT;           /* offset: 0x0040 size: 32 bit */
 6700       int8_t PCU_reserved_0044[16316];
 6701     } PCU_tag;
 6702   
 6703   #define PCU                            (*(volatile PCU_tag *) 0xC3FE8000UL)
 6704   
 6705     /****************************************************************/
 6706     /*                                                              */
 6707     /* Module: PMUCTRL  */
 6708     /*                                                              */
 6709     /****************************************************************/
 6710     typedef union {                      /* PMUCTRL_STATHVD - PMU Status Register HVD */
 6711       vuint32_t R;
 6712       struct {
 6713        vuint32_t:
 6714         11;
 6715         vuint32_t HVDT_LPB:5;            /* High Voltage Detector trimming bits LPB bus */
 6716        vuint32_t:
 6717         6;
 6718         vuint32_t HVD_M:1;               /* High Voltage Detector Main */
 6719         vuint32_t HVD_B:1;               /* High Voltage Detector Backup */
 6720        vuint32_t:
 6721         4;
 6722         vuint32_t HVD_LP:4;              /* High Voltage Detector trimming bits LP bus */
 6723       } B;
 6724     } PMUCTRL_STATHVD_32B_tag;
 6725   
 6726     typedef union {                      /* PMUCTRL_STATLVD - PMU Status Register LVD */
 6727       vuint32_t R;
 6728       struct {
 6729        vuint32_t:
 6730         11;
 6731         vuint32_t LVDT_LPB:5;            /* Ligh Voltage Detector trimming bits LPB bus */
 6732        vuint32_t:
 6733         6;
 6734         vuint32_t LVD_M:1;               /* Ligh Voltage Detector Main */
 6735         vuint32_t LVD_B:1;               /* Ligh Voltage Detector Backup */
 6736        vuint32_t:
 6737         4;
 6738         vuint32_t LVD_LP:4;              /* Ligh Voltage Detector trimming bits LP bus */
 6739       } B;
 6740     } PMUCTRL_STATLVD_32B_tag;
 6741   
 6742     typedef union {                      /* PMUCTRL_STATIREG - PMU Status Register IREG */
 6743       vuint32_t R;
 6744       struct {
 6745        vuint32_t:
 6746         28;
 6747         vuint32_t IIREG_HP:4;            /* Internal ballast REGulator hpreg1 trimming bits */
 6748       } B;
 6749     } PMUCTRL_STATIREG_32B_tag;
 6750   
 6751     typedef union {                      /* PMUCTRL_STATEREG - PMU Status Register EREG */
 6752       vuint32_t R;
 6753       struct {
 6754        vuint32_t:
 6755         28;
 6756         vuint32_t EEREG_HP:4;            /* Internal ballast REGulator hpreg1 trimming bits */
 6757       } B;
 6758     } PMUCTRL_STATEREG_32B_tag;
 6759   
 6760     typedef union {                      /* PMUCTRL_STATUS - PMU Status Register STATUS */
 6761       vuint32_t R;
 6762       struct {
 6763         vuint32_t EBMM:1;                /* External Ballast Management Mode */
 6764         vuint32_t AEBD:1;                /* Automatic External Ballast Detection */
 6765         vuint32_t ENPN:1;                /* External NPN status flag */
 6766        vuint32_t:
 6767         13;
 6768         vuint32_t CTB:2;                 /* Configuration Trace Bits */
 6769        vuint32_t:
 6770         6;
 6771         vuint32_t CBS:4;                 /* Current BIST Status */
 6772         vuint32_t CPCS:4;                /* Current Pmu Configuration Status */
 6773       } B;
 6774     } PMUCTRL_STATUS_32B_tag;
 6775   
 6776     typedef union {                      /* PMUCTRL_CTRL - PMU Control Register */
 6777       vuint32_t R;
 6778       struct {
 6779        vuint32_t:
 6780         30;
 6781         vuint32_t SILHT:2;               /* Start Idle or LVD or HVD BIST Test */
 6782       } B;
 6783     } PMUCTRL_CTRL_32B_tag;
 6784   
 6785     typedef union {                      /* PMUCTRL_MASKF - PMU Mask Fault Register */
 6786       vuint32_t R;
 6787       struct {
 6788         vuint32_t MF_BB:4;               /* Mask Fault Bypass Balast */
 6789        vuint32_t:
 6790         28;
 6791       } B;
 6792     } PMUCTRL_MASKF_32B_tag;
 6793   
 6794     typedef union {                      /* PMUCTRL_FAULT - PMU Fault Monitor Register */
 6795       vuint32_t R;
 6796       struct {
 6797         vuint32_t BB_LV:4;               /* Bypass Ballast Low Voltage */
 6798        vuint32_t:
 6799         9;
 6800         vuint32_t FLNCF:1;               /* FLash voltage monitor Non Critical Fault */
 6801         vuint32_t IONCF:1;               /* IO voltage monitor Non Critical Fault */
 6802         vuint32_t RENCF:1;               /* REgulator voltage monitor Non Critical Fault */
 6803        vuint32_t:
 6804         13;
 6805         vuint32_t LHCF:1;                /* Low High voltage detector Critical Fault */
 6806         vuint32_t LNCF:1;                /* Low  voltage detector Non Critical Fault */
 6807         vuint32_t HNCF:1;                /* High voltage detector Non Critical Fault */
 6808       } B;
 6809     } PMUCTRL_FAULT_32B_tag;
 6810   
 6811     typedef union {                      /* PMUCTRL_IRQS - PMU Interrupt Request Status Register */
 6812       vuint32_t R;
 6813       struct {
 6814        vuint32_t:
 6815         10;
 6816         vuint32_t MFVMP:1;               /* Main   Flash     Voltage Monitor interrupt Pending */
 6817         vuint32_t BFVMP:1;               /* Backup Flash     Voltage Monitor interrupt Pending */
 6818         vuint32_t MIVMP:1;               /* MAin   IO        Voltage Monitor interrupt Pending */
 6819         vuint32_t BIVMP:1;               /* Backup IO        Voltage Monitor interrupt Pending */
 6820         vuint32_t MRVMP:1;               /* Main   Regulator Voltage Monitor interrupt Pending */
 6821         vuint32_t BRVMP:1;               /* Backup Regulator Voltage Monitor interrupt Pending */
 6822        vuint32_t:
 6823         12;
 6824         vuint32_t MLVDP:1;               /* Main   Low  Voltage Detector error interrupt Pending */
 6825         vuint32_t BLVDP:1;               /* Backup Low  Voltage Detector error interrupt Pending */
 6826         vuint32_t MHVDP:1;               /* Main   High Voltage Detector error interrupt Pending */
 6827         vuint32_t BHVDP:1;               /* Backup High Voltage Detector error interrupt Pending */
 6828       } B;
 6829     } PMUCTRL_IRQS_32B_tag;
 6830   
 6831     typedef union {                      /* PMUCTRL_IRQE - PMU Interrupt Request Enable Register */
 6832       vuint32_t R;
 6833       struct {
 6834        vuint32_t:
 6835         10;
 6836         vuint32_t MFVME:1;               /* Main   Flash     Voltage Monitor interrupt Enable */
 6837         vuint32_t BFVME:1;               /* Backup Flash     Voltage Monitor interrupt Enable */
 6838         vuint32_t MIVME:1;               /* MAin   IO        Voltage Monitor interrupt Enable */
 6839         vuint32_t BIVME:1;               /* Backup IO        Voltage Monitor interrupt Enable */
 6840         vuint32_t MRVME:1;               /* Main   Regulator Voltage Monitor interrupt Enable */
 6841         vuint32_t BRVME:1;               /* Backup Regulator Voltage Monitor interrupt Enable */
 6842        vuint32_t:
 6843         12;
 6844         vuint32_t MLVDE:1;               /* Main   Low  Voltage Detector error interrupt Enable */
 6845         vuint32_t BLVDE:1;               /* Backup Low  Voltage Detector error interrupt Enable */
 6846         vuint32_t MHVDE:1;               /* Main   High Voltage Detector error interrupt Enable */
 6847         vuint32_t BHVDE:1;               /* Backup High Voltage Detector error interrupt Enable */
 6848       } B;
 6849     } PMUCTRL_IRQE_32B_tag;
 6850   
 6851     typedef struct PMUCTRL_struct_tag {
 6852       int8_t PMUCTRL_reserved_0000[4];
 6853   
 6854       /* PMUCTRL_STATHVD - PMU Status Register HVD */
 6855       PMUCTRL_STATHVD_32B_tag STATHVD;   /* offset: 0x0004 size: 32 bit */
 6856   
 6857       /* PMUCTRL_STATLVD - PMU Status Register LVD */
 6858       PMUCTRL_STATLVD_32B_tag STATLVD;   /* offset: 0x0008 size: 32 bit */
 6859       int8_t PMUCTRL_reserved_000C[20];
 6860   
 6861       /* PMUCTRL_STATIREG - PMU Status Register IREG */
 6862       PMUCTRL_STATIREG_32B_tag STATIREG; /* offset: 0x0020 size: 32 bit */
 6863   
 6864       /* PMUCTRL_STATEREG - PMU Status Register EREG */
 6865       PMUCTRL_STATEREG_32B_tag STATEREG; /* offset: 0x0024 size: 32 bit */
 6866       int8_t PMUCTRL_reserved_0028[24];
 6867   
 6868       /* PMUCTRL_STATUS - PMU Status Register STATUS */
 6869       PMUCTRL_STATUS_32B_tag STATUS;     /* offset: 0x0040 size: 32 bit */
 6870   
 6871       /* PMUCTRL_CTRL - PMU Control Register */
 6872       PMUCTRL_CTRL_32B_tag CTRL;         /* offset: 0x0044 size: 32 bit */
 6873       int8_t PMUCTRL_reserved_0048[40];
 6874   
 6875       /* PMUCTRL_MASKF - PMU Mask Fault Register */
 6876       PMUCTRL_MASKF_32B_tag MASKF;       /* offset: 0x0070 size: 32 bit */
 6877   
 6878       /* PMUCTRL_FAULT - PMU Fault Monitor Register */
 6879       PMUCTRL_FAULT_32B_tag FAULT;       /* offset: 0x0074 size: 32 bit */
 6880   
 6881       /* PMUCTRL_IRQS - PMU Interrupt Request Status Register */
 6882       PMUCTRL_IRQS_32B_tag IRQS;         /* offset: 0x0078 size: 32 bit */
 6883   
 6884       /* PMUCTRL_IRQE - PMU Interrupt Request Enable Register */
 6885       PMUCTRL_IRQE_32B_tag IRQE;         /* offset: 0x007C size: 32 bit */
 6886       int8_t PMUCTRL_reserved_0080[16256];
 6887     } PMUCTRL_tag;
 6888   
 6889   #define PMUCTRL                        (*(volatile PMUCTRL_tag *) 0xC3FE8080UL)
 6890   
 6891     /****************************************************************/
 6892     /*                                                              */
 6893     /* Module: PIT_RTI  */
 6894     /*                                                              */
 6895     /****************************************************************/
 6896     typedef union {                      /* PIT_RTI_PITMCR - PIT Module Control Register */
 6897       vuint32_t R;
 6898       struct {
 6899        vuint32_t:
 6900         30;
 6901         vuint32_t MDIS:1;                /* Module Disable. Disable the module clock */
 6902         vuint32_t FRZ:1;                 /* Freeze. Allows the timers to be stoppedwhen the device enters debug mode */
 6903       } B;
 6904     } PIT_RTI_PITMCR_32B_tag;
 6905   
 6906     /* Register layout for all registers LDVAL ... */
 6907     typedef union {                      /* PIT_RTI_LDVAL - Timer Load Value Register */
 6908       vuint32_t R;
 6909       struct {
 6910         vuint32_t TSV:32;                /* Time Start Value Bits */
 6911       } B;
 6912     } PIT_RTI_LDVAL_32B_tag;
 6913   
 6914     /* Register layout for all registers CVAL ... */
 6915     typedef union {                      /* PIT_RTI_CVAL - Current Timer Value Register */
 6916       vuint32_t R;
 6917       struct {
 6918         vuint32_t TVL:32;                /* Current Timer Value Bits */
 6919       } B;
 6920     } PIT_RTI_CVAL_32B_tag;
 6921   
 6922     /* Register layout for all registers TCTRL ... */
 6923     typedef union {                      /* PIT_RTI_TCTRL - Timer Control Register */
 6924       vuint32_t R;
 6925       struct {
 6926        vuint32_t:
 6927         30;
 6928         vuint32_t TIE:1;                 /* Timer Interrupt Enable Bit */
 6929         vuint32_t TEN:1;                 /* Timer Enable Bit */
 6930       } B;
 6931     } PIT_RTI_TCTRL_32B_tag;
 6932   
 6933     /* Register layout for all registers TFLG ... */
 6934     typedef union {                      /* PIT_RTI_TFLG - Timer Flag Register */
 6935       vuint32_t R;
 6936       struct {
 6937        vuint32_t:
 6938         31;
 6939         vuint32_t TIF:1;                 /* Timer Interrupt Flag Bit */
 6940       } B;
 6941     } PIT_RTI_TFLG_32B_tag;
 6942   
 6943     typedef struct PIT_RTI_CHANNEL_struct_tag {
 6944       /* PIT_RTI_LDVAL - Timer Load Value Register */
 6945       PIT_RTI_LDVAL_32B_tag LDVAL;       /* relative offset: 0x0000 */
 6946   
 6947       /* PIT_RTI_CVAL - Current Timer Value Register */
 6948       PIT_RTI_CVAL_32B_tag CVAL;         /* relative offset: 0x0004 */
 6949   
 6950       /* PIT_RTI_TCTRL - Timer Control Register */
 6951       PIT_RTI_TCTRL_32B_tag TCTRL;       /* relative offset: 0x0008 */
 6952   
 6953       /* PIT_RTI_TFLG - Timer Flag Register */
 6954       PIT_RTI_TFLG_32B_tag TFLG;         /* relative offset: 0x000C */
 6955     } PIT_RTI_CHANNEL_tag;
 6956   
 6957     typedef struct PIT_RTI_struct_tag {
 6958       /* PIT_RTI_PITMCR - PIT Module Control Register */
 6959       PIT_RTI_PITMCR_32B_tag PITMCR;     /* offset: 0x0000 size: 32 bit */
 6960       int8_t PIT_RTI_reserved_0004[252];
 6961       union {
 6962         /*  Register set CHANNEL */
 6963         PIT_RTI_CHANNEL_tag CHANNEL[4];  /* offset: 0x0100  (0x0010 x 4) */
 6964   
 6965         /*  Alias name for CHANNEL */
 6966         PIT_RTI_CHANNEL_tag CH[4];       /* deprecated - please avoid */
 6967         struct {
 6968           /* PIT_RTI_LDVAL - Timer Load Value Register */
 6969           PIT_RTI_LDVAL_32B_tag LDVAL0;  /* offset: 0x0100 size: 32 bit */
 6970   
 6971           /* PIT_RTI_CVAL - Current Timer Value Register */
 6972           PIT_RTI_CVAL_32B_tag CVAL0;    /* offset: 0x0104 size: 32 bit */
 6973   
 6974           /* PIT_RTI_TCTRL - Timer Control Register */
 6975           PIT_RTI_TCTRL_32B_tag TCTRL0;  /* offset: 0x0108 size: 32 bit */
 6976   
 6977           /* PIT_RTI_TFLG - Timer Flag Register */
 6978           PIT_RTI_TFLG_32B_tag TFLG0;    /* offset: 0x010C size: 32 bit */
 6979   
 6980           /* PIT_RTI_LDVAL - Timer Load Value Register */
 6981           PIT_RTI_LDVAL_32B_tag LDVAL1;  /* offset: 0x0110 size: 32 bit */
 6982   
 6983           /* PIT_RTI_CVAL - Current Timer Value Register */
 6984           PIT_RTI_CVAL_32B_tag CVAL1;    /* offset: 0x0114 size: 32 bit */
 6985   
 6986           /* PIT_RTI_TCTRL - Timer Control Register */
 6987           PIT_RTI_TCTRL_32B_tag TCTRL1;  /* offset: 0x0118 size: 32 bit */
 6988   
 6989           /* PIT_RTI_TFLG - Timer Flag Register */
 6990           PIT_RTI_TFLG_32B_tag TFLG1;    /* offset: 0x011C size: 32 bit */
 6991   
 6992           /* PIT_RTI_LDVAL - Timer Load Value Register */
 6993           PIT_RTI_LDVAL_32B_tag LDVAL2;  /* offset: 0x0120 size: 32 bit */
 6994   
 6995           /* PIT_RTI_CVAL - Current Timer Value Register */
 6996           PIT_RTI_CVAL_32B_tag CVAL2;    /* offset: 0x0124 size: 32 bit */
 6997   
 6998           /* PIT_RTI_TCTRL - Timer Control Register */
 6999           PIT_RTI_TCTRL_32B_tag TCTRL2;  /* offset: 0x0128 size: 32 bit */
 7000   
 7001           /* PIT_RTI_TFLG - Timer Flag Register */
 7002           PIT_RTI_TFLG_32B_tag TFLG2;    /* offset: 0x012C size: 32 bit */
 7003   
 7004           /* PIT_RTI_LDVAL - Timer Load Value Register */
 7005           PIT_RTI_LDVAL_32B_tag LDVAL3;  /* offset: 0x0130 size: 32 bit */
 7006   
 7007           /* PIT_RTI_CVAL - Current Timer Value Register */
 7008           PIT_RTI_CVAL_32B_tag CVAL3;    /* offset: 0x0134 size: 32 bit */
 7009   
 7010           /* PIT_RTI_TCTRL - Timer Control Register */
 7011           PIT_RTI_TCTRL_32B_tag TCTRL3;  /* offset: 0x0138 size: 32 bit */
 7012   
 7013           /* PIT_RTI_TFLG - Timer Flag Register */
 7014           PIT_RTI_TFLG_32B_tag TFLG3;    /* offset: 0x013C size: 32 bit */
 7015         };
 7016       };
 7017   
 7018       int8_t PIT_RTI_reserved_0140[16064];
 7019     } PIT_RTI_tag;
 7020   
 7021   #define PIT_RTI                        (*(volatile PIT_RTI_tag *) 0xC3FF0000UL)
 7022   
 7023     /****************************************************************/
 7024     /*                                                              */
 7025     /* Module: ADC  */
 7026     /*                                                              */
 7027     /****************************************************************/
 7028     typedef union {                      /* module configuration register */
 7029       vuint32_t R;
 7030       struct {
 7031         vuint32_t OWREN:1;               /* Overwrite enable */
 7032         vuint32_t WLSIDE:1;              /* Write Left/right Alligned */
 7033         vuint32_t MODE:1;                /* One Shot/Scan Mode Selectiom */
 7034         vuint32_t EDGLEV:1;              /* edge or level selection for external start trigger */
 7035         vuint32_t TRGEN:1;               /* external trigger enable */
 7036         vuint32_t EDGE:1;                /* start trigger egde /level detection */
 7037         vuint32_t XSTRTEN:1;             /* EXTERNAL START ENABLE */
 7038         vuint32_t NSTART:1;              /* start normal conversion */
 7039        vuint32_t:
 7040         1;
 7041         vuint32_t JTRGEN:1;              /* Injectin External Trigger Enable */
 7042         vuint32_t JEDGE:1;               /* start trigger egde /level detection for injected */
 7043         vuint32_t JSTART:1;              /* injected conversion start */
 7044        vuint32_t:
 7045         2;
 7046         vuint32_t CTUEN:1;               /* CTU enabaled */
 7047        vuint32_t:
 7048         8;
 7049         vuint32_t ADCLKSEL:1;            /* Select which clock for device */
 7050         vuint32_t ABORTCHAIN:1;          /* abort chain conversion */
 7051         vuint32_t ABORT:1;               /* abort current conversion */
 7052   
 7053   #ifndef USE_FIELD_ALIASES_ADC
 7054   
 7055         vuint32_t ACKO:1;                /* Auto Clock Off Enable */
 7056   
 7057   #else
 7058   
 7059         vuint32_t ACK0:1;                /* deprecated name - please avoid */
 7060   
 7061   #endif
 7062   
 7063         vuint32_t OFFREFRESH:1;          /* offset phase selection */
 7064         vuint32_t OFFCANC:1;             /* offset phase cancellation selection */
 7065        vuint32_t:
 7066         2;
 7067         vuint32_t PWDN:1;                /* Power Down Enable */
 7068       } B;
 7069     } ADC_MCR_32B_tag;
 7070   
 7071     typedef union {                      /* module status register */
 7072       vuint32_t R;
 7073       struct {
 7074        vuint32_t:
 7075         7;
 7076         vuint32_t NSTART:1;              /* normal conversion status */
 7077         vuint32_t JABORT:1;              /* Injection chain abort status */
 7078        vuint32_t:
 7079         2;
 7080         vuint32_t JSTART:1;              /* Injection Start status */
 7081        vuint32_t:
 7082         3;
 7083         vuint32_t CTUSTART:1;            /* ctu start status */
 7084         vuint32_t CHADDR:7;              /* which address conv is goin on */
 7085        vuint32_t:
 7086         3;
 7087   
 7088   #ifndef USE_FIELD_ALIASES_ADC
 7089   
 7090         vuint32_t ACKO:1;                /* Auto Clock Off Enable status */
 7091   
 7092   #else
 7093   
 7094         vuint32_t ACK0:1;                /* deprecated name - please avoid */
 7095   
 7096   #endif
 7097   
 7098         vuint32_t OFFREFRESH:1;          /* offset refresh status */
 7099         vuint32_t OFFCANC:1;             /* offset phase cancellation status */
 7100         vuint32_t ADCSTATUS:3;           /* status of ADC FSM */
 7101       } B;
 7102     } ADC_MSR_32B_tag;
 7103   
 7104     typedef union {                      /* Interrupt status register */
 7105       vuint32_t R;
 7106       struct {
 7107        vuint32_t:
 7108         25;
 7109         vuint32_t OFFCANCOVR:1;          /* Offset cancellation phase over */
 7110         vuint32_t EOFFSET:1;             /* error in offset refresh */
 7111         vuint32_t EOCTU:1;               /* end of CTU channel conversion */
 7112         vuint32_t JEOC:1;                /* end of injected channel conversion */
 7113         vuint32_t JECH:1;                /* end ofinjected chain conversion */
 7114         vuint32_t EOC:1;                 /* end of channel conversion */
 7115         vuint32_t ECH:1;                 /* end of chain conversion */
 7116       } B;
 7117     } ADC_ISR_32B_tag;
 7118   
 7119     typedef union {                      /* CHANNEL PENDING REGISTER 0 */
 7120       vuint32_t R;
 7121       struct {
 7122   
 7123   #ifndef USE_FIELD_ALIASES_ADC
 7124   
 7125         vuint32_t EOC_CH31:1;            /* Channel 31 conversion over */
 7126   
 7127   #else
 7128   
 7129         vuint32_t EOC31:1;               /* deprecated name - please avoid */
 7130   
 7131   #endif
 7132   
 7133   #ifndef USE_FIELD_ALIASES_ADC
 7134   
 7135         vuint32_t EOC_CH30:1;            /* Channel 30 conversion over */
 7136   
 7137   #else
 7138   
 7139         vuint32_t EOC30:1;               /* deprecated name - please avoid */
 7140   
 7141   #endif
 7142   
 7143   #ifndef USE_FIELD_ALIASES_ADC
 7144   
 7145         vuint32_t EOC_CH29:1;            /* Channel 29 conversion over */
 7146   
 7147   #else
 7148   
 7149         vuint32_t EOC29:1;               /* deprecated name - please avoid */
 7150   
 7151   #endif
 7152   
 7153   #ifndef USE_FIELD_ALIASES_ADC
 7154   
 7155         vuint32_t EOC_CH28:1;            /* Channel 28 conversion over */
 7156   
 7157   #else
 7158   
 7159         vuint32_t EOC28:1;               /* deprecated name - please avoid */
 7160   
 7161   #endif
 7162   
 7163   #ifndef USE_FIELD_ALIASES_ADC
 7164   
 7165         vuint32_t EOC_CH27:1;            /* Channel 27 conversion over */
 7166   
 7167   #else
 7168   
 7169         vuint32_t EOC27:1;               /* deprecated name - please avoid */
 7170   
 7171   #endif
 7172   
 7173   #ifndef USE_FIELD_ALIASES_ADC
 7174   
 7175         vuint32_t EOC_CH26:1;            /* Channel 26 conversion over */
 7176   
 7177   #else
 7178   
 7179         vuint32_t EOC26:1;               /* deprecated name - please avoid */
 7180   
 7181   #endif
 7182   
 7183   #ifndef USE_FIELD_ALIASES_ADC
 7184   
 7185         vuint32_t EOC_CH25:1;            /* Channel 25 conversion over */
 7186   
 7187   #else
 7188   
 7189         vuint32_t EOC25:1;               /* deprecated name - please avoid */
 7190   
 7191   #endif
 7192   
 7193   #ifndef USE_FIELD_ALIASES_ADC
 7194   
 7195         vuint32_t EOC_CH24:1;            /* Channel 24 conversion over */
 7196   
 7197   #else
 7198   
 7199         vuint32_t EOC24:1;               /* deprecated name - please avoid */
 7200   
 7201   #endif
 7202   
 7203   #ifndef USE_FIELD_ALIASES_ADC
 7204   
 7205         vuint32_t EOC_CH23:1;            /* Channel 23 conversion over */
 7206   
 7207   #else
 7208   
 7209         vuint32_t EOC23:1;               /* deprecated name - please avoid */
 7210   
 7211   #endif
 7212   
 7213   #ifndef USE_FIELD_ALIASES_ADC
 7214   
 7215         vuint32_t EOC_CH22:1;            /* Channel 22 conversion over */
 7216   
 7217   #else
 7218   
 7219         vuint32_t EOC22:1;               /* deprecated name - please avoid */
 7220   
 7221   #endif
 7222   
 7223   #ifndef USE_FIELD_ALIASES_ADC
 7224   
 7225         vuint32_t EOC_CH21:1;            /* Channel 21 conversion over */
 7226   
 7227   #else
 7228   
 7229         vuint32_t EOC21:1;               /* deprecated name - please avoid */
 7230   
 7231   #endif
 7232   
 7233   #ifndef USE_FIELD_ALIASES_ADC
 7234   
 7235         vuint32_t EOC_CH20:1;            /* Channel 20 conversion over */
 7236   
 7237   #else
 7238   
 7239         vuint32_t EOC20:1;               /* deprecated name - please avoid */
 7240   
 7241   #endif
 7242   
 7243   #ifndef USE_FIELD_ALIASES_ADC
 7244   
 7245         vuint32_t EOC_CH19:1;            /* Channel 19 conversion over */
 7246   
 7247   #else
 7248   
 7249         vuint32_t EOC19:1;               /* deprecated name - please avoid */
 7250   
 7251   #endif
 7252   
 7253   #ifndef USE_FIELD_ALIASES_ADC
 7254   
 7255         vuint32_t EOC_CH18:1;            /* Channel 18 conversion over */
 7256   
 7257   #else
 7258   
 7259         vuint32_t EOC18:1;               /* deprecated name - please avoid */
 7260   
 7261   #endif
 7262   
 7263   #ifndef USE_FIELD_ALIASES_ADC
 7264   
 7265         vuint32_t EOC_CH17:1;            /* Channel 17 conversion over */
 7266   
 7267   #else
 7268   
 7269         vuint32_t EOC17:1;               /* deprecated name - please avoid */
 7270   
 7271   #endif
 7272   
 7273   #ifndef USE_FIELD_ALIASES_ADC
 7274   
 7275         vuint32_t EOC_CH16:1;            /* Channel 16 conversion over */
 7276   
 7277   #else
 7278   
 7279         vuint32_t EOC16:1;               /* deprecated name - please avoid */
 7280   
 7281   #endif
 7282   
 7283   #ifndef USE_FIELD_ALIASES_ADC
 7284   
 7285         vuint32_t EOC_CH15:1;            /* Channel 15 conversion over */
 7286   
 7287   #else
 7288   
 7289         vuint32_t EOC15:1;               /* deprecated name - please avoid */
 7290   
 7291   #endif
 7292   
 7293   #ifndef USE_FIELD_ALIASES_ADC
 7294   
 7295         vuint32_t EOC_CH14:1;            /* Channel 14 conversion over */
 7296   
 7297   #else
 7298   
 7299         vuint32_t EOC14:1;               /* deprecated name - please avoid */
 7300   
 7301   #endif
 7302   
 7303   #ifndef USE_FIELD_ALIASES_ADC
 7304   
 7305         vuint32_t EOC_CH13:1;            /* Channel 13 conversion over */
 7306   
 7307   #else
 7308   
 7309         vuint32_t EOC13:1;               /* deprecated name - please avoid */
 7310   
 7311   #endif
 7312   
 7313   #ifndef USE_FIELD_ALIASES_ADC
 7314   
 7315         vuint32_t EOC_CH12:1;            /* Channel 12 conversion over */
 7316   
 7317   #else
 7318   
 7319         vuint32_t EOC12:1;               /* deprecated name - please avoid */
 7320   
 7321   #endif
 7322   
 7323   #ifndef USE_FIELD_ALIASES_ADC
 7324   
 7325         vuint32_t EOC_CH11:1;            /* Channel 11 conversion over */
 7326   
 7327   #else
 7328   
 7329         vuint32_t EOC11:1;               /* deprecated name - please avoid */
 7330   
 7331   #endif
 7332   
 7333   #ifndef USE_FIELD_ALIASES_ADC
 7334   
 7335         vuint32_t EOC_CH10:1;            /* Channel 10 conversion over */
 7336   
 7337   #else
 7338   
 7339         vuint32_t EOC10:1;               /* deprecated name - please avoid */
 7340   
 7341   #endif
 7342   
 7343   #ifndef USE_FIELD_ALIASES_ADC
 7344   
 7345         vuint32_t EOC_CH9:1;             /* Channel 9 conversion over */
 7346   
 7347   #else
 7348   
 7349         vuint32_t EOC9:1;                /* deprecated name - please avoid */
 7350   
 7351   #endif
 7352   
 7353   #ifndef USE_FIELD_ALIASES_ADC
 7354   
 7355         vuint32_t EOC_CH8:1;             /* Channel 8 conversion over */
 7356   
 7357   #else
 7358   
 7359         vuint32_t EOC8:1;                /* deprecated name - please avoid */
 7360   
 7361   #endif
 7362   
 7363   #ifndef USE_FIELD_ALIASES_ADC
 7364   
 7365         vuint32_t EOC_CH7:1;             /* Channel 7 conversion over */
 7366   
 7367   #else
 7368   
 7369         vuint32_t EOC7:1;                /* deprecated name - please avoid */
 7370   
 7371   #endif
 7372   
 7373   #ifndef USE_FIELD_ALIASES_ADC
 7374   
 7375         vuint32_t EOC_CH6:1;             /* Channel 6 conversion over */
 7376   
 7377   #else
 7378   
 7379         vuint32_t EOC6:1;                /* deprecated name - please avoid */
 7380   
 7381   #endif
 7382   
 7383   #ifndef USE_FIELD_ALIASES_ADC
 7384   
 7385         vuint32_t EOC_CH5:1;             /* Channel 5 conversion over */
 7386   
 7387   #else
 7388   
 7389         vuint32_t EOC5:1;                /* deprecated name - please avoid */
 7390   
 7391   #endif
 7392   
 7393   #ifndef USE_FIELD_ALIASES_ADC
 7394   
 7395         vuint32_t EOC_CH4:1;             /* Channel 4 conversion over */
 7396   
 7397   #else
 7398   
 7399         vuint32_t EOC4:1;                /* deprecated name - please avoid */
 7400   
 7401   #endif
 7402   
 7403   #ifndef USE_FIELD_ALIASES_ADC
 7404   
 7405         vuint32_t EOC_CH3:1;             /* Channel 3 conversion over */
 7406   
 7407   #else
 7408   
 7409         vuint32_t EOC3:1;                /* deprecated name - please avoid */
 7410   
 7411   #endif
 7412   
 7413   #ifndef USE_FIELD_ALIASES_ADC
 7414   
 7415         vuint32_t EOC_CH2:1;             /* Channel 2 conversion over */
 7416   
 7417   #else
 7418   
 7419         vuint32_t EOC2:1;                /* deprecated name - please avoid */
 7420   
 7421   #endif
 7422   
 7423   #ifndef USE_FIELD_ALIASES_ADC
 7424   
 7425         vuint32_t EOC_CH1:1;             /* Channel 1 conversion over */
 7426   
 7427   #else
 7428   
 7429         vuint32_t EOC1:1;                /* deprecated name - please avoid */
 7430   
 7431   #endif
 7432   
 7433   #ifndef USE_FIELD_ALIASES_ADC
 7434   
 7435         vuint32_t EOC_CH0:1;             /* Channel 0 conversion over */
 7436   
 7437   #else
 7438   
 7439         vuint32_t EOC0:1;                /* deprecated name - please avoid */
 7440   
 7441   #endif
 7442   
 7443       } B;
 7444     } ADC_CEOCFR0_32B_tag;
 7445   
 7446     typedef union {                      /* CHANNEL PENDING REGISTER 1 */
 7447       vuint32_t R;
 7448       struct {
 7449         vuint32_t EOC_CH63:1;            /* Channel 63 conversion over */
 7450         vuint32_t EOC_CH62:1;            /* Channel 62 conversion over */
 7451         vuint32_t EOC_CH61:1;            /* Channel 61 conversion over */
 7452         vuint32_t EOC_CH60:1;            /* Channel 60 conversion over */
 7453         vuint32_t EOC_CH59:1;            /* Channel 59 conversion over */
 7454         vuint32_t EOC_CH58:1;            /* Channel 58 conversion over */
 7455         vuint32_t EOC_CH57:1;            /* Channel 57 conversion over */
 7456         vuint32_t EOC_CH56:1;            /* Channel 56 conversion over */
 7457         vuint32_t EOC_CH55:1;            /* Channel 55 conversion over */
 7458         vuint32_t EOC_CH54:1;            /* Channel 54 conversion over */
 7459         vuint32_t EOC_CH53:1;            /* Channel 53 conversion over */
 7460         vuint32_t EOC_CH52:1;            /* Channel 52 conversion over */
 7461         vuint32_t EOC_CH51:1;            /* Channel 51 conversion over */
 7462         vuint32_t EOC_CH50:1;            /* Channel 50 conversion over */
 7463         vuint32_t EOC_CH49:1;            /* Channel 49 conversion over */
 7464         vuint32_t EOC_CH48:1;            /* Channel 48 conversion over */
 7465         vuint32_t EOC_CH47:1;            /* Channel 47 conversion over */
 7466         vuint32_t EOC_CH46:1;            /* Channel 46 conversion over */
 7467         vuint32_t EOC_CH45:1;            /* Channel 45 conversion over */
 7468         vuint32_t EOC_CH44:1;            /* Channel 44 conversion over */
 7469         vuint32_t EOC_CH43:1;            /* Channel 43 conversion over */
 7470         vuint32_t EOC_CH42:1;            /* Channel 42 conversion over */
 7471         vuint32_t EOC_CH41:1;            /* Channel 41 conversion over */
 7472         vuint32_t EOC_CH40:1;            /* Channel 40 conversion over */
 7473         vuint32_t EOC_CH39:1;            /* Channel 39 conversion over */
 7474         vuint32_t EOC_CH38:1;            /* Channel 38 conversion over */
 7475         vuint32_t EOC_CH37:1;            /* Channel 37 conversion over */
 7476         vuint32_t EOC_CH36:1;            /* Channel 36 conversion over */
 7477         vuint32_t EOC_CH35:1;            /* Channel 35 conversion over */
 7478         vuint32_t EOC_CH34:1;            /* Channel 34 conversion over */
 7479         vuint32_t EOC_CH33:1;            /* Channel 33 conversion over */
 7480         vuint32_t EOC_CH32:1;            /* Channel 32 conversion over */
 7481       } B;
 7482     } ADC_CEOCFR1_32B_tag;
 7483   
 7484     typedef union {                      /* CHANNEL PENDING REGISTER 2 */
 7485       vuint32_t R;
 7486       struct {
 7487         vuint32_t EOC_CH95:1;            /* Channel 95 conversion over */
 7488         vuint32_t EOC_CH94:1;            /* Channel 94 conversion over */
 7489         vuint32_t EOC_CH93:1;            /* Channel 93 conversion over */
 7490         vuint32_t EOC_CH92:1;            /* Channel 92 conversion over */
 7491         vuint32_t EOC_CH91:1;            /* Channel 91 conversion over */
 7492         vuint32_t EOC_CH90:1;            /* Channel 90 conversion over */
 7493         vuint32_t EOC_CH89:1;            /* Channel 89 conversion over */
 7494         vuint32_t EOC_CH88:1;            /* Channel 88 conversion over */
 7495         vuint32_t EOC_CH87:1;            /* Channel 87 conversion over */
 7496         vuint32_t EOC_CH86:1;            /* Channel 86 conversion over */
 7497         vuint32_t EOC_CH85:1;            /* Channel 85 conversion over */
 7498         vuint32_t EOC_CH84:1;            /* Channel 84 conversion over */
 7499         vuint32_t EOC_CH83:1;            /* Channel 83 conversion over */
 7500         vuint32_t EOC_CH82:1;            /* Channel 82 conversion over */
 7501         vuint32_t EOC_CH81:1;            /* Channel 81 conversion over */
 7502         vuint32_t EOC_CH80:1;            /* Channel 80 conversion over */
 7503         vuint32_t EOC_CH79:1;            /* Channel 79 conversion over */
 7504         vuint32_t EOC_CH78:1;            /* Channel 78 conversion over */
 7505         vuint32_t EOC_CH77:1;            /* Channel 77 conversion over */
 7506         vuint32_t EOC_CH76:1;            /* Channel 76 conversion over */
 7507         vuint32_t EOC_CH75:1;            /* Channel 75 conversion over */
 7508         vuint32_t EOC_CH74:1;            /* Channel 74 conversion over */
 7509         vuint32_t EOC_CH73:1;            /* Channel 73 conversion over */
 7510         vuint32_t EOC_CH72:1;            /* Channel 72 conversion over */
 7511         vuint32_t EOC_CH71:1;            /* Channel 71 conversion over */
 7512         vuint32_t EOC_CH70:1;            /* Channel 70 conversion over */
 7513         vuint32_t EOC_CH69:1;            /* Channel 69 conversion over */
 7514         vuint32_t EOC_CH68:1;            /* Channel 68 conversion over */
 7515         vuint32_t EOC_CH67:1;            /* Channel 67 conversion over */
 7516         vuint32_t EOC_CH66:1;            /* Channel 66 conversion over */
 7517         vuint32_t EOC_CH65:1;            /* Channel 65 conversion over */
 7518         vuint32_t EOC_CH64:1;            /* Channel 64 conversion over */
 7519       } B;
 7520     } ADC_CEOCFR2_32B_tag;
 7521   
 7522     typedef union {                      /* interrupt mask register */
 7523       vuint32_t R;
 7524       struct {
 7525        vuint32_t:
 7526         25;
 7527         vuint32_t MSKOFFCANCOVR:1;       /* mask bit for Calibration over */
 7528         vuint32_t MSKEOFFSET:1;          /* mask bit for Error in offset refresh */
 7529         vuint32_t MSKEOCTU:1;            /* mask bit for EOCTU */
 7530         vuint32_t MSKJEOC:1;             /* mask bit for JEOC */
 7531         vuint32_t MSKJECH:1;             /* mask bit for JECH */
 7532         vuint32_t MSKEOC:1;              /* mask bit for EOC */
 7533         vuint32_t MSKECH:1;              /* mask bit for ECH */
 7534       } B;
 7535     } ADC_IMR_32B_tag;
 7536   
 7537     typedef union {                      /* CHANNEL INTERRUPT MASK REGISTER 0 */
 7538       vuint32_t R;
 7539       struct {
 7540         vuint32_t CIM31:1;               /* Channel 31 mask register */
 7541         vuint32_t CIM30:1;               /* Channel 30 mask register */
 7542         vuint32_t CIM29:1;               /* Channel 29 mask register */
 7543         vuint32_t CIM28:1;               /* Channel 28 mask register */
 7544         vuint32_t CIM27:1;               /* Channel 27 mask register */
 7545         vuint32_t CIM26:1;               /* Channel 26 mask register */
 7546         vuint32_t CIM25:1;               /* Channel 25 mask register */
 7547         vuint32_t CIM24:1;               /* Channel 24 mask register */
 7548         vuint32_t CIM23:1;               /* Channel 23 mask register */
 7549         vuint32_t CIM22:1;               /* Channel 22 mask register */
 7550         vuint32_t CIM21:1;               /* Channel 21 mask register */
 7551         vuint32_t CIM20:1;               /* Channel 20 mask register */
 7552         vuint32_t CIM19:1;               /* Channel 19 mask register */
 7553         vuint32_t CIM18:1;               /* Channel 18 mask register */
 7554         vuint32_t CIM17:1;               /* Channel 17 mask register */
 7555         vuint32_t CIM16:1;               /* Channel 16 mask register */
 7556         vuint32_t CIM15:1;               /* Channel 15 mask register */
 7557         vuint32_t CIM14:1;               /* Channel 14 mask register */
 7558         vuint32_t CIM13:1;               /* Channel 13 mask register */
 7559         vuint32_t CIM12:1;               /* Channel 12 mask register */
 7560         vuint32_t CIM11:1;               /* Channel 11 mask register */
 7561         vuint32_t CIM10:1;               /* Channel 10 mask register */
 7562         vuint32_t CIM9:1;                /* Channel 9  mask register */
 7563         vuint32_t CIM8:1;                /* Channel 8  mask register */
 7564         vuint32_t CIM7:1;                /* Channel 7  mask register */
 7565         vuint32_t CIM6:1;                /* Channel 6  mask register */
 7566         vuint32_t CIM5:1;                /* Channel 5  mask register */
 7567         vuint32_t CIM4:1;                /* Channel 4  mask register */
 7568         vuint32_t CIM3:1;                /* Channel 3  mask register */
 7569         vuint32_t CIM2:1;                /* Channel 2  mask register */
 7570         vuint32_t CIM1:1;                /* Channel 1  mask register */
 7571         vuint32_t CIM0:1;                /* Channel 0  mask register */
 7572       } B;
 7573     } ADC_CIMR0_32B_tag;
 7574   
 7575     typedef union {                      /* CHANNEL INTERRUPT MASK REGISTER 1 */
 7576       vuint32_t R;
 7577       struct {
 7578         vuint32_t CIM63:1;               /* Channel 63 mask register */
 7579         vuint32_t CIM62:1;               /* Channel 62 mask register */
 7580         vuint32_t CIM61:1;               /* Channel 61 mask register */
 7581         vuint32_t CIM60:1;               /* Channel 60 mask register */
 7582         vuint32_t CIM59:1;               /* Channel 59 mask register */
 7583         vuint32_t CIM58:1;               /* Channel 58 mask register */
 7584         vuint32_t CIM57:1;               /* Channel 57 mask register */
 7585         vuint32_t CIM56:1;               /* Channel 56 mask register */
 7586         vuint32_t CIM55:1;               /* Channel 55 mask register */
 7587         vuint32_t CIM54:1;               /* Channel 54 mask register */
 7588         vuint32_t CIM53:1;               /* Channel 53 mask register */
 7589         vuint32_t CIM52:1;               /* Channel 52 mask register */
 7590         vuint32_t CIM51:1;               /* Channel 51 mask register */
 7591         vuint32_t CIM50:1;               /* Channel 50 mask register */
 7592         vuint32_t CIM49:1;               /* Channel 49 mask register */
 7593         vuint32_t CIM48:1;               /* Channel 48 mask register */
 7594         vuint32_t CIM47:1;               /* Channel 47 mask register */
 7595         vuint32_t CIM46:1;               /* Channel 46 mask register */
 7596         vuint32_t CIM45:1;               /* Channel 45 mask register */
 7597         vuint32_t CIM44:1;               /* Channel 44 mask register */
 7598         vuint32_t CIM43:1;               /* Channel 43 mask register */
 7599         vuint32_t CIM42:1;               /* Channel 42 mask register */
 7600         vuint32_t CIM41:1;               /* Channel 41 mask register */
 7601         vuint32_t CIM40:1;               /* Channel 40 mask register */
 7602         vuint32_t CIM39:1;               /* Channel 39 mask register */
 7603         vuint32_t CIM38:1;               /* Channel 38 mask register */
 7604         vuint32_t CIM37:1;               /* Channel 37 mask register */
 7605         vuint32_t CIM36:1;               /* Channel 36 mask register */
 7606         vuint32_t CIM35:1;               /* Channel 35 mask register */
 7607         vuint32_t CIM34:1;               /* Channel 34 mask register */
 7608         vuint32_t CIM33:1;               /* Channel 33 mask register */
 7609         vuint32_t CIM32:1;               /* Channel 32 mask register */
 7610       } B;
 7611     } ADC_CIMR1_32B_tag;
 7612   
 7613     typedef union {                      /* CHANNEL INTERRUPT MASK REGISTER 2 */
 7614       vuint32_t R;
 7615       struct {
 7616         vuint32_t CIM95:1;               /* Channel 95 mask register */
 7617         vuint32_t CIM94:1;               /* Channel 94 mask register */
 7618         vuint32_t CIM93:1;               /* Channel 93 mask register */
 7619         vuint32_t CIM92:1;               /* Channel 92 mask register */
 7620         vuint32_t CIM91:1;               /* Channel 91 mask register */
 7621         vuint32_t CIM90:1;               /* Channel 90 mask register */
 7622         vuint32_t CIM89:1;               /* Channel 89 mask register */
 7623         vuint32_t CIM88:1;               /* Channel 88 mask register */
 7624         vuint32_t CIM87:1;               /* Channel 87 mask register */
 7625         vuint32_t CIM86:1;               /* Channel 86 mask register */
 7626         vuint32_t CIM85:1;               /* Channel 85 mask register */
 7627         vuint32_t CIM84:1;               /* Channel 84 mask register */
 7628         vuint32_t CIM83:1;               /* Channel 83 mask register */
 7629         vuint32_t CIM82:1;               /* Channel 82 mask register */
 7630         vuint32_t CIM81:1;               /* Channel 81 mask register */
 7631         vuint32_t CIM80:1;               /* Channel 80 mask register */
 7632         vuint32_t CIM79:1;               /* Channel 79 mask register */
 7633         vuint32_t CIM78:1;               /* Channel 78 mask register */
 7634         vuint32_t CIM77:1;               /* Channel 77 mask register */
 7635         vuint32_t CIM76:1;               /* Channel 76 mask register */
 7636         vuint32_t CIM75:1;               /* Channel 75 mask register */
 7637         vuint32_t CIM74:1;               /* Channel 74 mask register */
 7638         vuint32_t CIM73:1;               /* Channel 73 mask register */
 7639         vuint32_t CIM72:1;               /* Channel 72 mask register */
 7640         vuint32_t CIM71:1;               /* Channel 71 mask register */
 7641         vuint32_t CIM70:1;               /* Channel 70 mask register */
 7642         vuint32_t CIM69:1;               /* Channel 69 mask register */
 7643         vuint32_t CIM68:1;               /* Channel 68 mask register */
 7644         vuint32_t CIM67:1;               /* Channel 67 mask register */
 7645         vuint32_t CIM66:1;               /* Channel 66 mask register */
 7646         vuint32_t CIM65:1;               /* Channel 65 mask register */
 7647         vuint32_t CIM64:1;               /* Channel 64 mask register */
 7648       } B;
 7649     } ADC_CIMR2_32B_tag;
 7650   
 7651     typedef union {                      /* Watchdog Threshold interrupt status register */
 7652       vuint32_t R;
 7653       struct {
 7654        vuint32_t:
 7655         24;
 7656         vuint32_t WDG3H:1;               /* Interrupt generated on the value being higher than the HTHV 3 */
 7657         vuint32_t WDG2H:1;               /* Interrupt generated on the value being higher than the HTHV 2 */
 7658         vuint32_t WDG1H:1;               /* Interrupt generated on the value being higher than the HTHV 1 */
 7659         vuint32_t WDG0H:1;               /* Interrupt generated on the value being higher than the HTHV 0 */
 7660         vuint32_t WDG3L:1;               /* Interrupt generated on the value being lower than the LTHV 3 */
 7661         vuint32_t WDG2L:1;               /* Interrupt generated on the value being lower than the LTHV 2 */
 7662         vuint32_t WDG1L:1;               /* Interrupt generated on the value being lower than the LTHV 1 */
 7663         vuint32_t WDG0L:1;               /* Interrupt generated on the value being lower than the LTHV 0 */
 7664       } B;
 7665     } ADC_WTISR_32B_tag;
 7666   
 7667     typedef union {                      /* Watchdog interrupt MASK register */
 7668       vuint32_t R;
 7669       struct {
 7670        vuint32_t:
 7671         24;
 7672         vuint32_t MSKWDG3H:1;            /* Mask enable for Interrupt generated on the value being higher than the HTHV 3 */
 7673         vuint32_t MSKWDG2H:1;            /* Mask enable for  Interrupt generated on the value being higher than the HTHV 2 */
 7674         vuint32_t MSKWDG1H:1;            /* Mask enable for Interrupt generated on the value being higher than the HTHV 1 */
 7675         vuint32_t MSKWDG0H:1;            /* Mask enable for Interrupt generated on the value being higher than the HTHV 0 */
 7676         vuint32_t MSKWDG3L:1;            /* Mask enable for Interrupt generated on the value being lower than the LTHV 3 */
 7677         vuint32_t MSKWDG2L:1;            /* Mask enable for Interrupt generated on the value being lower than the LTHV 2 */
 7678         vuint32_t MSKWDG1L:1;            /* MAsk enable for Interrupt generated on the value being lower than the LTHV 1 */
 7679         vuint32_t MSKWDG0L:1;            /* Mask enable for Interrupt generated on the value being lower than the LTHV 0 */
 7680       } B;
 7681     } ADC_WTIMR_32B_tag;
 7682   
 7683     typedef union {                      /* DMAE register */
 7684       vuint32_t R;
 7685       struct {
 7686        vuint32_t:
 7687         30;
 7688         vuint32_t DCLR:1;                /* DMA clear sequence enable */
 7689         vuint32_t DMAEN:1;               /* DMA global enable */
 7690       } B;
 7691     } ADC_DMAE_32B_tag;
 7692   
 7693     typedef union {                      /* DMA  REGISTER 0 */
 7694       vuint32_t R;
 7695       struct {
 7696         vuint32_t DMA31:1;               /* Channel 31 DMA Enable */
 7697         vuint32_t DMA30:1;               /* Channel 30 DMA Enable */
 7698         vuint32_t DMA29:1;               /* Channel 29 DMA Enable */
 7699         vuint32_t DMA28:1;               /* Channel 28 DMA Enable */
 7700         vuint32_t DMA27:1;               /* Channel 27 DMA Enable */
 7701         vuint32_t DMA26:1;               /* Channel 26 DMA Enable */
 7702         vuint32_t DMA25:1;               /* Channel 25 DMA Enable */
 7703         vuint32_t DMA24:1;               /* Channel 24 DMA Enable */
 7704         vuint32_t DMA23:1;               /* Channel 23 DMA Enable */
 7705         vuint32_t DMA22:1;               /* Channel 22 DMA Enable */
 7706         vuint32_t DMA21:1;               /* Channel 21 DMA Enable */
 7707         vuint32_t DMA20:1;               /* Channel 20 DMA Enable */
 7708         vuint32_t DMA19:1;               /* Channel 19 DMA Enable */
 7709         vuint32_t DMA18:1;               /* Channel 18 DMA Enable */
 7710         vuint32_t DMA17:1;               /* Channel 17 DMA Enable */
 7711         vuint32_t DMA16:1;               /* Channel 16 DMA Enable */
 7712         vuint32_t DMA15:1;               /* Channel 15 DMA Enable */
 7713         vuint32_t DMA14:1;               /* Channel 14 DMA Enable */
 7714         vuint32_t DMA13:1;               /* Channel 13 DMA Enable */
 7715         vuint32_t DMA12:1;               /* Channel 12 DMA Enable */
 7716         vuint32_t DMA11:1;               /* Channel 11 DMA Enable */
 7717         vuint32_t DMA10:1;               /* Channel 10 DMA Enable */
 7718         vuint32_t DMA9:1;                /* Channel 9 DMA Enable */
 7719         vuint32_t DMA8:1;                /* Channel 8 DMA Enable */
 7720         vuint32_t DMA7:1;                /* Channel 7 DMA Enable */
 7721         vuint32_t DMA6:1;                /* Channel 6 DMA Enable */
 7722         vuint32_t DMA5:1;                /* Channel 5 DMA Enable */
 7723         vuint32_t DMA4:1;                /* Channel 4 DMA Enable */
 7724         vuint32_t DMA3:1;                /* Channel 3 DMA Enable */
 7725         vuint32_t DMA2:1;                /* Channel 2 DMA Enable */
 7726         vuint32_t DMA1:1;                /* Channel 1 DMA Enable */
 7727         vuint32_t DMA0:1;                /* Channel 0 DMA Enable */
 7728       } B;
 7729     } ADC_DMAR0_32B_tag;
 7730   
 7731     typedef union {                      /* DMA REGISTER 1 */
 7732       vuint32_t R;
 7733       struct {
 7734         vuint32_t DMA63:1;               /* Channel 63 DMA Enable */
 7735         vuint32_t DMA62:1;               /* Channel 62 DMA Enable */
 7736         vuint32_t DMA61:1;               /* Channel 61 DMA Enable */
 7737         vuint32_t DMA60:1;               /* Channel 60 DMA Enable */
 7738         vuint32_t DMA59:1;               /* Channel 59 DMA Enable */
 7739         vuint32_t DMA58:1;               /* Channel 58 DMA Enable */
 7740         vuint32_t DMA57:1;               /* Channel 57 DMA Enable */
 7741         vuint32_t DMA56:1;               /* Channel 56 DMA Enable */
 7742         vuint32_t DMA55:1;               /* Channel 55 DMA Enable */
 7743         vuint32_t DMA54:1;               /* Channel 54 DMA Enable */
 7744         vuint32_t DMA53:1;               /* Channel 53 DMA Enable */
 7745         vuint32_t DMA52:1;               /* Channel 52 DMA Enable */
 7746         vuint32_t DMA51:1;               /* Channel 51 DMA Enable */
 7747         vuint32_t DMA50:1;               /* Channel 50 DMA Enable */
 7748         vuint32_t DMA49:1;               /* Channel 49 DMA Enable */
 7749         vuint32_t DMA48:1;               /* Channel 48 DMA Enable */
 7750         vuint32_t DMA47:1;               /* Channel 47 DMA Enable */
 7751         vuint32_t DMA46:1;               /* Channel 46 DMA Enable */
 7752         vuint32_t DMA45:1;               /* Channel 45 DMA Enable */
 7753         vuint32_t DMA44:1;               /* Channel 44 DMA Enable */
 7754         vuint32_t DMA43:1;               /* Channel 43 DMA Enable */
 7755         vuint32_t DMA42:1;               /* Channel 42 DMA Enable */
 7756         vuint32_t DMA41:1;               /* Channel 41 DMA Enable */
 7757         vuint32_t DMA40:1;               /* Channel 40 DMA Enable */
 7758         vuint32_t DMA39:1;               /* Channel 39 DMA Enable */
 7759         vuint32_t DMA38:1;               /* Channel 38 DMA Enable */
 7760         vuint32_t DMA37:1;               /* Channel 37 DMA Enable */
 7761         vuint32_t DMA36:1;               /* Channel 36 DMA Enable */
 7762         vuint32_t DMA35:1;               /* Channel 35 DMA Enable */
 7763         vuint32_t DMA34:1;               /* Channel 34 DMA Enable */
 7764         vuint32_t DMA33:1;               /* Channel 33 DMA Enable */
 7765         vuint32_t DMA32:1;               /* Channel 32 DMA Enable */
 7766       } B;
 7767     } ADC_DMAR1_32B_tag;
 7768   
 7769     typedef union {                      /* DMA REGISTER 2 */
 7770       vuint32_t R;
 7771       struct {
 7772         vuint32_t DMA95:1;               /* Channel 95 DMA Enable */
 7773         vuint32_t DMA94:1;               /* Channel 94 DMA Enable */
 7774         vuint32_t DMA93:1;               /* Channel 93 DMA Enable */
 7775         vuint32_t DMA92:1;               /* Channel 92 DMA Enable */
 7776         vuint32_t DMA91:1;               /* Channel 91 DMA Enable */
 7777         vuint32_t DMA90:1;               /* Channel 90 DMA Enable */
 7778         vuint32_t DMA89:1;               /* Channel 89 DMA Enable */
 7779         vuint32_t DMA88:1;               /* Channel 88 DMA Enable */
 7780         vuint32_t DMA87:1;               /* Channel 87 DMA Enable */
 7781         vuint32_t DMA86:1;               /* Channel 86 DMA Enable */
 7782         vuint32_t DMA85:1;               /* Channel 85 DMA Enable */
 7783         vuint32_t DMA84:1;               /* Channel 84 DMA Enable */
 7784         vuint32_t DMA83:1;               /* Channel 83 DMA Enable */
 7785         vuint32_t DMA82:1;               /* Channel 82 DMA Enable */
 7786         vuint32_t DMA81:1;               /* Channel 81 DMA Enable */
 7787         vuint32_t DMA80:1;               /* Channel 80 DMA Enable */
 7788         vuint32_t DMA79:1;               /* Channel 79 DMA Enable */
 7789         vuint32_t DMA78:1;               /* Channel 78 DMA Enable */
 7790         vuint32_t DMA77:1;               /* Channel 77 DMA Enable */
 7791         vuint32_t DMA76:1;               /* Channel 76 DMA Enable */
 7792         vuint32_t DMA75:1;               /* Channel 75 DMA Enable */
 7793         vuint32_t DMA74:1;               /* Channel 74 DMA Enable */
 7794         vuint32_t DMA73:1;               /* Channel 73 DMA Enable */
 7795         vuint32_t DMA72:1;               /* Channel 72 DMA Enable */
 7796         vuint32_t DMA71:1;               /* Channel 71 DMA Enable */
 7797         vuint32_t DMA70:1;               /* Channel 70 DMA Enable */
 7798         vuint32_t DMA69:1;               /* Channel 69 DMA Enable */
 7799         vuint32_t DMA68:1;               /* Channel 68 DMA Enable */
 7800         vuint32_t DMA67:1;               /* Channel 67 DMA Enable */
 7801         vuint32_t DMA66:1;               /* Channel 66 DMA Enable */
 7802         vuint32_t DMA65:1;               /* Channel 65 DMA Enable */
 7803         vuint32_t DMA64:1;               /* Channel 64 DMA Enable */
 7804       } B;
 7805     } ADC_DMAR2_32B_tag;
 7806   
 7807     /* Register layout for all registers TRC ... */
 7808     typedef union {                      /* Threshold Control register C */
 7809       vuint32_t R;
 7810       struct {
 7811        vuint32_t:
 7812         16;
 7813         vuint32_t THREN:1;               /* Threshold enable */
 7814         vuint32_t THRINV:1;              /* invert the output pin */
 7815         vuint32_t THROP:1;               /* output pin register */
 7816        vuint32_t:
 7817         6;
 7818         vuint32_t THRCH:7;               /* Choose channel for threshold register */
 7819       } B;
 7820     } ADC_TRC_32B_tag;
 7821   
 7822     /* Register layout for all registers THRHLR ... */
 7823     typedef union {                      /* Upper Threshold register */
 7824       vuint32_t R;
 7825       struct {
 7826        vuint32_t:
 7827         4;
 7828         vuint32_t THRH:12;               /* high threshold value s */
 7829        vuint32_t:
 7830         4;
 7831         vuint32_t THRL:12;               /* low threshold value s */
 7832       } B;
 7833     } ADC_THRHLR_32B_tag;
 7834   
 7835     /* Register layout for all registers THRALT ... */
 7836     typedef union {                      /* alternate Upper Threshold register */
 7837       vuint32_t R;
 7838       struct {
 7839        vuint32_t:
 7840         6;
 7841         vuint32_t THRH:10;               /* high threshold value s */
 7842        vuint32_t:
 7843         6;
 7844         vuint32_t THRL:10;               /* low threshold value s */
 7845       } B;
 7846     } ADC_THRALT_32B_tag;
 7847   
 7848     typedef union {                      /* PRESAMPLING CONTROL REGISTER */
 7849       vuint32_t R;
 7850       struct {
 7851        vuint32_t:
 7852         25;
 7853         vuint32_t PREVAL2:2;             /* INternal Voltage selection for Presampling */
 7854         vuint32_t PREVAL1:2;             /* INternal Voltage selection for Presampling */
 7855         vuint32_t PREVAL0:2;             /* INternal Voltage selection for Presampling */
 7856   
 7857   #ifndef USE_FIELD_ALIASES_ADC
 7858   
 7859         vuint32_t PRECONV:1;             /* Presampled value */
 7860   
 7861   #else
 7862   
 7863         vuint32_t PREONCE:1;             /* deprecated name - please avoid */
 7864   
 7865   #endif
 7866   
 7867       } B;
 7868     } ADC_PSCR_32B_tag;
 7869   
 7870     typedef union {                      /* Presampling  Register 0 */
 7871       vuint32_t R;
 7872       struct {
 7873         vuint32_t PRES31:1;              /* Channel 31 Presampling  Enable */
 7874         vuint32_t PRES30:1;              /* Channel 30 Presampling  Enable */
 7875         vuint32_t PRES29:1;              /* Channel 29 Presampling  Enable */
 7876         vuint32_t PRES28:1;              /* Channel 28 Presampling  Enable */
 7877         vuint32_t PRES27:1;              /* Channel 27 Presampling  Enable */
 7878         vuint32_t PRES26:1;              /* Channel 26 Presampling  Enable */
 7879         vuint32_t PRES25:1;              /* Channel 25 Presampling  Enable */
 7880         vuint32_t PRES24:1;              /* Channel 24 Presampling  Enable */
 7881         vuint32_t PRES23:1;              /* Channel 23 Presampling  Enable */
 7882         vuint32_t PRES22:1;              /* Channel 22 Presampling  Enable */
 7883         vuint32_t PRES21:1;              /* Channel 21 Presampling  Enable */
 7884         vuint32_t PRES20:1;              /* Channel 20 Presampling  Enable */
 7885         vuint32_t PRES19:1;              /* Channel 19 Presampling  Enable */
 7886         vuint32_t PRES18:1;              /* Channel 18 Presampling  Enable */
 7887         vuint32_t PRES17:1;              /* Channel 17 Presampling  Enable */
 7888         vuint32_t PRES16:1;              /* Channel 16 Presampling  Enable */
 7889         vuint32_t PRES15:1;              /* Channel 15   Presampling  Enable */
 7890         vuint32_t PRES14:1;              /* Channel 14   Presampling  Enable */
 7891         vuint32_t PRES13:1;              /* Channel 13  Presampling   Enable */
 7892         vuint32_t PRES12:1;              /* Channel 12   Presampling  Enable */
 7893         vuint32_t PRES11:1;              /* Channel 11   Presampling  Enable */
 7894         vuint32_t PRES10:1;              /* Channel 10  Presampling   Enable */
 7895         vuint32_t PRES9:1;               /* Channel 9 Presampling   Enable */
 7896         vuint32_t PRES8:1;               /* Channel 8 Presampling  Enable */
 7897         vuint32_t PRES7:1;               /* Channel 7 Presampling    Enable */
 7898         vuint32_t PRES6:1;               /* Channel 6 Presampling   Enable */
 7899         vuint32_t PRES5:1;               /* Channel 5 Presampling  Enable */
 7900         vuint32_t PRES4:1;               /* Channel 4 Presampling  Enable */
 7901         vuint32_t PRES3:1;               /* Channel 3 Presampling  Enable */
 7902         vuint32_t PRES2:1;               /* Channel 2 Presampling  Enable */
 7903         vuint32_t PRES1:1;               /* Channel 1presampling  Enable */
 7904         vuint32_t PRES0:1;               /* Channel 0 Presampling  Enable */
 7905       } B;
 7906     } ADC_PSR0_32B_tag;
 7907   
 7908     typedef union {                      /* Presampling REGISTER 1 */
 7909       vuint32_t R;
 7910       struct {
 7911         vuint32_t PRES63:1;              /* Channel 63 Presampling  Enable */
 7912         vuint32_t PRES62:1;              /* Channel 62 Presampling  Enable */
 7913         vuint32_t PRES61:1;              /* Channel 61 Presampling  Enable */
 7914         vuint32_t PRES60:1;              /* Channel 60 Presampling  Enable */
 7915         vuint32_t PRES59:1;              /* Channel 59 Presampling  Enable */
 7916         vuint32_t PRES58:1;              /* Channel 58 Presampling  Enable */
 7917         vuint32_t PRES57:1;              /* Channel 57 Presampling  Enable */
 7918         vuint32_t PRES56:1;              /* Channel 56 Presampling  Enable */
 7919         vuint32_t PRES55:1;              /* Channel 55 Presampling  Enable */
 7920         vuint32_t PRES54:1;              /* Channel 54 Presampling  Enable */
 7921         vuint32_t PRES53:1;              /* Channel 53 Presampling  Enable */
 7922         vuint32_t PRES52:1;              /* Channel 52 Presampling  Enable */
 7923         vuint32_t PRES51:1;              /* Channel 51 Presampling  Enable */
 7924         vuint32_t PRES50:1;              /* Channel 50 Presampling  Enable */
 7925         vuint32_t PRES49:1;              /* Channel 49 Presampling  Enable */
 7926         vuint32_t PRES48:1;              /* Channel 48 Presampling  Enable */
 7927         vuint32_t PRES47:1;              /* Channel 47 Presampling  Enable */
 7928         vuint32_t PRES46:1;              /* Channel 46 Presampling  Enable */
 7929         vuint32_t PRES45:1;              /* Channel 45 Presampling  Enable */
 7930         vuint32_t PRES44:1;              /* Channel 44 Presampling  Enable */
 7931         vuint32_t PRES43:1;              /* Channel 43 Presampling  Enable */
 7932         vuint32_t PRES42:1;              /* Channel 42 Presampling  Enable */
 7933         vuint32_t PRES41:1;              /* Channel 41 Presampling  Enable */
 7934         vuint32_t PRES40:1;              /* Channel 40 Presampling  Enable */
 7935         vuint32_t PRES39:1;              /* Channel 39 Presampling  Enable */
 7936         vuint32_t PRES38:1;              /* Channel 38 Presampling  Enable */
 7937         vuint32_t PRES37:1;              /* Channel 37 Presampling  Enable */
 7938         vuint32_t PRES36:1;              /* Channel 36 Presampling  Enable */
 7939         vuint32_t PRES35:1;              /* Channel 35 Presampling  Enable */
 7940         vuint32_t PRES34:1;              /* Channel 34 Presampling  Enable */
 7941         vuint32_t PRES33:1;              /* Channel 33 Presampling  Enable */
 7942         vuint32_t PRES32:1;              /* Channel 32 Presampling  Enable */
 7943       } B;
 7944     } ADC_PSR1_32B_tag;
 7945   
 7946     typedef union {                      /* Presampling REGISTER 2 */
 7947       vuint32_t R;
 7948       struct {
 7949         vuint32_t PRES95:1;              /* Channel 95 Presampling  Enable */
 7950         vuint32_t PRES94:1;              /* Channel 94 Presampling  Enable */
 7951         vuint32_t PRES93:1;              /* Channel 93 Presampling  Enable */
 7952         vuint32_t PRES92:1;              /* Channel 92 Presampling  Enable */
 7953         vuint32_t PRES91:1;              /* Channel 91 Presampling  Enable */
 7954         vuint32_t PRES90:1;              /* Channel 90 Presampling  Enable */
 7955         vuint32_t PRES89:1;              /* Channel 89 Presampling  Enable */
 7956         vuint32_t PRES88:1;              /* Channel 88 Presampling  Enable */
 7957         vuint32_t PRES87:1;              /* Channel 87 Presampling  Enable */
 7958         vuint32_t PRES86:1;              /* Channel 86 Presampling  Enable */
 7959         vuint32_t PRES85:1;              /* Channel 85 Presampling  Enable */
 7960         vuint32_t PRES84:1;              /* Channel 84 Presampling  Enable */
 7961         vuint32_t PRES83:1;              /* Channel 83 Presampling  Enable */
 7962         vuint32_t PRES82:1;              /* Channel 82 Presampling  Enable */
 7963         vuint32_t PRES81:1;              /* Channel 81 Presampling  Enable */
 7964         vuint32_t PRES80:1;              /* Channel 80 Presampling  Enable */
 7965         vuint32_t PRES79:1;              /* Channel 79 Presampling  Enable */
 7966         vuint32_t PRES78:1;              /* Channel 78 Presampling  Enable */
 7967         vuint32_t PRES77:1;              /* Channel 77 Presampling  Enable */
 7968         vuint32_t PRES76:1;              /* Channel 76 Presampling  Enable */
 7969         vuint32_t PRES75:1;              /* Channel 75 Presampling  Enable */
 7970         vuint32_t PRES74:1;              /* Channel 74 Presampling  Enable */
 7971         vuint32_t PRES73:1;              /* Channel 73 Presampling  Enable */
 7972         vuint32_t PRES72:1;              /* Channel 72 Presampling  Enable */
 7973         vuint32_t PRES71:1;              /* Channel 71 Presampling  Enable */
 7974         vuint32_t PRES70:1;              /* Channel 70 Presampling  Enable */
 7975         vuint32_t PRES69:1;              /* Channel 69 Presampling  Enable */
 7976         vuint32_t PRES68:1;              /* Channel 68 Presampling  Enable */
 7977         vuint32_t PRES67:1;              /* Channel 67 Presampling  Enable */
 7978         vuint32_t PRES66:1;              /* Channel 66 Presampling  Enable */
 7979         vuint32_t PRES65:1;              /* Channel 65 Presampling  Enable */
 7980         vuint32_t PRES64:1;              /* Channel 64 Presampling  Enable */
 7981       } B;
 7982     } ADC_PSR2_32B_tag;
 7983   
 7984     /* Register layout for all registers CTR ... */
 7985     typedef union {                      /* conversion timing register */
 7986       vuint32_t R;
 7987       struct {
 7988        vuint32_t:
 7989         16;
 7990         vuint32_t INPLATCH:1;            /* configuration bits for the LATCHING PHASE duration */
 7991        vuint32_t:
 7992         1;
 7993         vuint32_t OFFSHIFT:2;            /* configuration for offset shift characteristics */
 7994        vuint32_t:
 7995         1;
 7996         vuint32_t INPCMP:2;              /* configuration bits for the COMPARISON duration */
 7997        vuint32_t:
 7998         1;
 7999   
 8000   #ifndef USE_FIELD_ALIASES_ADC
 8001   
 8002         vuint32_t INSAMP:8;              /* configuration bits for the SAMPLING PHASE duration */
 8003   
 8004   #else
 8005   
 8006         vuint32_t INPSAMP:8;             /* deprecated name - please avoid */
 8007   
 8008   #endif
 8009   
 8010       } B;
 8011     } ADC_CTR_32B_tag;
 8012   
 8013     typedef union {                      /* conversion timing register */
 8014       vuint32_t R;
 8015       struct {
 8016        vuint32_t:
 8017         16;
 8018         vuint32_t INPLATCH:1;            /* configuration bits for the LATCHING PHASE duration */
 8019        vuint32_t:
 8020         1;
 8021         vuint32_t OFFSHIFT:2;            /* configuration for offset shift characteristics */
 8022        vuint32_t:
 8023         1;
 8024         vuint32_t INPCMP:2;              /* configuration bits for the COMPARISON duration */
 8025        vuint32_t:
 8026         1;
 8027   
 8028   #ifndef USE_FIELD_ALIASES_ADC
 8029   
 8030         vuint32_t INSAMP:7;              /* configuration bits for the SAMPLING PHASE duration */
 8031   
 8032   #else
 8033   
 8034         vuint32_t INPSAMP:7;             /* deprecated name - please avoid */
 8035   
 8036   #endif
 8037   
 8038         vuint32_t TSENS:1;               /* configuration bit for TSENS*/
 8039       } B;
 8040     } ADC_CTR1_32B_tag;
 8041   
 8042     typedef union {                      /* NORMAL CONVERSION MASK REGISTER 0 */
 8043       vuint32_t R;
 8044       struct {
 8045         vuint32_t CH31:1;                /* Channel 31 Normal Sampling Enable */
 8046         vuint32_t CH30:1;                /* Channel 30 Normal Sampling Enable */
 8047         vuint32_t CH29:1;                /* Channel 29 Normal Sampling Enable */
 8048         vuint32_t CH28:1;                /* Channel 28 Normal Sampling Enable */
 8049         vuint32_t CH27:1;                /* Channel 27 Normal Sampling Enable */
 8050         vuint32_t CH26:1;                /* Channel 26 Normal Sampling Enable */
 8051         vuint32_t CH25:1;                /* Channel 25 Normal Sampling Enable */
 8052         vuint32_t CH24:1;                /* Channel 24 Normal Sampling Enable */
 8053         vuint32_t CH23:1;                /* Channel 23 Normal Sampling Enable */
 8054         vuint32_t CH22:1;                /* Channel 22 Normal Sampling Enable */
 8055         vuint32_t CH21:1;                /* Channel 21 Normal Sampling Enable */
 8056         vuint32_t CH20:1;                /* Channel 20 Normal Sampling Enable */
 8057         vuint32_t CH19:1;                /* Channel 19 Normal Sampling Enable */
 8058         vuint32_t CH18:1;                /* Channel 18 Normal Sampling Enable */
 8059         vuint32_t CH17:1;                /* Channel 17 Normal Sampling Enable */
 8060         vuint32_t CH16:1;                /* Channel 16 Normal Sampling Enable */
 8061         vuint32_t CH15:1;                /* Channel 15 Normal Sampling Enable */
 8062         vuint32_t CH14:1;                /* Channel 14 Normal Sampling Enable */
 8063         vuint32_t CH13:1;                /* Channel 13 Normal Sampling Enable */
 8064         vuint32_t CH12:1;                /* Channel 12 Normal Sampling Enable */
 8065         vuint32_t CH11:1;                /* Channel 11 Normal Sampling Enable */
 8066         vuint32_t CH10:1;                /* Channel 10 Normal Sampling Enable */
 8067         vuint32_t CH9:1;                 /* Channel 9 Normal Sampling Enable */
 8068         vuint32_t CH8:1;                 /* Channel 8 Normal Sampling Enable */
 8069         vuint32_t CH7:1;                 /* Channel 7 Normal Sampling Enable */
 8070         vuint32_t CH6:1;                 /* Channel 6 Normal Sampling Enable */
 8071         vuint32_t CH5:1;                 /* Channel 5 Normal Sampling Enable */
 8072         vuint32_t CH4:1;                 /* Channel 4 Normal Sampling Enable */
 8073         vuint32_t CH3:1;                 /* Channel 3 Normal Sampling Enable */
 8074         vuint32_t CH2:1;                 /* Channel 2 Normal Sampling Enable */
 8075         vuint32_t CH1:1;                 /* Channel 1 Normal Sampling Enable */
 8076         vuint32_t CH0:1;                 /* Channel 0 Normal Sampling Enable */
 8077       } B;
 8078     } ADC_NCMR0_32B_tag;
 8079   
 8080     typedef union {                      /* NORMAL CONVERSION MASK REGISTER 1 */
 8081       vuint32_t R;
 8082       struct {
 8083         vuint32_t CH63:1;                /* Channel 63 Normal Sampling Enable */
 8084         vuint32_t CH62:1;                /* Channel 62 Normal Sampling Enable */
 8085         vuint32_t CH61:1;                /* Channel 61 Normal Sampling Enable */
 8086         vuint32_t CH60:1;                /* Channel 60 Normal Sampling Enable */
 8087         vuint32_t CH59:1;                /* Channel 59 Normal Sampling Enable */
 8088         vuint32_t CH58:1;                /* Channel 58 Normal Sampling Enable */
 8089         vuint32_t CH57:1;                /* Channel 57 Normal Sampling Enable */
 8090         vuint32_t CH56:1;                /* Channel 56 Normal Sampling Enable */
 8091         vuint32_t CH55:1;                /* Channel 55 Normal Sampling Enable */
 8092         vuint32_t CH54:1;                /* Channel 54 Normal Sampling Enable */
 8093         vuint32_t CH53:1;                /* Channel 53 Normal Sampling Enable */
 8094         vuint32_t CH52:1;                /* Channel 52 Normal Sampling Enable */
 8095         vuint32_t CH51:1;                /* Channel 51 Normal Sampling Enable */
 8096         vuint32_t CH50:1;                /* Channel 50 Normal Sampling Enable */
 8097         vuint32_t CH49:1;                /* Channel 49 Normal Sampling Enable */
 8098         vuint32_t CH48:1;                /* Channel 48 Normal Sampling Enable */
 8099         vuint32_t CH47:1;                /* Channel 47 Normal Sampling Enable */
 8100         vuint32_t CH46:1;                /* Channel 46 Normal Sampling Enable */
 8101         vuint32_t CH45:1;                /* Channel 45 Normal Sampling Enable */
 8102         vuint32_t CH44:1;                /* Channel 44 Normal Sampling Enable */
 8103         vuint32_t CH43:1;                /* Channel 43 Normal Sampling Enable */
 8104         vuint32_t CH42:1;                /* Channel 42 Normal Sampling Enable */
 8105         vuint32_t CH41:1;                /* Channel 41 Normal Sampling Enable */
 8106         vuint32_t CH40:1;                /* Channel 40 Normal Sampling Enable */
 8107         vuint32_t CH39:1;                /* Channel 39 Normal Sampling Enable */
 8108         vuint32_t CH38:1;                /* Channel 38 Normal Sampling Enable */
 8109         vuint32_t CH37:1;                /* Channel 37 Normal Sampling Enable */
 8110         vuint32_t CH36:1;                /* Channel 36 Normal Sampling Enable */
 8111         vuint32_t CH35:1;                /* Channel 35 Normal Sampling Enable */
 8112         vuint32_t CH34:1;                /* Channel 34 Normal Sampling Enable */
 8113         vuint32_t CH33:1;                /* Channel 33 Normal Sampling Enable */
 8114         vuint32_t CH32:1;                /* Channel 32 Normal Sampling Enable */
 8115       } B;
 8116     } ADC_NCMR1_32B_tag;
 8117   
 8118     typedef union {                      /* NORMAL CONVERSION MASK REGISTER 2 */
 8119       vuint32_t R;
 8120       struct {
 8121         vuint32_t CH95:1;                /* Channel 95 Normal Sampling Enable */
 8122         vuint32_t CH94:1;                /* Channel 94 Normal Sampling Enable */
 8123         vuint32_t CH93:1;                /* Channel 93 Normal Sampling Enable */
 8124         vuint32_t CH92:1;                /* Channel 92 Normal Sampling Enable */
 8125         vuint32_t CH91:1;                /* Channel 91 Normal Sampling Enable */
 8126         vuint32_t CH90:1;                /* Channel 90 Normal Sampling Enable */
 8127         vuint32_t CH89:1;                /* Channel 89 Normal Sampling Enable */
 8128         vuint32_t CH88:1;                /* Channel 88 Normal Sampling Enable */
 8129         vuint32_t CH87:1;                /* Channel 87 Normal Sampling Enable */
 8130         vuint32_t CH86:1;                /* Channel 86 Normal Sampling Enable */
 8131         vuint32_t CH85:1;                /* Channel 85 Normal Sampling Enable */
 8132         vuint32_t CH84:1;                /* Channel 84 Normal Sampling Enable */
 8133         vuint32_t CH83:1;                /* Channel 83 Normal Sampling Enable */
 8134         vuint32_t CH82:1;                /* Channel 82 Normal Sampling Enable */
 8135         vuint32_t CH81:1;                /* Channel 81 Normal Sampling Enable */
 8136         vuint32_t CH80:1;                /* Channel 80 Normal Sampling Enable */
 8137         vuint32_t CH79:1;                /* Channel 79 Normal Sampling Enable */
 8138         vuint32_t CH78:1;                /* Channel 78 Normal Sampling Enable */
 8139         vuint32_t CH77:1;                /* Channel 77 Normal Sampling Enable */
 8140         vuint32_t CH76:1;                /* Channel 76 Normal Sampling Enable */
 8141         vuint32_t CH75:1;                /* Channel 75 Normal Sampling Enable */
 8142         vuint32_t CH74:1;                /* Channel 74 Normal Sampling Enable */
 8143         vuint32_t CH73:1;                /* Channel 73 Normal Sampling Enable */
 8144         vuint32_t CH72:1;                /* Channel 72 Normal Sampling Enable */
 8145         vuint32_t CH71:1;                /* Channel 71 Normal Sampling Enable */
 8146         vuint32_t CH70:1;                /* Channel 70 Normal Sampling Enable */
 8147         vuint32_t CH69:1;                /* Channel 69 Normal Sampling Enable */
 8148         vuint32_t CH68:1;                /* Channel 68 Normal Sampling Enable */
 8149         vuint32_t CH67:1;                /* Channel 67 Normal Sampling Enable */
 8150         vuint32_t CH66:1;                /* Channel 66 Normal Sampling Enable */
 8151         vuint32_t CH65:1;                /* Channel 65 Normal Sampling Enable */
 8152         vuint32_t CH64:1;                /* Channel 64 Normal Sampling Enable */
 8153       } B;
 8154     } ADC_NCMR2_32B_tag;
 8155   
 8156     typedef union {                      /* Injected Conversion Mask Register 0 */
 8157       vuint32_t R;
 8158       struct {
 8159         vuint32_t CH31:1;                /* Channel 31 Injected Sampling Enable */
 8160         vuint32_t CH30:1;                /* Channel 30 Injected Sampling Enable */
 8161         vuint32_t CH29:1;                /* Channel 29 Injected Sampling Enable */
 8162         vuint32_t CH28:1;                /* Channel 28 Injected Sampling Enable */
 8163         vuint32_t CH27:1;                /* Channel 27 Injected Sampling Enable */
 8164         vuint32_t CH26:1;                /* Channel 26 Injected Sampling Enable */
 8165         vuint32_t CH25:1;                /* Channel 25 Injected Sampling Enable */
 8166         vuint32_t CH24:1;                /* Channel 24 Injected Sampling Enable */
 8167         vuint32_t CH23:1;                /* Channel 23 Injected Sampling Enable */
 8168         vuint32_t CH22:1;                /* Channel 22 Injected Sampling Enable */
 8169         vuint32_t CH21:1;                /* Channel 21 Injected Sampling Enable */
 8170         vuint32_t CH20:1;                /* Channel 20 Injected Sampling Enable */
 8171         vuint32_t CH19:1;                /* Channel 19 Injected Sampling Enable */
 8172         vuint32_t CH18:1;                /* Channel 18 Injected Sampling Enable */
 8173         vuint32_t CH17:1;                /* Channel 17 Injected Sampling Enable */
 8174         vuint32_t CH16:1;                /* Channel 16 Injected Sampling Enable */
 8175         vuint32_t CH15:1;                /* Channel 15   Injected Sampling Enable */
 8176         vuint32_t CH14:1;                /* Channel 14   Injected Sampling Enable */
 8177         vuint32_t CH13:1;                /* Channel 13  Injected  Sampling Enable */
 8178         vuint32_t CH12:1;                /* Channel 12   Injected Sampling Enable */
 8179         vuint32_t CH11:1;                /* Channel 11   Injected Sampling Enable */
 8180         vuint32_t CH10:1;                /* Channel 10  Injected  Sampling Enable */
 8181         vuint32_t CH9:1;                 /* Channel 9 Injected  Sampling Enable */
 8182         vuint32_t CH8:1;                 /* Channel 8 Injected Sampling Enable */
 8183         vuint32_t CH7:1;                 /* Channel 7 Injected   Sampling Enable */
 8184         vuint32_t CH6:1;                 /* Channel 6 Injected  Sampling Enable */
 8185         vuint32_t CH5:1;                 /* Channel 5 Injected Sampling Enable */
 8186         vuint32_t CH4:1;                 /* Channel 4 Injected Sampling Enable */
 8187         vuint32_t CH3:1;                 /* Channel 3 Injected Sampling Enable */
 8188         vuint32_t CH2:1;                 /* Channel 2 Injected Sampling Enable */
 8189         vuint32_t CH1:1;                 /* Channel 1 injected Sampling Enable */
 8190         vuint32_t CH0:1;                 /* Channel 0 injected Sampling Enable */
 8191       } B;
 8192     } ADC_JCMR0_32B_tag;
 8193   
 8194     typedef union {                      /* INJECTED CONVERSION MASK REGISTER 1 */
 8195       vuint32_t R;
 8196       struct {
 8197         vuint32_t CH63:1;                /* Channel 63 Injected Sampling Enable */
 8198         vuint32_t CH62:1;                /* Channel 62 Injected Sampling Enable */
 8199         vuint32_t CH61:1;                /* Channel 61 Injected Sampling Enable */
 8200         vuint32_t CH60:1;                /* Channel 60 Injected Sampling Enable */
 8201         vuint32_t CH59:1;                /* Channel 59 Injected Sampling Enable */
 8202         vuint32_t CH58:1;                /* Channel 58 Injected Sampling Enable */
 8203         vuint32_t CH57:1;                /* Channel 57 Injected Sampling Enable */
 8204         vuint32_t CH56:1;                /* Channel 56 Injected Sampling Enable */
 8205         vuint32_t CH55:1;                /* Channel 55 Injected Sampling Enable */
 8206         vuint32_t CH54:1;                /* Channel 54 Injected Sampling Enable */
 8207         vuint32_t CH53:1;                /* Channel 53 Injected Sampling Enable */
 8208         vuint32_t CH52:1;                /* Channel 52 Injected Sampling Enable */
 8209         vuint32_t CH51:1;                /* Channel 51 Injected Sampling Enable */
 8210         vuint32_t CH50:1;                /* Channel 50 Injected Sampling Enable */
 8211         vuint32_t CH49:1;                /* Channel 49 Injected Sampling Enable */
 8212         vuint32_t CH48:1;                /* Channel 48 Injected Sampling Enable */
 8213         vuint32_t CH47:1;                /* Channel 47 Injected Sampling Enable */
 8214         vuint32_t CH46:1;                /* Channel 46 Injected Sampling Enable */
 8215         vuint32_t CH45:1;                /* Channel 45 Injected Sampling Enable */
 8216         vuint32_t CH44:1;                /* Channel 44 Injected Sampling Enable */
 8217         vuint32_t CH43:1;                /* Channel 43 Injected Sampling Enable */
 8218         vuint32_t CH42:1;                /* Channel 42 Injected Sampling Enable */
 8219         vuint32_t CH41:1;                /* Channel 41 Injected Sampling Enable */
 8220         vuint32_t CH40:1;                /* Channel 40 Injected Sampling Enable */
 8221         vuint32_t CH39:1;                /* Channel 39 Injected Sampling Enable */
 8222         vuint32_t CH38:1;                /* Channel 38 Injected Sampling Enable */
 8223         vuint32_t CH37:1;                /* Channel 37 Injected Sampling Enable */
 8224         vuint32_t CH36:1;                /* Channel 36 Injected Sampling Enable */
 8225         vuint32_t CH35:1;                /* Channel 35 Injected Sampling Enable */
 8226         vuint32_t CH34:1;                /* Channel 34 Injected Sampling Enable */
 8227         vuint32_t CH33:1;                /* Channel 33 Injected Sampling Enable */
 8228         vuint32_t CH32:1;                /* Channel 32 Injected Sampling Enable */
 8229       } B;
 8230     } ADC_JCMR1_32B_tag;
 8231   
 8232     typedef union {                      /* INJECTED CONVERSION MASK REGISTER 2 */
 8233       vuint32_t R;
 8234       struct {
 8235         vuint32_t CH95:1;                /* Channel 95 Injected Sampling Enable */
 8236         vuint32_t CH94:1;                /* Channel 94 Injected Sampling Enable */
 8237         vuint32_t CH93:1;                /* Channel 93 Injected Sampling Enable */
 8238         vuint32_t CH92:1;                /* Channel 92 Injected Sampling Enable */
 8239         vuint32_t CH91:1;                /* Channel 91 Injected Sampling Enable */
 8240         vuint32_t CH90:1;                /* Channel 90 Injected Sampling Enable */
 8241         vuint32_t CH89:1;                /* Channel 89 Injected Sampling Enable */
 8242         vuint32_t CH88:1;                /* Channel 88 Injected Sampling Enable */
 8243         vuint32_t CH87:1;                /* Channel 87 Injected Sampling Enable */
 8244         vuint32_t CH86:1;                /* Channel 86 Injected Sampling Enable */
 8245         vuint32_t CH85:1;                /* Channel 85 Injected Sampling Enable */
 8246         vuint32_t CH84:1;                /* Channel 84 Injected Sampling Enable */
 8247         vuint32_t CH83:1;                /* Channel 83 Injected Sampling Enable */
 8248         vuint32_t CH82:1;                /* Channel 82 Injected Sampling Enable */
 8249         vuint32_t CH81:1;                /* Channel 81 Injected Sampling Enable */
 8250         vuint32_t CH80:1;                /* Channel 80 Injected Sampling Enable */
 8251         vuint32_t CH79:1;                /* Channel 79 Injected Sampling Enable */
 8252         vuint32_t CH78:1;                /* Channel 78 Injected Sampling Enable */
 8253         vuint32_t CH77:1;                /* Channel 77 Injected Sampling Enable */
 8254         vuint32_t CH76:1;                /* Channel 76 Injected Sampling Enable */
 8255         vuint32_t CH75:1;                /* Channel 75 Injected Sampling Enable */
 8256         vuint32_t CH74:1;                /* Channel 74 Injected Sampling Enable */
 8257         vuint32_t CH73:1;                /* Channel 73 Injected Sampling Enable */
 8258         vuint32_t CH72:1;                /* Channel 72 Injected Sampling Enable */
 8259         vuint32_t CH71:1;                /* Channel 71 Injected Sampling Enable */
 8260         vuint32_t CH70:1;                /* Channel 70 Injected Sampling Enable */
 8261         vuint32_t CH69:1;                /* Channel 69 Injected Sampling Enable */
 8262         vuint32_t CH68:1;                /* Channel 68 Injected Sampling Enable */
 8263         vuint32_t CH67:1;                /* Channel 67 Injected Sampling Enable */
 8264         vuint32_t CH66:1;                /* Channel 66 Injected Sampling Enable */
 8265         vuint32_t CH65:1;                /* Channel 65 Injected Sampling Enable */
 8266         vuint32_t CH64:1;                /* Channel 64 Injected Sampling Enable */
 8267       } B;
 8268     } ADC_JCMR2_32B_tag;
 8269   
 8270     typedef union {                      /* Offset Word Regsiter */
 8271       vuint32_t R;
 8272       struct {
 8273        vuint32_t:
 8274         15;
 8275         vuint32_t OFFSETLOAD:1;          /* load_offset */
 8276        vuint32_t:
 8277         8;
 8278   
 8279   #ifndef USE_FIELD_ALIASES_ADC
 8280   
 8281         vuint32_t OFFSET_WORD:8;         /* OFFSET word coeff.generated at the end of offset cancellation is lathed int o this register */
 8282   
 8283   #else
 8284   
 8285         vuint32_t OFFSETWORD:8;          /* deprecated name - please avoid */
 8286   
 8287   #endif
 8288   
 8289       } B;
 8290     } ADC_OFFWR_32B_tag;
 8291   
 8292     typedef union {                      /* Decode Signal Delay Register */
 8293       vuint32_t R;
 8294       struct {
 8295        vuint32_t:
 8296         24;
 8297         vuint32_t DSD:8;                 /* take into account the settling time of the external mux */
 8298       } B;
 8299     } ADC_DSDR_32B_tag;
 8300   
 8301     typedef union {                      /* Power Down Dealy Register */
 8302       vuint32_t R;
 8303       struct {
 8304        vuint32_t:
 8305         24;
 8306         vuint32_t PDED:8;                /* The delay between the power down bit reset and the starting of conversion */
 8307       } B;
 8308     } ADC_PDEDR_32B_tag;
 8309   
 8310     /* Register layout for all registers CDR ... */
 8311     typedef union {                      /* CHANNEL DATA REGS */
 8312       vuint32_t R;
 8313       struct {
 8314        vuint32_t:
 8315         12;
 8316         vuint32_t VALID:1;               /* validity of data */
 8317         vuint32_t OVERW:1;               /* overwrite data */
 8318         vuint32_t RESULT:2;              /* reflects mode conversion */
 8319        vuint32_t:
 8320         4;
 8321         vuint32_t CDATA:12;              /* Channel 0 converted data */
 8322       } B;
 8323     } ADC_CDR_32B_tag;
 8324   
 8325     typedef union {                      /* Upper Threshold register 4 is not contiguous to 3 */
 8326       vuint32_t R;
 8327       struct {
 8328        vuint32_t:
 8329         4;
 8330         vuint32_t THRH:12;               /* high threshold value s */
 8331        vuint32_t:
 8332         4;
 8333         vuint32_t THRL:12;               /* low threshold value s */
 8334       } B;
 8335     } ADC_THRHLR4_32B_tag;
 8336   
 8337     typedef union {                      /* Upper Threshold register 5 */
 8338       vuint32_t R;
 8339       struct {
 8340        vuint32_t:
 8341         4;
 8342         vuint32_t THRH:12;               /* high threshold value s */
 8343        vuint32_t:
 8344         4;
 8345         vuint32_t THRL:12;               /* low threshold value s */
 8346       } B;
 8347     } ADC_THRHLR5_32B_tag;
 8348   
 8349     typedef union {                      /* Upper Threshold register 6 */
 8350       vuint32_t R;
 8351       struct {
 8352        vuint32_t:
 8353         4;
 8354         vuint32_t THRH:12;               /* high threshold value s */
 8355        vuint32_t:
 8356         4;
 8357         vuint32_t THRL:12;               /* low threshold value s */
 8358       } B;
 8359     } ADC_THRHLR6_32B_tag;
 8360   
 8361     typedef union {                      /* Upper Threshold register 7 */
 8362       vuint32_t R;
 8363       struct {
 8364        vuint32_t:
 8365         4;
 8366         vuint32_t THRH:12;               /* high threshold value s */
 8367        vuint32_t:
 8368         4;
 8369         vuint32_t THRL:12;               /* low threshold value s */
 8370       } B;
 8371     } ADC_THRHLR7_32B_tag;
 8372   
 8373     typedef union {                      /* Upper Threshold register 8 */
 8374       vuint32_t R;
 8375       struct {
 8376        vuint32_t:
 8377         4;
 8378         vuint32_t THRH:12;               /* high threshold value s */
 8379        vuint32_t:
 8380         4;
 8381         vuint32_t THRL:12;               /* low threshold value s */
 8382       } B;
 8383     } ADC_THRHLR8_32B_tag;
 8384   
 8385     typedef union {                      /* Upper Threshold register 9 */
 8386       vuint32_t R;
 8387       struct {
 8388        vuint32_t:
 8389         4;
 8390         vuint32_t THRH:12;               /* high threshold value s */
 8391        vuint32_t:
 8392         4;
 8393         vuint32_t THRL:12;               /* low threshold value s */
 8394       } B;
 8395     } ADC_THRHLR9_32B_tag;
 8396   
 8397     typedef union {                      /* Upper Threshold register 10 */
 8398       vuint32_t R;
 8399       struct {
 8400        vuint32_t:
 8401         4;
 8402         vuint32_t THRH:12;               /* high threshold value s */
 8403        vuint32_t:
 8404         4;
 8405         vuint32_t THRL:12;               /* low threshold value s */
 8406       } B;
 8407     } ADC_THRHLR10_32B_tag;
 8408   
 8409     typedef union {                      /* Upper Threshold register 11 */
 8410       vuint32_t R;
 8411       struct {
 8412        vuint32_t:
 8413         4;
 8414         vuint32_t THRH:12;               /* high threshold value s */
 8415        vuint32_t:
 8416         4;
 8417         vuint32_t THRL:12;               /* low threshold value s */
 8418       } B;
 8419     } ADC_THRHLR11_32B_tag;
 8420   
 8421     typedef union {                      /* Upper Threshold register 12 */
 8422       vuint32_t R;
 8423       struct {
 8424        vuint32_t:
 8425         4;
 8426         vuint32_t THRH:12;               /* high threshold value s */
 8427        vuint32_t:
 8428         4;
 8429         vuint32_t THRL:12;               /* low threshold value s */
 8430       } B;
 8431     } ADC_THRHLR12_32B_tag;
 8432   
 8433     typedef union {                      /* Upper Threshold register 13 */
 8434       vuint32_t R;
 8435       struct {
 8436        vuint32_t:
 8437         4;
 8438         vuint32_t THRH:12;               /* high threshold value s */
 8439        vuint32_t:
 8440         4;
 8441         vuint32_t THRL:12;               /* low threshold value s */
 8442       } B;
 8443     } ADC_THRHLR13_32B_tag;
 8444   
 8445     typedef union {                      /* Upper Threshold register 14 */
 8446       vuint32_t R;
 8447       struct {
 8448        vuint32_t:
 8449         4;
 8450         vuint32_t THRH:12;               /* high threshold value s */
 8451        vuint32_t:
 8452         4;
 8453         vuint32_t THRL:12;               /* low threshold value s */
 8454       } B;
 8455     } ADC_THRHLR14_32B_tag;
 8456   
 8457     typedef union {                      /* Upper Threshold register 15 */
 8458       vuint32_t R;
 8459       struct {
 8460        vuint32_t:
 8461         4;
 8462         vuint32_t THRH:12;               /* high threshold value s */
 8463        vuint32_t:
 8464         4;
 8465         vuint32_t THRL:12;               /* low threshold value s */
 8466       } B;
 8467     } ADC_THRHLR15_32B_tag;
 8468   
 8469     /* Register layout for all registers CWSELR ... */
 8470     typedef union {                      /* Channel Watchdog Select register */
 8471       vuint32_t R;
 8472       struct {
 8473         vuint32_t WSEL_CH7:4;            /* Channel Watchdog select for channel 7+R*8 */
 8474         vuint32_t WSEL_CH6:4;            /* Channel Watchdog select for channel 6+R*8 */
 8475         vuint32_t WSEL_CH5:4;            /* Channel Watchdog select for channel 5+R*8 */
 8476         vuint32_t WSEL_CH4:4;            /* Channel Watchdog select for channel 4+R*8 */
 8477         vuint32_t WSEL_CH3:4;            /* Channel Watchdog select for channel 3+R*8 */
 8478         vuint32_t WSEL_CH2:4;            /* Channel Watchdog select for channel 2+R*8 */
 8479         vuint32_t WSEL_CH1:4;            /* Channel Watchdog select for channel 1+R*8 */
 8480         vuint32_t WSEL_CH0:4;            /* Channel Watchdog select for channel 0+R*8 */
 8481       } B;
 8482     } ADC_CWSELR_32B_tag;
 8483   
 8484     /* Register layout for all registers CWENR ... */
 8485     typedef union {                      /* Channel Watchdog Enable Register */
 8486       vuint32_t R;
 8487       struct {
 8488        vuint32_t:
 8489         16;
 8490         vuint32_t CWEN15PRT32:1;         /* Channel Watchdog Enable 0+R*32 */
 8491         vuint32_t CWEN14PRT32:1;         /* Channel Watchdog Enable 0+R*32 */
 8492         vuint32_t CWEN13PRT32:1;         /* Channel Watchdog Enable 0+R*32 */
 8493         vuint32_t CWEN12PRT32:1;         /* Channel Watchdog Enable 0+R*32 */
 8494         vuint32_t CWEN11PRT32:1;         /* Channel Watchdog Enable 0+R*32 */
 8495         vuint32_t CWEN10PRT32:1;         /* Channel Watchdog Enable 0+R*32 */
 8496         vuint32_t CWEN09PRT32:1;         /* Channel Watchdog Enable 0+R*32 */
 8497         vuint32_t CWEN08PRT32:1;         /* Channel Watchdog Enable 0+R*32 */
 8498         vuint32_t CWEN07PRT32:1;         /* Channel Watchdog Enable 0+R*32 */
 8499         vuint32_t CWEN06PRT32:1;         /* Channel Watchdog Enable 0+R*32 */
 8500         vuint32_t CWEN05PRT32:1;         /* Channel Watchdog Enable 0+R*32 */
 8501         vuint32_t CWEN04PRT32:1;         /* Channel Watchdog Enable 0+R*32 */
 8502         vuint32_t CWEN03PRT32:1;         /* Channel Watchdog Enable 0+R*32 */
 8503         vuint32_t CWEN02PRT32:1;         /* Channel Watchdog Enable 0+R*32 */
 8504         vuint32_t CWEN01PRT32:1;         /* Channel Watchdog Enable 0+R*32 */
 8505         vuint32_t CWEN00PRT32:1;         /* Channel Watchdog Enable 0+R*32 */
 8506       } B;
 8507     } ADC_CWENR_32B_tag;
 8508   
 8509     /* Register layout for all registers AWORR ... */
 8510     typedef union {                      /* Analog Watchdog Out of Range Register */
 8511       vuint32_t R;
 8512       struct {
 8513         vuint32_t AWOR_CH31:1;           /* Channel 31+R*32 converted data out of range */
 8514         vuint32_t AWOR_CH30:1;           /* Channel 30+R*32 converted data out of range */
 8515         vuint32_t AWOR_CH29:1;           /* Channel 29+R*32 converted data out of range */
 8516         vuint32_t AWOR_CH28:1;           /* Channel 28+R*32 converted data out of range */
 8517         vuint32_t AWOR_CH27:1;           /* Channel 27+R*32 converted data out of range */
 8518         vuint32_t AWOR_CH26:1;           /* Channel 26+R*32 converted data out of range */
 8519         vuint32_t AWOR_CH25:1;           /* Channel 25+R*32 converted data out of range */
 8520         vuint32_t AWOR_CH24:1;           /* Channel 24+R*32 converted data out of range */
 8521         vuint32_t AWOR_CH23:1;           /* Channel 23+R*32 converted data out of range */
 8522         vuint32_t AWOR_CH22:1;           /* Channel 22+R*32 converted data out of range */
 8523         vuint32_t AWOR_CH21:1;           /* Channel 21+R*32 converted data out of range */
 8524         vuint32_t AWOR_CH20:1;           /* Channel 20+R*32 converted data out of range */
 8525         vuint32_t AWOR_CH19:1;           /* Channel 19+R*32 converted data out of range */
 8526         vuint32_t AWOR_CH18:1;           /* Channel 18+R*32 converted data out of range */
 8527         vuint32_t AWOR_CH17:1;           /* Channel 17+R*32 converted data out of range */
 8528         vuint32_t AWOR_CH16:1;           /* Channel 16+R*32 converted data out of range */
 8529         vuint32_t AWOR_CH15:1;           /* Channel 15+R*32 converted data out of range */
 8530         vuint32_t AWOR_CH14:1;           /* Channel 14+R*32 converted data out of range */
 8531         vuint32_t AWOR_CH13:1;           /* Channel 13+R*32 converted data out of range */
 8532         vuint32_t AWOR_CH12:1;           /* Channel 12+R*32 converted data out of range */
 8533         vuint32_t AWOR_CH11:1;           /* Channel 11+R*32 converted data out of range */
 8534         vuint32_t AWOR_CH10:1;           /* Channel 10+R*32 converted data out of range */
 8535         vuint32_t AWOR_CH9:1;            /* Channel 9+R*32 converted data out of range */
 8536         vuint32_t AWOR_CH8:1;            /* Channel 8+R*32 converted data out of range */
 8537         vuint32_t AWOR_CH7:1;            /* Channel 7+R*32 converted data out of range */
 8538         vuint32_t AWOR_CH6:1;            /* Channel 6+R*32 converted data out of range */
 8539         vuint32_t AWOR_CH5:1;            /* Channel 5+R*32 converted data out of range */
 8540         vuint32_t AWOR_CH4:1;            /* Channel 4+R*32 converted data out of range */
 8541         vuint32_t AWOR_CH3:1;            /* Channel 3+R*32 converted data out of range */
 8542         vuint32_t AWOR_CH2:1;            /* Channel 2+R*32 converted data out of range */
 8543         vuint32_t AWOR_CH1:1;            /* Channel 1+R*32 converted data out of range */
 8544         vuint32_t AWOR_CH0:1;            /* Channel 0+R*32 converted data out of range */
 8545       } B;
 8546     } ADC_AWORR_32B_tag;
 8547   
 8548     typedef union {                      /* SELF TEST CONFIGURATION REGISTER 1 */
 8549       vuint32_t R;
 8550       struct {
 8551         vuint32_t INPSAMP_C:8;           /* Sampling phase duration for the test conversions - algorithm C */
 8552         vuint32_t INPSAMP_RC:8;          /* Sampling phase duration for the test conversions - algorithm RC */
 8553         vuint32_t INPSAMP_S:8;           /* Sampling phase duration for the test conversions - algorithm S */
 8554        vuint32_t:
 8555         5;
 8556         vuint32_t ST_INPCMP:2;           /* Configuration bit for comparison phase duration for self test channel */
 8557         vuint32_t ST_INPLATCH:1;         /* Configuration bit for Latching phase duration for self test channel */
 8558       } B;
 8559     } ADC_STCR1_32B_tag;
 8560   
 8561     typedef union {                      /* SELF TEST CONFIGURATION REGISTER 2 */
 8562       vuint32_t R;
 8563       struct {
 8564        vuint32_t:
 8565         5;
 8566         vuint32_t SERR:1;                /* Error fault injection bit (write only) */
 8567         vuint32_t MSKSTWDTERR:1;         /* Interrupt enable (STSR2.WDTERR status bit) */
 8568        vuint32_t:
 8569         1;
 8570         vuint32_t MSKST_EOC:1;           /* Interrupt enable bit for STSR2.ST_EOC */
 8571        vuint32_t:
 8572         4;
 8573         vuint32_t MSKWDG_EOA_C:1;        /* Interrupt enable (WDG_EOA_C status bit) */
 8574         vuint32_t MSKWDG_EOA_RC:1;       /* Interrupt enable (WDG_EOA_RC status bit) */
 8575         vuint32_t MSKWDG_EOA_S:1;        /* Interrupt enable (WDG_EOA_S status bit) */
 8576         vuint32_t MSKERR_C:1;            /* Interrupt enable (ERR_C status bit) */
 8577         vuint32_t MSKERR_RC:1;           /* Interrupt enable (ERR_RC status bit) */
 8578         vuint32_t MSKERR_S2:1;           /* Interrupt enable (ERR_S2 status bit) */
 8579         vuint32_t MSKERR_S1:1;           /* Interrupt enable (ERR_S1 status bit) */
 8580         vuint32_t MSKERR_S0:1;           /* Interrupt enable (ERR_S0 status bit) */
 8581        vuint32_t:
 8582         3;
 8583         vuint32_t EN:1;                  /* Self testing channel enable */
 8584        vuint32_t:
 8585         4;
 8586         vuint32_t FMA_C:1;               /* Fault mapping for the algorithm C */
 8587         vuint32_t FMAR_C:1;              /* Fault mapping for the algorithm RC */
 8588         vuint32_t FMA_S:1;               /* Fault mapping for the algorithm BGAP */
 8589       } B;
 8590     } ADC_STCR2_32B_tag;
 8591   
 8592     typedef union {                      /* SELF TEST CONFIGURATION REGISTER 3 */
 8593       vuint32_t R;
 8594       struct {
 8595        vuint32_t:
 8596         22;
 8597         vuint32_t ALG:2;                 /* Algorithm scheduling */
 8598        vuint32_t:
 8599         8;
 8600       } B;
 8601     } ADC_STCR3_32B_tag;
 8602   
 8603     typedef union {                      /* SELF TEST BAUD RATE REGISTER */
 8604       vuint32_t R;
 8605       struct {
 8606        vuint32_t:
 8607         13;
 8608         vuint32_t WDT:3;                 /* Watchdog timer value */
 8609        vuint32_t:
 8610         8;
 8611         vuint32_t BR:8;                  /* Baud rate for the selected algorithm in SCAN mode */
 8612       } B;
 8613     } ADC_STBRR_32B_tag;
 8614   
 8615     typedef union {                      /* SELF TEST STATUS REGISTER 1 */
 8616       vuint32_t R;
 8617       struct {
 8618        vuint32_t:
 8619         6;
 8620         vuint32_t WDTERR:1;              /* Watchdog timer error */
 8621         vuint32_t OVERWR:1;              /* Overwrite error */
 8622         vuint32_t ST_EOC:1;              /* Self test EOC bit */
 8623        vuint32_t:
 8624         4;
 8625         vuint32_t WDG_EOA_C:1;           /* Algorithm  C completed without error */
 8626         vuint32_t WDG_EOA_RC:1;          /* Algorithm RC completed without error */
 8627         vuint32_t WDG_EOA_S:1;           /* Algorithm  S completed without error */
 8628         vuint32_t ERR_C:1;               /* Error on the self testing channel (algorithm  C) */
 8629         vuint32_t ERR_RC:1;              /* Error on the self testing channel (algorithm RC) */
 8630         vuint32_t ERR_S2:1;              /* Error on the self testing channel (algorithm SUPPLY, step 2) */
 8631         vuint32_t ERR_S1:1;              /* Error on the self testing channel (algorithm SUPPLY, step 1) */
 8632         vuint32_t ERR_S0:1;              /* Error on the self testing channel (algorithm SUPPLY, step 0) */
 8633        vuint32_t:
 8634         1;
 8635         vuint32_t STEP_C:5;              /* Step of algorithm  C when ERR_C  has occurred */
 8636         vuint32_t STEP_RC:5;             /* Step of algorithm RC when ERR_RC has occurred */
 8637       } B;
 8638     } ADC_STSR1_32B_tag;
 8639   
 8640     typedef union {                      /* SELF TEST STATUS REGISTER 2 */
 8641       vuint32_t R;
 8642       struct {
 8643         vuint32_t OVFL:1;                /* Overflow bit */
 8644        vuint32_t:
 8645         3;
 8646         vuint32_t DATA1:12;              /* Test channel converted data when ERR_S1 has occurred */
 8647        vuint32_t:
 8648         4;
 8649         vuint32_t DATA0:12;              /* Test channel converted data when ERR_S1 has occurred */
 8650       } B;
 8651     } ADC_STSR2_32B_tag;
 8652   
 8653     typedef union {                      /* SELF TEST STATUS REGISTER 3 */
 8654       vuint32_t R;
 8655       struct {
 8656        vuint32_t:
 8657         4;
 8658         vuint32_t DATA1:12;              /* Test channel converted data when ERR_S0 has occurred */
 8659        vuint32_t:
 8660         4;
 8661         vuint32_t DATA0:12;              /* Test channel converted data when ERR_S0 has occurred */
 8662       } B;
 8663     } ADC_STSR3_32B_tag;
 8664   
 8665     typedef union {                      /* SELF TEST STATUS REGISTER 4 */
 8666       vuint32_t R;
 8667       struct {
 8668        vuint32_t:
 8669         4;
 8670         vuint32_t DATA1:12;              /* Test channel converted data when ERR_C has occurred */
 8671        vuint32_t:
 8672         4;
 8673         vuint32_t DATA0:12;              /* Test channel converted data when ERR_C has occurred */
 8674       } B;
 8675     } ADC_STSR4_32B_tag;
 8676   
 8677     typedef union {                      /* SELF TEST DATA REGISTER 1 */
 8678       vuint32_t R;
 8679       struct {
 8680        vuint32_t:
 8681         12;
 8682         vuint32_t VALID:1;               /* Valid data */
 8683         vuint32_t OVERWR:1;              /* Overwrite data */
 8684        vuint32_t:
 8685         6;
 8686         vuint32_t TCDATA:12;             /* Test channel converted data */
 8687       } B;
 8688     } ADC_STDR1_32B_tag;
 8689   
 8690     typedef union {                      /* SELF TEST DATA REGISTER 2 */
 8691       vuint32_t R;
 8692       struct {
 8693         vuint32_t FDATA:12;              /* Fractional part of the ratio TEST for algorithm S */
 8694         vuint32_t VALID:1;               /* Valid data */
 8695         vuint32_t OVERWR:1;              /* Overwrite data */
 8696        vuint32_t:
 8697         6;
 8698         vuint32_t IDATA:12;              /* Integer part of the ratio TEST for algorithm S */
 8699       } B;
 8700     } ADC_STDR2_32B_tag;
 8701   
 8702     typedef union {                      /* SELF TEST ANALOG WATCHDOG REGISTER 0 */
 8703       vuint32_t R;
 8704       struct {
 8705         vuint32_t AWDE:1;                /* Analog WatchDog Enable - algorithm S */
 8706         vuint32_t WDTE:1;                /* WatchDog Timer Enable - algorithm S */
 8707        vuint32_t:
 8708         2;
 8709         vuint32_t THRH:12;               /* High threshold value for channel 0 */
 8710        vuint32_t:
 8711         4;
 8712         vuint32_t THRL:12;               /* Low threshold value for channel 0 */
 8713       } B;
 8714     } ADC_STAW0R_32B_tag;
 8715   
 8716     typedef union {                      /* SELF TEST ANALOG WATCHDOG REGISTER 1A */
 8717       vuint32_t R;
 8718       struct {
 8719         vuint32_t AWDE:1;                /* Analog WatchDog Enable - algorithm S */
 8720        vuint32_t:
 8721         3;
 8722         vuint32_t THRH:12;               /* High threshold value for test channel - algorithm S */
 8723        vuint32_t:
 8724         4;
 8725         vuint32_t THRL:12;               /* Low threshold value for test channel - algorithm S */
 8726       } B;
 8727     } ADC_STAW1AR_32B_tag;
 8728   
 8729     typedef union {                      /* SELF TEST ANALOG WATCHDOG REGISTER 1B */
 8730       vuint32_t R;
 8731       struct {
 8732        vuint32_t:
 8733         4;
 8734         vuint32_t THRH:12;               /* High threshold value for test channel - algorithm S */
 8735        vuint32_t:
 8736         4;
 8737         vuint32_t THRL:12;               /* Low threshold value for test channel - algorithm S */
 8738       } B;
 8739     } ADC_STAW1BR_32B_tag;
 8740   
 8741     typedef union {                      /* SELF TEST ANALOG WATCHDOG REGISTER 2 */
 8742       vuint32_t R;
 8743       struct {
 8744         vuint32_t AWDE:1;                /* Analog WatchDog Enable - algorithm S */
 8745        vuint32_t:
 8746         19;
 8747         vuint32_t THRL:12;               /* Low threshold value for channel */
 8748       } B;
 8749     } ADC_STAW2R_32B_tag;
 8750   
 8751     typedef union {                      /* SELF TEST ANALOG WATCHDOG REGISTER 3 */
 8752       vuint32_t R;
 8753       struct {
 8754         vuint32_t AWDE:1;                /* Analog WatchDog Enable - algorithm RC */
 8755         vuint32_t WDTE:1;                /* WatchDog Timer Enable - algorithm RC */
 8756        vuint32_t:
 8757         2;
 8758         vuint32_t THRH:12;               /* High threshold value for channel 3 */
 8759        vuint32_t:
 8760         4;
 8761         vuint32_t THRL:12;               /* Low threshold value for channel 3 */
 8762       } B;
 8763     } ADC_STAW3R_32B_tag;
 8764   
 8765     typedef union {                      /* SELF TEST ANALOG WATCHDOG REGISTER 4 */
 8766       vuint32_t R;
 8767       struct {
 8768         vuint32_t AWDE:1;                /* Analog WatchDog Enable - algorithm C */
 8769         vuint32_t WDTE:1;                /* WatchDog Timer Enable - algorithm C */
 8770        vuint32_t:
 8771         2;
 8772         vuint32_t THRH:12;               /* High threshold value for channel 4 */
 8773        vuint32_t:
 8774         4;
 8775         vuint32_t THRL:12;               /* Low threshold value for channel 4 */
 8776       } B;
 8777     } ADC_STAW4R_32B_tag;
 8778   
 8779     typedef union {                      /* SELF TEST ANALOG WATCHDOG REGISTER 5 */
 8780       vuint32_t R;
 8781       struct {
 8782        vuint32_t:
 8783         4;
 8784         vuint32_t THRH:12;               /* High threshold value for algorithm C */
 8785        vuint32_t:
 8786         4;
 8787         vuint32_t THRL:12;               /* Low threshold value for algorithm C */
 8788       } B;
 8789     } ADC_STAW5R_32B_tag;
 8790   
 8791     typedef struct ADC_struct_tag {
 8792       /* module configuration register */
 8793       ADC_MCR_32B_tag MCR;               /* offset: 0x0000 size: 32 bit */
 8794   
 8795       /* module status register */
 8796       ADC_MSR_32B_tag MSR;               /* offset: 0x0004 size: 32 bit */
 8797       int8_t ADC_reserved_0008[8];
 8798   
 8799       /* Interrupt status register */
 8800       ADC_ISR_32B_tag ISR;               /* offset: 0x0010 size: 32 bit */
 8801       union {
 8802         ADC_CEOCFR0_32B_tag CEOCFR[3];   /* offset: 0x0014  (0x0004 x 3) */
 8803         struct {
 8804           /* CHANNEL PENDING REGISTER 0 */
 8805           ADC_CEOCFR0_32B_tag CEOCFR0;   /* offset: 0x0014 size: 32 bit */
 8806   
 8807           /* CHANNEL PENDING REGISTER 1 */
 8808           ADC_CEOCFR1_32B_tag CEOCFR1;   /* offset: 0x0018 size: 32 bit */
 8809   
 8810           /* CHANNEL PENDING REGISTER 2 */
 8811           ADC_CEOCFR2_32B_tag CEOCFR2;   /* offset: 0x001C size: 32 bit */
 8812         };
 8813       };
 8814   
 8815       /* interrupt mask register */
 8816       ADC_IMR_32B_tag IMR;               /* offset: 0x0020 size: 32 bit */
 8817       union {
 8818         ADC_CIMR0_32B_tag CIMR[3];       /* offset: 0x0024  (0x0004 x 3) */
 8819         struct {
 8820           /* CHANNEL INTERRUPT MASK REGISTER 0 */
 8821           ADC_CIMR0_32B_tag CIMR0;       /* offset: 0x0024 size: 32 bit */
 8822   
 8823           /* CHANNEL INTERRUPT MASK REGISTER 1 */
 8824           ADC_CIMR1_32B_tag CIMR1;       /* offset: 0x0028 size: 32 bit */
 8825   
 8826           /* CHANNEL INTERRUPT MASK REGISTER 2 */
 8827           ADC_CIMR2_32B_tag CIMR2;       /* offset: 0x002C size: 32 bit */
 8828         };
 8829       };
 8830   
 8831       /* Watchdog Threshold interrupt status register */
 8832       ADC_WTISR_32B_tag WTISR;           /* offset: 0x0030 size: 32 bit */
 8833   
 8834       /* Watchdog interrupt MASK register */
 8835       ADC_WTIMR_32B_tag WTIMR;           /* offset: 0x0034 size: 32 bit */
 8836       int8_t ADC_reserved_0038[8];
 8837   
 8838       /* DMAE register */
 8839       ADC_DMAE_32B_tag DMAE;             /* offset: 0x0040 size: 32 bit */
 8840       union {
 8841         ADC_DMAR0_32B_tag DMAR[3];       /* offset: 0x0044  (0x0004 x 3) */
 8842         struct {
 8843           /* DMA  REGISTER 0 */
 8844           ADC_DMAR0_32B_tag DMAR0;       /* offset: 0x0044 size: 32 bit */
 8845   
 8846           /* DMA REGISTER 1 */
 8847           ADC_DMAR1_32B_tag DMAR1;       /* offset: 0x0048 size: 32 bit */
 8848   
 8849           /* DMA REGISTER 2 */
 8850           ADC_DMAR2_32B_tag DMAR2;       /* offset: 0x004C size: 32 bit */
 8851         };
 8852       };
 8853   
 8854       union {
 8855         /* Threshold Control register C */
 8856         ADC_TRC_32B_tag TRC[4];          /* offset: 0x0050  (0x0004 x 4) */
 8857         struct {
 8858           /* Threshold Control register C */
 8859           ADC_TRC_32B_tag TRC0;          /* offset: 0x0050 size: 32 bit */
 8860           ADC_TRC_32B_tag TRC1;          /* offset: 0x0054 size: 32 bit */
 8861           ADC_TRC_32B_tag TRC2;          /* offset: 0x0058 size: 32 bit */
 8862           ADC_TRC_32B_tag TRC3;          /* offset: 0x005C size: 32 bit */
 8863         };
 8864       };
 8865   
 8866       union {
 8867         /* Upper Threshold register */
 8868         ADC_THRHLR_32B_tag THRHLR[4];    /* offset: 0x0060  (0x0004 x 4) */
 8869         struct {
 8870           /* Upper Threshold register */
 8871           ADC_THRHLR_32B_tag THRHLR0;    /* offset: 0x0060 size: 32 bit */
 8872           ADC_THRHLR_32B_tag THRHLR1;    /* offset: 0x0064 size: 32 bit */
 8873           ADC_THRHLR_32B_tag THRHLR2;    /* offset: 0x0068 size: 32 bit */
 8874           ADC_THRHLR_32B_tag THRHLR3;    /* offset: 0x006C size: 32 bit */
 8875         };
 8876       };
 8877   
 8878       union {
 8879         /* alternate Upper Threshold register */
 8880         ADC_THRALT_32B_tag THRALT[4];    /* offset: 0x0070  (0x0004 x 4) */
 8881         struct {
 8882           /* alternate Upper Threshold register */
 8883           ADC_THRALT_32B_tag THRALT0;    /* offset: 0x0070 size: 32 bit */
 8884           ADC_THRALT_32B_tag THRALT1;    /* offset: 0x0074 size: 32 bit */
 8885           ADC_THRALT_32B_tag THRALT2;    /* offset: 0x0078 size: 32 bit */
 8886           ADC_THRALT_32B_tag THRALT3;    /* offset: 0x007C size: 32 bit */
 8887         };
 8888       };
 8889   
 8890       /* PRESAMPLING CONTROL REGISTER */
 8891       ADC_PSCR_32B_tag PSCR;             /* offset: 0x0080 size: 32 bit */
 8892       union {
 8893         ADC_PSR0_32B_tag PSR[3];         /* offset: 0x0084  (0x0004 x 3) */
 8894         struct {
 8895           /* Presampling  Register 0 */
 8896           ADC_PSR0_32B_tag PSR0;         /* offset: 0x0084 size: 32 bit */
 8897   
 8898           /* Presampling REGISTER 1 */
 8899           ADC_PSR1_32B_tag PSR1;         /* offset: 0x0088 size: 32 bit */
 8900   
 8901           /* Presampling REGISTER 2 */
 8902           ADC_PSR2_32B_tag PSR2;         /* offset: 0x008C size: 32 bit */
 8903         };
 8904       };
 8905   
 8906       int8_t ADC_reserved_0090[4];
 8907       union {
 8908         /* conversion timing register */
 8909         ADC_CTR_32B_tag CTR[3];          /* offset: 0x0094  (0x0004 x 3) */
 8910         struct {
 8911           /* conversion timing register */
 8912           ADC_CTR_32B_tag CTR0;          /* offset: 0x0094 size: 32 bit */
 8913           ADC_CTR1_32B_tag CTR1;         /* offset: 0x0098 size: 32 bit */
 8914           ADC_CTR_32B_tag CTR2;          /* offset: 0x009C size: 32 bit */
 8915         };
 8916       };
 8917   
 8918       int8_t ADC_reserved_00A0[4];
 8919       union {
 8920         ADC_NCMR0_32B_tag NCMR[3];       /* offset: 0x00A4  (0x0004 x 3) */
 8921         struct {
 8922           /* NORMAL CONVERSION MASK REGISTER 0 */
 8923           ADC_NCMR0_32B_tag NCMR0;       /* offset: 0x00A4 size: 32 bit */
 8924   
 8925           /* NORMAL CONVERSION MASK REGISTER 1 */
 8926           ADC_NCMR1_32B_tag NCMR1;       /* offset: 0x00A8 size: 32 bit */
 8927   
 8928           /* NORMAL CONVERSION MASK REGISTER 2 */
 8929           ADC_NCMR2_32B_tag NCMR2;       /* offset: 0x00AC size: 32 bit */
 8930         };
 8931       };
 8932   
 8933       int8_t ADC_reserved_00B0[4];
 8934       union {
 8935         ADC_JCMR0_32B_tag JCMR[3];       /* offset: 0x00B4  (0x0004 x 3) */
 8936         struct {
 8937           /* Injected Conversion Mask Register 0 */
 8938           ADC_JCMR0_32B_tag JCMR0;       /* offset: 0x00B4 size: 32 bit */
 8939   
 8940           /* INJECTED CONVERSION MASK REGISTER 1 */
 8941           ADC_JCMR1_32B_tag JCMR1;       /* offset: 0x00B8 size: 32 bit */
 8942   
 8943           /* INJECTED CONVERSION MASK REGISTER 2 */
 8944           ADC_JCMR2_32B_tag JCMR2;       /* offset: 0x00BC size: 32 bit */
 8945         };
 8946       };
 8947   
 8948       /* Offset Word Regsiter */
 8949       ADC_OFFWR_32B_tag OFFWR;           /* offset: 0x00C0 size: 32 bit */
 8950   
 8951       /* Decode Signal Delay Register */
 8952       ADC_DSDR_32B_tag DSDR;             /* offset: 0x00C4 size: 32 bit */
 8953   
 8954       /* Power Down Dealy Register */
 8955       ADC_PDEDR_32B_tag PDEDR;           /* offset: 0x00C8 size: 32 bit */
 8956       int8_t ADC_reserved_00CC[52];
 8957       union {
 8958         /* CHANNEL DATA REGS */
 8959         ADC_CDR_32B_tag CDR[96];         /* offset: 0x0100  (0x0004 x 96) */
 8960         struct {
 8961           /* CHANNEL DATA REGS */
 8962           ADC_CDR_32B_tag CDR0;          /* offset: 0x0100 size: 32 bit */
 8963           ADC_CDR_32B_tag CDR1;          /* offset: 0x0104 size: 32 bit */
 8964           ADC_CDR_32B_tag CDR2;          /* offset: 0x0108 size: 32 bit */
 8965           ADC_CDR_32B_tag CDR3;          /* offset: 0x010C size: 32 bit */
 8966           ADC_CDR_32B_tag CDR4;          /* offset: 0x0110 size: 32 bit */
 8967           ADC_CDR_32B_tag CDR5;          /* offset: 0x0114 size: 32 bit */
 8968           ADC_CDR_32B_tag CDR6;          /* offset: 0x0118 size: 32 bit */
 8969           ADC_CDR_32B_tag CDR7;          /* offset: 0x011C size: 32 bit */
 8970           ADC_CDR_32B_tag CDR8;          /* offset: 0x0120 size: 32 bit */
 8971           ADC_CDR_32B_tag CDR9;          /* offset: 0x0124 size: 32 bit */
 8972           ADC_CDR_32B_tag CDR10;         /* offset: 0x0128 size: 32 bit */
 8973           ADC_CDR_32B_tag CDR11;         /* offset: 0x012C size: 32 bit */
 8974           ADC_CDR_32B_tag CDR12;         /* offset: 0x0130 size: 32 bit */
 8975           ADC_CDR_32B_tag CDR13;         /* offset: 0x0134 size: 32 bit */
 8976           ADC_CDR_32B_tag CDR14;         /* offset: 0x0138 size: 32 bit */
 8977           ADC_CDR_32B_tag CDR15;         /* offset: 0x013C size: 32 bit */
 8978           ADC_CDR_32B_tag CDR16;         /* offset: 0x0140 size: 32 bit */
 8979           ADC_CDR_32B_tag CDR17;         /* offset: 0x0144 size: 32 bit */
 8980           ADC_CDR_32B_tag CDR18;         /* offset: 0x0148 size: 32 bit */
 8981           ADC_CDR_32B_tag CDR19;         /* offset: 0x014C size: 32 bit */
 8982           ADC_CDR_32B_tag CDR20;         /* offset: 0x0150 size: 32 bit */
 8983           ADC_CDR_32B_tag CDR21;         /* offset: 0x0154 size: 32 bit */
 8984           ADC_CDR_32B_tag CDR22;         /* offset: 0x0158 size: 32 bit */
 8985           ADC_CDR_32B_tag CDR23;         /* offset: 0x015C size: 32 bit */
 8986           ADC_CDR_32B_tag CDR24;         /* offset: 0x0160 size: 32 bit */
 8987           ADC_CDR_32B_tag CDR25;         /* offset: 0x0164 size: 32 bit */
 8988           ADC_CDR_32B_tag CDR26;         /* offset: 0x0168 size: 32 bit */
 8989           ADC_CDR_32B_tag CDR27;         /* offset: 0x016C size: 32 bit */
 8990           ADC_CDR_32B_tag CDR28;         /* offset: 0x0170 size: 32 bit */
 8991           ADC_CDR_32B_tag CDR29;         /* offset: 0x0174 size: 32 bit */
 8992           ADC_CDR_32B_tag CDR30;         /* offset: 0x0178 size: 32 bit */
 8993           ADC_CDR_32B_tag CDR31;         /* offset: 0x017C size: 32 bit */
 8994           ADC_CDR_32B_tag CDR32;         /* offset: 0x0180 size: 32 bit */
 8995           ADC_CDR_32B_tag CDR33;         /* offset: 0x0184 size: 32 bit */
 8996           ADC_CDR_32B_tag CDR34;         /* offset: 0x0188 size: 32 bit */
 8997           ADC_CDR_32B_tag CDR35;         /* offset: 0x018C size: 32 bit */
 8998           ADC_CDR_32B_tag CDR36;         /* offset: 0x0190 size: 32 bit */
 8999           ADC_CDR_32B_tag CDR37;         /* offset: 0x0194 size: 32 bit */
 9000           ADC_CDR_32B_tag CDR38;         /* offset: 0x0198 size: 32 bit */
 9001           ADC_CDR_32B_tag CDR39;         /* offset: 0x019C size: 32 bit */
 9002           ADC_CDR_32B_tag CDR40;         /* offset: 0x01A0 size: 32 bit */
 9003           ADC_CDR_32B_tag CDR41;         /* offset: 0x01A4 size: 32 bit */
 9004           ADC_CDR_32B_tag CDR42;         /* offset: 0x01A8 size: 32 bit */
 9005           ADC_CDR_32B_tag CDR43;         /* offset: 0x01AC size: 32 bit */
 9006           ADC_CDR_32B_tag CDR44;         /* offset: 0x01B0 size: 32 bit */
 9007           ADC_CDR_32B_tag CDR45;         /* offset: 0x01B4 size: 32 bit */
 9008           ADC_CDR_32B_tag CDR46;         /* offset: 0x01B8 size: 32 bit */
 9009           ADC_CDR_32B_tag CDR47;         /* offset: 0x01BC size: 32 bit */
 9010           ADC_CDR_32B_tag CDR48;         /* offset: 0x01C0 size: 32 bit */
 9011           ADC_CDR_32B_tag CDR49;         /* offset: 0x01C4 size: 32 bit */
 9012           ADC_CDR_32B_tag CDR50;         /* offset: 0x01C8 size: 32 bit */
 9013           ADC_CDR_32B_tag CDR51;         /* offset: 0x01CC size: 32 bit */
 9014           ADC_CDR_32B_tag CDR52;         /* offset: 0x01D0 size: 32 bit */
 9015           ADC_CDR_32B_tag CDR53;         /* offset: 0x01D4 size: 32 bit */
 9016           ADC_CDR_32B_tag CDR54;         /* offset: 0x01D8 size: 32 bit */
 9017           ADC_CDR_32B_tag CDR55;         /* offset: 0x01DC size: 32 bit */
 9018           ADC_CDR_32B_tag CDR56;         /* offset: 0x01E0 size: 32 bit */
 9019           ADC_CDR_32B_tag CDR57;         /* offset: 0x01E4 size: 32 bit */
 9020           ADC_CDR_32B_tag CDR58;         /* offset: 0x01E8 size: 32 bit */
 9021           ADC_CDR_32B_tag CDR59;         /* offset: 0x01EC size: 32 bit */
 9022           ADC_CDR_32B_tag CDR60;         /* offset: 0x01F0 size: 32 bit */
 9023           ADC_CDR_32B_tag CDR61;         /* offset: 0x01F4 size: 32 bit */
 9024           ADC_CDR_32B_tag CDR62;         /* offset: 0x01F8 size: 32 bit */
 9025           ADC_CDR_32B_tag CDR63;         /* offset: 0x01FC size: 32 bit */
 9026           ADC_CDR_32B_tag CDR64;         /* offset: 0x0200 size: 32 bit */
 9027           ADC_CDR_32B_tag CDR65;         /* offset: 0x0204 size: 32 bit */
 9028           ADC_CDR_32B_tag CDR66;         /* offset: 0x0208 size: 32 bit */
 9029           ADC_CDR_32B_tag CDR67;         /* offset: 0x020C size: 32 bit */
 9030           ADC_CDR_32B_tag CDR68;         /* offset: 0x0210 size: 32 bit */
 9031           ADC_CDR_32B_tag CDR69;         /* offset: 0x0214 size: 32 bit */
 9032           ADC_CDR_32B_tag CDR70;         /* offset: 0x0218 size: 32 bit */
 9033           ADC_CDR_32B_tag CDR71;         /* offset: 0x021C size: 32 bit */
 9034           ADC_CDR_32B_tag CDR72;         /* offset: 0x0220 size: 32 bit */
 9035           ADC_CDR_32B_tag CDR73;         /* offset: 0x0224 size: 32 bit */
 9036           ADC_CDR_32B_tag CDR74;         /* offset: 0x0228 size: 32 bit */
 9037           ADC_CDR_32B_tag CDR75;         /* offset: 0x022C size: 32 bit */
 9038           ADC_CDR_32B_tag CDR76;         /* offset: 0x0230 size: 32 bit */
 9039           ADC_CDR_32B_tag CDR77;         /* offset: 0x0234 size: 32 bit */
 9040           ADC_CDR_32B_tag CDR78;         /* offset: 0x0238 size: 32 bit */
 9041           ADC_CDR_32B_tag CDR79;         /* offset: 0x023C size: 32 bit */
 9042           ADC_CDR_32B_tag CDR80;         /* offset: 0x0240 size: 32 bit */
 9043           ADC_CDR_32B_tag CDR81;         /* offset: 0x0244 size: 32 bit */
 9044           ADC_CDR_32B_tag CDR82;         /* offset: 0x0248 size: 32 bit */
 9045           ADC_CDR_32B_tag CDR83;         /* offset: 0x024C size: 32 bit */
 9046           ADC_CDR_32B_tag CDR84;         /* offset: 0x0250 size: 32 bit */
 9047           ADC_CDR_32B_tag CDR85;         /* offset: 0x0254 size: 32 bit */
 9048           ADC_CDR_32B_tag CDR86;         /* offset: 0x0258 size: 32 bit */
 9049           ADC_CDR_32B_tag CDR87;         /* offset: 0x025C size: 32 bit */
 9050           ADC_CDR_32B_tag CDR88;         /* offset: 0x0260 size: 32 bit */
 9051           ADC_CDR_32B_tag CDR89;         /* offset: 0x0264 size: 32 bit */
 9052           ADC_CDR_32B_tag CDR90;         /* offset: 0x0268 size: 32 bit */
 9053           ADC_CDR_32B_tag CDR91;         /* offset: 0x026C size: 32 bit */
 9054           ADC_CDR_32B_tag CDR92;         /* offset: 0x0270 size: 32 bit */
 9055           ADC_CDR_32B_tag CDR93;         /* offset: 0x0274 size: 32 bit */
 9056           ADC_CDR_32B_tag CDR94;         /* offset: 0x0278 size: 32 bit */
 9057           ADC_CDR_32B_tag CDR95;         /* offset: 0x027C size: 32 bit */
 9058         };
 9059       };
 9060   
 9061       /* Upper Threshold register 4 is not contiguous to 3 */
 9062       ADC_THRHLR4_32B_tag THRHLR4;       /* offset: 0x0280 size: 32 bit */
 9063   
 9064       /* Upper Threshold register 5 */
 9065       ADC_THRHLR5_32B_tag THRHLR5;       /* offset: 0x0284 size: 32 bit */
 9066   
 9067       /* Upper Threshold register 6 */
 9068       ADC_THRHLR6_32B_tag THRHLR6;       /* offset: 0x0288 size: 32 bit */
 9069   
 9070       /* Upper Threshold register 7 */
 9071       ADC_THRHLR7_32B_tag THRHLR7;       /* offset: 0x028C size: 32 bit */
 9072   
 9073       /* Upper Threshold register 8 */
 9074       ADC_THRHLR8_32B_tag THRHLR8;       /* offset: 0x0290 size: 32 bit */
 9075   
 9076       /* Upper Threshold register 9 */
 9077       ADC_THRHLR9_32B_tag THRHLR9;       /* offset: 0x0294 size: 32 bit */
 9078   
 9079       /* Upper Threshold register 10 */
 9080       ADC_THRHLR10_32B_tag THRHLR10;     /* offset: 0x0298 size: 32 bit */
 9081   
 9082       /* Upper Threshold register 11 */
 9083       ADC_THRHLR11_32B_tag THRHLR11;     /* offset: 0x029C size: 32 bit */
 9084   
 9085       /* Upper Threshold register 12 */
 9086       ADC_THRHLR12_32B_tag THRHLR12;     /* offset: 0x02A0 size: 32 bit */
 9087   
 9088       /* Upper Threshold register 13 */
 9089       ADC_THRHLR13_32B_tag THRHLR13;     /* offset: 0x02A4 size: 32 bit */
 9090   
 9091       /* Upper Threshold register 14 */
 9092       ADC_THRHLR14_32B_tag THRHLR14;     /* offset: 0x02A8 size: 32 bit */
 9093   
 9094       /* Upper Threshold register 15 */
 9095       ADC_THRHLR15_32B_tag THRHLR15;     /* offset: 0x02AC size: 32 bit */
 9096       union {
 9097         /* Channel Watchdog Select register */
 9098         ADC_CWSELR_32B_tag CWSELR[12];   /* offset: 0x02B0  (0x0004 x 12) */
 9099         struct {
 9100           /* Channel Watchdog Select register */
 9101           ADC_CWSELR_32B_tag CWSELR0;    /* offset: 0x02B0 size: 32 bit */
 9102           ADC_CWSELR_32B_tag CWSELR1;    /* offset: 0x02B4 size: 32 bit */
 9103           ADC_CWSELR_32B_tag CWSELR2;    /* offset: 0x02B8 size: 32 bit */
 9104           ADC_CWSELR_32B_tag CWSELR3;    /* offset: 0x02BC size: 32 bit */
 9105           ADC_CWSELR_32B_tag CWSELR4;    /* offset: 0x02C0 size: 32 bit */
 9106           ADC_CWSELR_32B_tag CWSELR5;    /* offset: 0x02C4 size: 32 bit */
 9107           ADC_CWSELR_32B_tag CWSELR6;    /* offset: 0x02C8 size: 32 bit */
 9108           ADC_CWSELR_32B_tag CWSELR7;    /* offset: 0x02CC size: 32 bit */
 9109           ADC_CWSELR_32B_tag CWSELR8;    /* offset: 0x02D0 size: 32 bit */
 9110           ADC_CWSELR_32B_tag CWSELR9;    /* offset: 0x02D4 size: 32 bit */
 9111           ADC_CWSELR_32B_tag CWSELR10;   /* offset: 0x02D8 size: 32 bit */
 9112           ADC_CWSELR_32B_tag CWSELR11;   /* offset: 0x02DC size: 32 bit */
 9113         };
 9114       };
 9115   
 9116       union {
 9117         /* Channel Watchdog Enable Register */
 9118         ADC_CWENR_32B_tag CWENR[3];      /* offset: 0x02E0  (0x0004 x 3) */
 9119         struct {
 9120           /* Channel Watchdog Enable Register */
 9121           ADC_CWENR_32B_tag CWENR0;      /* offset: 0x02E0 size: 32 bit */
 9122           ADC_CWENR_32B_tag CWENR1;      /* offset: 0x02E4 size: 32 bit */
 9123           ADC_CWENR_32B_tag CWENR2;      /* offset: 0x02E8 size: 32 bit */
 9124         };
 9125       };
 9126   
 9127       int8_t ADC_reserved_02EC[4];
 9128       union {
 9129         /* Analog Watchdog Out of Range Register */
 9130         ADC_AWORR_32B_tag AWORR[3];      /* offset: 0x02F0  (0x0004 x 3) */
 9131         struct {
 9132           /* Analog Watchdog Out of Range Register */
 9133           ADC_AWORR_32B_tag AWORR0;      /* offset: 0x02F0 size: 32 bit */
 9134           ADC_AWORR_32B_tag AWORR1;      /* offset: 0x02F4 size: 32 bit */
 9135           ADC_AWORR_32B_tag AWORR2;      /* offset: 0x02F8 size: 32 bit */
 9136         };
 9137       };
 9138   
 9139       int8_t ADC_reserved_02FC[68];
 9140   
 9141       /* SELF TEST CONFIGURATION REGISTER 1 */
 9142       ADC_STCR1_32B_tag STCR1;           /* offset: 0x0340 size: 32 bit */
 9143   
 9144       /* SELF TEST CONFIGURATION REGISTER 2 */
 9145       ADC_STCR2_32B_tag STCR2;           /* offset: 0x0344 size: 32 bit */
 9146   
 9147       /* SELF TEST CONFIGURATION REGISTER 3 */
 9148       ADC_STCR3_32B_tag STCR3;           /* offset: 0x0348 size: 32 bit */
 9149   
 9150       /* SELF TEST BAUD RATE REGISTER */
 9151       ADC_STBRR_32B_tag STBRR;           /* offset: 0x034C size: 32 bit */
 9152   
 9153       /* SELF TEST STATUS REGISTER 1 */
 9154       ADC_STSR1_32B_tag STSR1;           /* offset: 0x0350 size: 32 bit */
 9155   
 9156       /* SELF TEST STATUS REGISTER 2 */
 9157       ADC_STSR2_32B_tag STSR2;           /* offset: 0x0354 size: 32 bit */
 9158   
 9159       /* SELF TEST STATUS REGISTER 3 */
 9160       ADC_STSR3_32B_tag STSR3;           /* offset: 0x0358 size: 32 bit */
 9161   
 9162       /* SELF TEST STATUS REGISTER 4 */
 9163       ADC_STSR4_32B_tag STSR4;           /* offset: 0x035C size: 32 bit */
 9164       int8_t ADC_reserved_0360[16];
 9165   
 9166       /* SELF TEST DATA REGISTER 1 */
 9167       ADC_STDR1_32B_tag STDR1;           /* offset: 0x0370 size: 32 bit */
 9168   
 9169       /* SELF TEST DATA REGISTER 2 */
 9170       ADC_STDR2_32B_tag STDR2;           /* offset: 0x0374 size: 32 bit */
 9171       int8_t ADC_reserved_0378[8];
 9172   
 9173       /* SELF TEST ANALOG WATCHDOG REGISTER 0 */
 9174       ADC_STAW0R_32B_tag STAW0R;         /* offset: 0x0380 size: 32 bit */
 9175   
 9176       /* SELF TEST ANALOG WATCHDOG REGISTER 1A */
 9177       ADC_STAW1AR_32B_tag STAW1AR;       /* offset: 0x0384 size: 32 bit */
 9178   
 9179       /* SELF TEST ANALOG WATCHDOG REGISTER 1B */
 9180       ADC_STAW1BR_32B_tag STAW1BR;       /* offset: 0x0388 size: 32 bit */
 9181   
 9182       /* SELF TEST ANALOG WATCHDOG REGISTER 2 */
 9183       ADC_STAW2R_32B_tag STAW2R;         /* offset: 0x038C size: 32 bit */
 9184   
 9185       /* SELF TEST ANALOG WATCHDOG REGISTER 3 */
 9186       ADC_STAW3R_32B_tag STAW3R;         /* offset: 0x0390 size: 32 bit */
 9187   
 9188       /* SELF TEST ANALOG WATCHDOG REGISTER 4 */
 9189       ADC_STAW4R_32B_tag STAW4R;         /* offset: 0x0394 size: 32 bit */
 9190   
 9191       /* SELF TEST ANALOG WATCHDOG REGISTER 5 */
 9192       ADC_STAW5R_32B_tag STAW5R;         /* offset: 0x0398 size: 32 bit */
 9193       int8_t ADC_reserved_039C[15460];
 9194     } ADC_tag;
 9195   
 9196   #define ADC0                           (*(volatile ADC_tag *) 0xFFE00000UL)
 9197   #define ADC1                           (*(volatile ADC_tag *) 0xFFE04000UL)
 9198   
 9199     /****************************************************************/
 9200     /*                                                              */
 9201     /* Module: CTU  */
 9202     /*                                                              */
 9203     /****************************************************************/
 9204     typedef union {                      /* Trigger Generator Subunit Input Selection register */
 9205       vuint32_t R;
 9206       struct {
 9207         vuint32_t I15_FE:1;              /* ext_signal Falling Edge */
 9208         vuint32_t I15_RE:1;              /* ext_signal Rising  Edge */
 9209         vuint32_t I14_FE:1;              /* eTimer2 Falling Edge Enable */
 9210         vuint32_t I14_RE:1;              /* eTimer2 Rising  Edge Enable */
 9211         vuint32_t I13_FE:1;              /* eTimer1 Falling Edge Enable */
 9212         vuint32_t I13_RE:1;              /* eTimer1 Rising  Edge Enable */
 9213         vuint32_t I12_FE:1;              /* RPWM ch3 Falling Edge Enable */
 9214         vuint32_t I12_RE:1;              /* RPWM ch3 Rising  Edge Enable */
 9215         vuint32_t I11_FE:1;              /* RPWM ch2 Falling Edge Enable */
 9216         vuint32_t I11_RE:1;              /* RPWM ch2 Rising  Edge Enable */
 9217         vuint32_t I10_FE:1;              /* RPWM ch1 Falling Edge Enable */
 9218         vuint32_t I10_RE:1;              /* RPWM ch1 Rising  Edge Enable */
 9219         vuint32_t I9_FE:1;               /* RPWM ch0 Falling Edge Enable */
 9220         vuint32_t I9_RE:1;               /* RPWM ch0 Rising  Edge Enable */
 9221         vuint32_t I8_FE:1;               /* PWM ch3 even trig Falling edge Enable */
 9222         vuint32_t I8_RE:1;               /* PWM ch3 even trig Rising  edge Enable */
 9223         vuint32_t I7_FE:1;               /* PWM ch2 even trig Falling edge Enable */
 9224         vuint32_t I7_RE:1;               /* PWM ch2 even trig Rising  edge Enable */
 9225         vuint32_t I6_FE:1;               /* PWM ch1 even trig Falling edge Enable */
 9226         vuint32_t I6_RE:1;               /* PWM ch1 even trig Rising  edge Enable */
 9227         vuint32_t I5_FE:1;               /* PWM ch0 even trig Falling edge Enable */
 9228         vuint32_t I5_RE:1;               /* PWM ch0 even trig Rising edge Enable */
 9229         vuint32_t I4_FE:1;               /* PWM ch3 odd trig Falling edge Enable */
 9230         vuint32_t I4_RE:1;               /* PWM ch3 odd trig Rising  edge Enable */
 9231         vuint32_t I3_FE:1;               /* PWM ch2 odd trig Falling edge Enable */
 9232         vuint32_t I3_RE:1;               /* PWM ch2 odd trig Rising  edge Enable */
 9233         vuint32_t I2_FE:1;               /* PWM ch1 odd trig Falling edge Enable */
 9234         vuint32_t I2_RE:1;               /* PWM ch1 odd trig Rising  edge Enable */
 9235         vuint32_t I1_FE:1;               /* PWM ch0 odd trig Falling edge Enable */
 9236         vuint32_t I1_RE:1;               /* PWM ch0 odd trig Rising  edge Enable */
 9237         vuint32_t I0_FE:1;               /* PWM Reload Falling Edge Enable */
 9238         vuint32_t I0_RE:1;               /* PWM Reload Rising  Edge Enable */
 9239       } B;
 9240     } CTU_TGSISR_32B_tag;
 9241   
 9242     typedef union {                      /* Trigger Generator Subunit Control Register */
 9243       vuint16_t R;
 9244       struct {
 9245        vuint16_t:
 9246         7;
 9247   
 9248   #ifndef USE_FIELD_ALIASES_CTU
 9249   
 9250         vuint16_t ET_TM:1;               /* Toggle Mode Enable */
 9251   
 9252   #else
 9253   
 9254         vuint16_t ETTM:1;                /* deprecated name - please avoid */
 9255   
 9256   #endif
 9257   
 9258         vuint16_t PRES:2;                /* TGS Prescaler Selection */
 9259   
 9260   #ifndef USE_FIELD_ALIASES_CTU
 9261   
 9262         vuint16_t MRS_SM:5;              /* MRS Selection in Sequential Mode */
 9263   
 9264   #else
 9265   
 9266         vuint16_t MRSSM:5;               /* deprecated name - please avoid */
 9267   
 9268   #endif
 9269   
 9270   #ifndef USE_FIELD_ALIASES_CTU
 9271   
 9272         vuint16_t TGS_M:1;               /* Trigger Generator Subunit Mode */
 9273   
 9274   #else
 9275   
 9276         vuint16_t TGSM:1;                /* deprecated name - please avoid */
 9277   
 9278   #endif
 9279   
 9280       } B;
 9281     } CTU_TGSCR_16B_tag;
 9282   
 9283     typedef union {                      /*  */
 9284       vuint16_t R;
 9285     } CTU_TCR_16B_tag;
 9286   
 9287     typedef union {                      /* TGS Counter Compare Register */
 9288       vuint16_t R;
 9289   
 9290   #ifdef USE_FIELD_ALIASES_CTU
 9291   
 9292       struct {
 9293         vuint16_t TGSCCV:16;             /* deprecated field -- do not use */
 9294       } B;
 9295   
 9296   #endif
 9297   
 9298     } CTU_TGSCCR_16B_tag;
 9299   
 9300     typedef union {                      /* TGS Counter Reload Register */
 9301       vuint16_t R;
 9302   
 9303   #ifdef USE_FIELD_ALIASES_CTU
 9304   
 9305       struct {
 9306         vuint16_t TGSCRV:16;             /* deprecated field -- do not use */
 9307       } B;
 9308   
 9309   #endif
 9310   
 9311     } CTU_TGSCRR_16B_tag;
 9312   
 9313     typedef union {                      /* Commands List Control Register 1 */
 9314       vuint32_t R;
 9315       struct {
 9316        vuint32_t:
 9317         3;
 9318         vuint32_t T3INDEX:5;             /* Trigger 3 First Command address */
 9319        vuint32_t:
 9320         3;
 9321         vuint32_t T2INDEX:5;             /* Trigger 2 First Command address */
 9322        vuint32_t:
 9323         3;
 9324         vuint32_t T1INDEX:5;             /* Trigger 1 First Command address */
 9325        vuint32_t:
 9326         3;
 9327         vuint32_t T0INDEX:5;             /* Trigger 0 First Command address */
 9328       } B;
 9329     } CTU_CLCR1_32B_tag;
 9330   
 9331     typedef union {                      /* Commands List Control Register 2 */
 9332       vuint32_t R;
 9333       struct {
 9334        vuint32_t:
 9335         3;
 9336         vuint32_t T7INDEX:5;             /* Trigger 7 First Command address */
 9337        vuint32_t:
 9338         3;
 9339         vuint32_t T6INDEX:5;             /* Trigger 6 First Command address */
 9340        vuint32_t:
 9341         3;
 9342         vuint32_t T5INDEX:5;             /* Trigger 5 First Command address */
 9343        vuint32_t:
 9344         3;
 9345         vuint32_t T4INDEX:5;             /* Trigger 4 First Command address */
 9346       } B;
 9347     } CTU_CLCR2_32B_tag;
 9348   
 9349     typedef union {                      /* Trigger Handler Control Register 1 */
 9350       vuint32_t R;
 9351       struct {
 9352        vuint32_t:
 9353         1;
 9354         vuint32_t T3_E:1;                /* Trigger 3 enable */
 9355         vuint32_t T3_ETE:1;              /* Trigger 3 Ext Trigger output enable */
 9356         vuint32_t T3_T4E:1;              /* Trigger 3 Timer4 output enable */
 9357         vuint32_t T3_T3E:1;              /* Trigger 3 Timer3 output enable */
 9358         vuint32_t T3_T2E:1;              /* Trigger 3 Timer2 output enable */
 9359         vuint32_t T3_T1E:1;              /* Trigger 3 Timer1 output enable */
 9360         vuint32_t T3_ADCE:1;             /* Trigger 3 ADC Command output enable */
 9361        vuint32_t:
 9362         1;
 9363         vuint32_t T2_E:1;                /* Trigger 2 enable */
 9364         vuint32_t T2_ETE:1;              /* Trigger 2 Ext Trigger output enable */
 9365         vuint32_t T2_T4E:1;              /* Trigger 2 Timer4 output enable */
 9366         vuint32_t T2_T3E:1;              /* Trigger 2 Timer3 output enable */
 9367         vuint32_t T2_T2E:1;              /* Trigger 2 Timer2 output enable */
 9368         vuint32_t T2_T1E:1;              /* Trigger 2 Timer1 output enable */
 9369         vuint32_t T2_ADCE:1;             /* Trigger 2 ADC Command output enable */
 9370        vuint32_t:
 9371         1;
 9372         vuint32_t T1_E:1;                /* Trigger 1 enable */
 9373         vuint32_t T1_ETE:1;              /* Trigger 1 Ext Trigger output enable */
 9374         vuint32_t T1_T4E:1;              /* Trigger 1 Timer4 output enable */
 9375         vuint32_t T1_T3E:1;              /* Trigger 1 Timer3 output enable */
 9376         vuint32_t T1_T2E:1;              /* Trigger 1 Timer2 output enable */
 9377         vuint32_t T1_T1E:1;              /* Trigger 1 Timer1 output enable */
 9378         vuint32_t T1_ADCE:1;             /* Trigger 1 ADC Command output enable */
 9379        vuint32_t:
 9380         1;
 9381         vuint32_t T0_E:1;                /* Trigger 0 enable */
 9382         vuint32_t T0_ETE:1;              /* Trigger 0 Ext Trigger output enable */
 9383         vuint32_t T0_T4E:1;              /* Trigger 0 Timer4 output enable */
 9384         vuint32_t T0_T3E:1;              /* Trigger 0 Timer3 output enable */
 9385         vuint32_t T0_T2E:1;              /* Trigger 0 Timer2 output enable */
 9386         vuint32_t T0_T1E:1;              /* Trigger 0 Timer1 output enable */
 9387         vuint32_t T0_ADCE:1;             /* Trigger 0 ADC Command output enable */
 9388       } B;
 9389     } CTU_THCR1_32B_tag;
 9390   
 9391     typedef union {                      /* Trigger Handler Control Register 2 */
 9392       vuint32_t R;
 9393       struct {
 9394        vuint32_t:
 9395         1;
 9396         vuint32_t T7_E:1;                /* Trigger 7 enable */
 9397         vuint32_t T7_ETE:1;              /* Trigger 7 Ext Trigger output enable */
 9398         vuint32_t T7_T4E:1;              /* Trigger 7 Timer4 output enable */
 9399         vuint32_t T7_T3E:1;              /* Trigger 7 Timer3 output enable */
 9400         vuint32_t T7_T2E:1;              /* Trigger 7 Timer2 output enable */
 9401         vuint32_t T7_T1E:1;              /* Trigger 7 Timer1 output enable */
 9402         vuint32_t T7_ADCE:1;             /* Trigger 7 ADC Command output enable */
 9403        vuint32_t:
 9404         1;
 9405         vuint32_t T6_E:1;                /* Trigger 6 enable */
 9406         vuint32_t T6_ETE:1;              /* Trigger 6 Ext Trigger output enable */
 9407         vuint32_t T6_T4E:1;              /* Trigger 6 Timer4 output enable */
 9408         vuint32_t T6_T3E:1;              /* Trigger 6 Timer3 output enable */
 9409         vuint32_t T6_T2E:1;              /* Trigger 6 Timer2 output enable */
 9410         vuint32_t T6_T1E:1;              /* Trigger 6 Timer1 output enable */
 9411         vuint32_t T6_ADCE:1;             /* Trigger 6 ADC Command output enable */
 9412        vuint32_t:
 9413         1;
 9414         vuint32_t T5_E:1;                /* Trigger 5 enable */
 9415         vuint32_t T5_ETE:1;              /* Trigger 5 Ext Trigger output enable */
 9416         vuint32_t T5_T4E:1;              /* Trigger 5 Timer4 output enable */
 9417         vuint32_t T5_T3E:1;              /* Trigger 5 Timer3 output enable */
 9418         vuint32_t T5_T2E:1;              /* Trigger 5 Timer2 output enable */
 9419         vuint32_t T5_T1E:1;              /* Trigger 5 Timer1 output enable */
 9420         vuint32_t T5_ADCE:1;             /* Trigger 5 ADC Command output enable */
 9421        vuint32_t:
 9422         1;
 9423         vuint32_t T4_E:1;                /* Trigger 4 enable */
 9424         vuint32_t T4_ETE:1;              /* Trigger 4 Ext Trigger output enable */
 9425         vuint32_t T4_T4E:1;              /* Trigger 4 Timer4 output enable */
 9426         vuint32_t T4_T3E:1;              /* Trigger 4 Timer3 output enable */
 9427         vuint32_t T4_T2E:1;              /* Trigger 4 Timer2 output enable */
 9428         vuint32_t T4_T1E:1;              /* Trigger 4 Timer1 output enable */
 9429         vuint32_t T4_ADCE:1;             /* Trigger 4 ADC Command output enable */
 9430       } B;
 9431     } CTU_THCR2_32B_tag;
 9432   
 9433     /* Register layout for all registers CLR_DCM ... */
 9434     typedef union {                      /* Command List Register. View: (CMS=BIT13=)ST1 = 1, (BIT9=)ST0 = DONT CARE */
 9435       vuint16_t R;
 9436       struct {
 9437         vuint16_t CIR:1;                 /* Command Interrupt Request */
 9438         vuint16_t LC:1;                  /* Last Command */
 9439         vuint16_t CMS:1;                 /* Conversion Mode Selection */
 9440         vuint16_t FIFO:3;                /* FIFO for ADC A/B */
 9441        vuint16_t:
 9442         1;
 9443         vuint16_t CHB:4;                 /* ADC unit B channel number */
 9444        vuint16_t:
 9445         1;
 9446         vuint16_t CHA:4;                 /* ADC unit A channel number */
 9447       } B;
 9448     } CTU_CLR_DCM_16B_tag;
 9449   
 9450     /* Register layout for all registers CLR_SCM ... */
 9451     typedef union {                      /* Command List Register. View: (CMS=BIT13=)ST1 = 0, (BIT9=)ST0 = 0 */
 9452       vuint16_t R;
 9453       struct {
 9454         vuint16_t CIR:1;                 /* Command Interrupt Request */
 9455         vuint16_t LC:1;                  /* Last Command */
 9456         vuint16_t CMS:1;                 /* Conversion Mode Selection */
 9457         vuint16_t FIFO:3;                /* FIFO for ADC A/B */
 9458        vuint16_t:
 9459         4;
 9460         vuint16_t SU:1;                  /* Selection ADC Unit */
 9461        vuint16_t:
 9462         1;
 9463         vuint16_t CH:4;                  /* ADC unit channel number */
 9464       } B;
 9465     } CTU_CLR_SCM_16B_tag;
 9466   
 9467     /* Register layout for all registers CLR ... */
 9468     typedef union {                      /* Command List Register. View: BIT13, BIT9 */
 9469       vuint16_t R;
 9470       struct {
 9471        vuint16_t:
 9472         2;
 9473         vuint16_t ST1:1;                 /* Self test mode bit 1 */
 9474        vuint16_t:
 9475         3;
 9476         vuint16_t ST0:1;                 /* Self test mode bit 0 */
 9477        vuint16_t:
 9478         9;
 9479       } B;
 9480     } CTU_CLR_16B_tag;
 9481   
 9482     typedef union {                      /* Control Register */
 9483       vuint16_t R;
 9484       struct {
 9485         vuint16_t EMPTY_CLR7:1;          /* Empty Clear 7 */
 9486         vuint16_t EMPTY_CLR6:1;          /* Empty Clear 6 */
 9487         vuint16_t EMPTY_CLR5:1;          /* Empty Clear 5 */
 9488         vuint16_t EMPTY_CLR4:1;          /* Empty Clear 4 */
 9489         vuint16_t EMPTY_CLR3:1;          /* Empty Clear 3 */
 9490         vuint16_t EMPTY_CLR2:1;          /* Empty Clear 2 */
 9491         vuint16_t EMPTY_CLR1:1;          /* Empty Clear 1 */
 9492         vuint16_t EMPTY_CLR0:1;          /* Empty Clear 0 */
 9493   
 9494   #ifndef USE_FIELD_ALIASES_CTU
 9495   
 9496         vuint16_t DMA_EN7:1;             /* Enable DMA interface for FIFO 7 */
 9497   
 9498   #else
 9499   
 9500         vuint16_t DMAEN7:1;              /* deprecated name - please avoid */
 9501   
 9502   #endif
 9503   
 9504   #ifndef USE_FIELD_ALIASES_CTU
 9505   
 9506         vuint16_t DMA_EN6:1;             /* Enable DMA interface for FIFO 6 */
 9507   
 9508   #else
 9509   
 9510         vuint16_t DMAEN6:1;              /* deprecated name - please avoid */
 9511   
 9512   #endif
 9513   
 9514   #ifndef USE_FIELD_ALIASES_CTU
 9515   
 9516         vuint16_t DMA_EN5:1;             /* Enable DMA interface for FIFO 5 */
 9517   
 9518   #else
 9519   
 9520         vuint16_t DMAEN5:1;              /* deprecated name - please avoid */
 9521   
 9522   #endif
 9523   
 9524   #ifndef USE_FIELD_ALIASES_CTU
 9525   
 9526         vuint16_t DMA_EN4:1;             /* Enable DMA interface for FIFO 4 */
 9527   
 9528   #else
 9529   
 9530         vuint16_t DMAEN4:1;              /* deprecated name - please avoid */
 9531   
 9532   #endif
 9533   
 9534   #ifndef USE_FIELD_ALIASES_CTU
 9535   
 9536         vuint16_t DMA_EN3:1;             /* Enable DMA interface for FIFO 3 */
 9537   
 9538   #else
 9539   
 9540         vuint16_t DMAEN3:1;              /* deprecated name - please avoid */
 9541   
 9542   #endif
 9543   
 9544   #ifndef USE_FIELD_ALIASES_CTU
 9545   
 9546         vuint16_t DMA_EN2:1;             /* Enable DMA interface for FIFO 2 */
 9547   
 9548   #else
 9549   
 9550         vuint16_t DMAEN2:1;              /* deprecated name - please avoid */
 9551   
 9552   #endif
 9553   
 9554   #ifndef USE_FIELD_ALIASES_CTU
 9555   
 9556         vuint16_t DMA_EN1:1;             /* Enable DMA interface for FIFO 1 */
 9557   
 9558   #else
 9559   
 9560         vuint16_t DMAEN1:1;              /* deprecated name - please avoid */
 9561   
 9562   #endif
 9563   
 9564   #ifndef USE_FIELD_ALIASES_CTU
 9565   
 9566         vuint16_t DMA_EN0:1;             /* Enable DMA interface for FIFO 0 */
 9567   
 9568   #else
 9569   
 9570         vuint16_t DMAEN0:1;              /* deprecated name - please avoid */
 9571   
 9572   #endif
 9573   
 9574       } B;
 9575     } CTU_CR_16B_tag;
 9576   
 9577     typedef union {                      /* Control Register FIFO */
 9578       vuint32_t R;
 9579       struct {
 9580         vuint32_t FIFO_OVERRUN_EN7:1;    /* FIFO 7 OVERRUN  Enable Interrupt */
 9581         vuint32_t FIFO_OVERFLOW_EN7:1;   /* FIFO 7 OVERFLOW Enable Interrupt */
 9582         vuint32_t FIFO_EMPTY_EN7:1;      /* FIFO 7 EMPTY Enable Interrupt */
 9583         vuint32_t FIFO_FULL_EN7:1;       /* FIFO 7 FULL Enable Interrupt */
 9584         vuint32_t FIFO_OVERRUN_EN6:1;    /* FIFO 6 OVERRUN  Enable Interrupt */
 9585         vuint32_t FIFO_OVERFLOW_EN6:1;   /* FIFO 6 OVERFLOW Enable Interrupt */
 9586         vuint32_t FIFO_EMPTY_EN6:1;      /* FIFO 6 EMPTY Enable Interrupt */
 9587         vuint32_t FIFO_FULL_EN6:1;       /* FIFO 6 FULL Enable Interrupt */
 9588         vuint32_t FIFO_OVERRUN_EN5:1;    /* FIFO 5 OVERRUN  Enable Interrupt */
 9589         vuint32_t FIFO_OVERFLOW_EN5:1;   /* FIFO 5 OVERFLOW Enable Interrupt */
 9590         vuint32_t FIFO_EMPTY_EN5:1;      /* FIFO 5 EMPTY Enable Interrupt */
 9591         vuint32_t FIFO_FULL_EN5:1;       /* FIFO 5 FULL Enable Interrupt */
 9592         vuint32_t FIFO_OVERRUN_EN4:1;    /* FIFO 4 OVERRUN  Enable Interrupt */
 9593         vuint32_t FIFO_OVERFLOW_EN4:1;   /* FIFO 4 OVERFLOW Enable Interrupt */
 9594         vuint32_t FIFO_EMPTY_EN4:1;      /* FIFO 4 EMPTY Enable Interrupt */
 9595         vuint32_t FIFO_FULL_EN4:1;       /* FIFO 4 FULL Enable Interrupt */
 9596         vuint32_t FIFO_OVERRUN_EN3:1;    /* FIFO 3 OVERRUN  Enable Interrupt */
 9597         vuint32_t FIFO_OVERFLOW_EN3:1;   /* FIFO 3 OVERFLOW Enable Interrupt */
 9598         vuint32_t FIFO_EMPTY_EN3:1;      /* FIFO 3 EMPTY Enable Interrupt */
 9599         vuint32_t FIFO_FULL_EN3:1;       /* FIFO 3 FULL Enable Interrupt */
 9600         vuint32_t FIFO_OVERRUN_EN2:1;    /* FIFO 2 OVERRUN  Enable Interrupt */
 9601         vuint32_t FIFO_OVERFLOW_EN2:1;   /* FIFO 2 OVERFLOW Enable Interrupt */
 9602         vuint32_t FIFO_EMPTY_EN2:1;      /* FIFO 2 EMPTY Enable Interrupt */
 9603         vuint32_t FIFO_FULL_EN2:1;       /* FIFO 2 FULL Enable Interrupt */
 9604         vuint32_t FIFO_OVERRUN_EN1:1;    /* FIFO 1 OVERRUN  Enable Interrupt */
 9605         vuint32_t FIFO_OVERFLOW_EN1:1;   /* FIFO 1 OVERFLOW Enable Interrupt */
 9606         vuint32_t FIFO_EMPTY_EN1:1;      /* FIFO 1 EMPTY Enable Interrupt */
 9607         vuint32_t FIFO_FULL_EN1:1;       /* FIFO 1 FULL Enable Interrupt */
 9608         vuint32_t FIFO_OVERRUN_EN0:1;    /* FIFO 0 OVERRUN  Enable Interrupt */
 9609         vuint32_t FIFO_OVERFLOW_EN0:1;   /* FIFO 0 OVERFLOW Enable Interrupt */
 9610         vuint32_t FIFO_EMPTY_EN0:1;      /* FIFO 0 EMPTY Enable Interrupt */
 9611         vuint32_t FIFO_FULL_EN0:1;       /* FIFO 0 FULL Enable Interrupt */
 9612       } B;
 9613     } CTU_FCR_32B_tag;
 9614   
 9615     typedef union {                      /* Threshold 1 Register */
 9616       vuint32_t R;
 9617       struct {
 9618         vuint32_t THRESHOLD3:8;          /* Threshold FIFO 3 */
 9619         vuint32_t THRESHOLD2:8;          /* Threshold FIFO 2 */
 9620         vuint32_t THRESHOLD1:8;          /* Threshold FIFO 1 */
 9621         vuint32_t THRESHOLD0:8;          /* Threshold FIFO 0 */
 9622       } B;
 9623     } CTU_TH1_32B_tag;
 9624   
 9625     typedef union {                      /* Threshold 2 Register */
 9626       vuint32_t R;
 9627       struct {
 9628         vuint32_t THRESHOLD7:8;          /* Threshold FIFO 7 */
 9629         vuint32_t THRESHOLD6:8;          /* Threshold FIFO 6 */
 9630         vuint32_t THRESHOLD5:8;          /* Threshold FIFO 5 */
 9631         vuint32_t THRESHOLD4:8;          /* Threshold FIFO 4 */
 9632       } B;
 9633     } CTU_TH2_32B_tag;
 9634   
 9635     typedef union {                      /* Status Register */
 9636       vuint32_t R;
 9637       struct {
 9638         vuint32_t FIFO_OVERRUN7:1;       /* FIFO 7 OVERRUN  Flag */
 9639         vuint32_t FIFO_OVERFLOW7:1;      /* FIFO 7 OVERFLOW Flag */
 9640         vuint32_t FIFO_EMPTY7:1;         /* FIFO 7 EMPTY Flag */
 9641         vuint32_t FIFO_FULL7:1;          /* FIFO 7 FULL Flag */
 9642         vuint32_t FIFO_OVERRUN6:1;       /* FIFO 6 OVERRUN  Flag */
 9643         vuint32_t FIFO_OVERFLOW6:1;      /* FIFO 6 OVERFLOW Flag */
 9644         vuint32_t FIFO_EMPTY6:1;         /* FIFO 6 EMPTY Flag */
 9645         vuint32_t FIFO_FULL6:1;          /* FIFO 6 FULL Flag */
 9646         vuint32_t FIFO_OVERRUN5:1;       /* FIFO 5 OVERRUN  Flag */
 9647         vuint32_t FIFO_OVERFLOW5:1;      /* FIFO 5 OVERFLOW Flag */
 9648         vuint32_t FIFO_EMPTY5:1;         /* FIFO 5 EMPTY Flag */
 9649         vuint32_t FIFO_FULL5:1;          /* FIFO 5 FULL Flag */
 9650         vuint32_t FIFO_OVERRUN4:1;       /* FIFO 4 OVERRUN  Flag */
 9651         vuint32_t FIFO_OVERFLOW4:1;      /* FIFO 4 OVERFLOW Flag */
 9652         vuint32_t FIFO_EMPTY4:1;         /* FIFO 4 EMPTY Flag */
 9653         vuint32_t FIFO_FULL4:1;          /* FIFO 4 FULL Flag */
 9654         vuint32_t FIFO_OVERRUN3:1;       /* FIFO 3 OVERRUN  Flag */
 9655         vuint32_t FIFO_OVERFLOW3:1;      /* FIFO 3 OVERFLOW Flag */
 9656         vuint32_t FIFO_EMPTY3:1;         /* FIFO 3 EMPTY Flag */
 9657         vuint32_t FIFO_FULL3:1;          /* FIFO 3 FULL Flag */
 9658         vuint32_t FIFO_OVERRUN2:1;       /* FIFO 2 OVERRUN  Flag */
 9659         vuint32_t FIFO_OVERFLOW2:1;      /* FIFO 2 OVERFLOW Flag */
 9660         vuint32_t FIFO_EMPTY2:1;         /* FIFO 2 EMPTY Flag */
 9661         vuint32_t FIFO_FULL2:1;          /* FIFO 2 FULL Flag */
 9662         vuint32_t FIFO_OVERRUN1:1;       /* FIFO 1 OVERRUN  Flag */
 9663         vuint32_t FIFO_OVERFLOW1:1;      /* FIFO 1 OVERFLOW Flag */
 9664         vuint32_t FIFO_EMPTY1:1;         /* FIFO 1 EMPTY Flag */
 9665         vuint32_t FIFO_FULL1:1;          /* FIFO 1 FULL Flag */
 9666         vuint32_t FIFO_OVERRUN0:1;       /* FIFO 0 OVERRUN  Flag */
 9667         vuint32_t FIFO_OVERFLOW0:1;      /* FIFO 0 OVERFLOW Flag */
 9668         vuint32_t FIFO_EMPTY0:1;         /* FIFO 0 EMPTY Flag */
 9669         vuint32_t FIFO_FULL0:1;          /* FIFO 0 FULL Flag */
 9670       } B;
 9671     } CTU_STS_32B_tag;
 9672   
 9673     /* Register layout for all registers FR ... */
 9674     typedef union {                      /* FIFO Right Aligned register */
 9675       vuint32_t R;
 9676       struct {
 9677        vuint32_t:
 9678         11;
 9679         vuint32_t ADC:1;                 /* ADC Unit */
 9680         vuint32_t N_CH:4;                /* Number Channel */
 9681        vuint32_t:
 9682         4;
 9683         vuint32_t DATA:12;               /* Data Fifo */
 9684       } B;
 9685     } CTU_FR_32B_tag;
 9686   
 9687     /* Register layout for all registers FL ... */
 9688     typedef union {                      /* FIFO Left Aligned register */
 9689       vuint32_t R;
 9690       struct {
 9691        vuint32_t:
 9692         11;
 9693         vuint32_t ADC:1;                 /* ADC Unit */
 9694         vuint32_t N_CH:4;                /* Number Channel */
 9695        vuint32_t:
 9696         1;
 9697         vuint32_t DATA:12;               /* Data Fifo */
 9698        vuint32_t:
 9699         3;
 9700       } B;
 9701     } CTU_FL_32B_tag;
 9702   
 9703     typedef union {                      /* CTU Error Flag Register */
 9704       vuint16_t R;
 9705       struct {
 9706        vuint16_t:
 9707         3;
 9708         vuint16_t CS:1;                  /* Counter Status */
 9709         vuint16_t ET_OE:1;               /* ExtTrigger Generation Overrun */
 9710         vuint16_t ERR_CMP:1;             /* Set if counter reaches TGSCCR register */
 9711         vuint16_t T4_OE:1;               /* Timer4 Generation Overrun */
 9712         vuint16_t T3_OE:1;               /* Timer3 Generation Overrun */
 9713         vuint16_t T2_OE:1;               /* Timer2 Generation Overrun */
 9714         vuint16_t T1_OE:1;               /* Timer1 Generation Overrun */
 9715   
 9716   #ifndef USE_FIELD_ALIASES_CTU
 9717   
 9718         vuint16_t ADC_OE:1;              /* ADC Command Generation Overrun */
 9719   
 9720   #else
 9721   
 9722         vuint16_t ADCOE:1;               /* deprecated name - please avoid */
 9723   
 9724   #endif
 9725   
 9726   #ifndef USE_FIELD_ALIASES_CTU
 9727   
 9728         vuint16_t TGS_OSM:1;             /* TGS Overrun */
 9729   
 9730   #else
 9731   
 9732         vuint16_t TGSOSM:1;              /* deprecated name - please avoid */
 9733   
 9734   #endif
 9735   
 9736   #ifndef USE_FIELD_ALIASES_CTU
 9737   
 9738         vuint16_t MRS_O:1;               /* MRS Overrun */
 9739   
 9740   #else
 9741   
 9742         vuint16_t MRSO:1;                /* deprecated name - please avoid */
 9743   
 9744   #endif
 9745   
 9746         vuint16_t ICE:1;                 /* Invalid Command Error */
 9747   
 9748   #ifndef USE_FIELD_ALIASES_CTU
 9749   
 9750         vuint16_t SM_TO:1;               /* Trigger Overrun */
 9751   
 9752   #else
 9753   
 9754         vuint16_t SMTO:1;                /* deprecated name - please avoid */
 9755   
 9756   #endif
 9757   
 9758   #ifndef USE_FIELD_ALIASES_CTU
 9759   
 9760         vuint16_t MRS_RE:1;              /* MRS Reload Error */
 9761   
 9762   #else
 9763   
 9764         vuint16_t MRSRE:1;               /* deprecated name - please avoid */
 9765   
 9766   #endif
 9767   
 9768       } B;
 9769     } CTU_CTUEFR_16B_tag;
 9770   
 9771     typedef union {                      /* CTU Interrupt Flag Register */
 9772       vuint16_t R;
 9773       struct {
 9774        vuint16_t:
 9775         4;
 9776         vuint16_t S_E_B:1;               /* Slice time OK */
 9777         vuint16_t S_E_A:1;               /* Slice time OK */
 9778   
 9779   #ifndef USE_FIELD_ALIASES_CTU
 9780   
 9781         vuint16_t ADC_I:1;               /* ADC Command Interrupt Flag */
 9782   
 9783   #else
 9784   
 9785         vuint16_t ADC:1;                 /* deprecated name - please avoid */
 9786   
 9787   #endif
 9788   
 9789   #ifndef USE_FIELD_ALIASES_CTU
 9790   
 9791         vuint16_t T7_I:1;                /* Trigger 7  Interrupt Flag */
 9792   
 9793   #else
 9794   
 9795         vuint16_t T7:1;                  /* deprecated name - please avoid */
 9796   
 9797   #endif
 9798   
 9799   #ifndef USE_FIELD_ALIASES_CTU
 9800   
 9801         vuint16_t T6_I:1;                /* Trigger 6  Interrupt Flag */
 9802   
 9803   #else
 9804   
 9805         vuint16_t T6:1;                  /* deprecated name - please avoid */
 9806   
 9807   #endif
 9808   
 9809   #ifndef USE_FIELD_ALIASES_CTU
 9810   
 9811         vuint16_t T5_I:1;                /* Trigger 5  Interrupt Flag */
 9812   
 9813   #else
 9814   
 9815         vuint16_t T5:1;                  /* deprecated name - please avoid */
 9816   
 9817   #endif
 9818   
 9819   #ifndef USE_FIELD_ALIASES_CTU
 9820   
 9821         vuint16_t T4_I:1;                /* Trigger 4  Interrupt Flag */
 9822   
 9823   #else
 9824   
 9825         vuint16_t T4:1;                  /* deprecated name - please avoid */
 9826   
 9827   #endif
 9828   
 9829   #ifndef USE_FIELD_ALIASES_CTU
 9830   
 9831         vuint16_t T3_I:1;                /* Trigger 3  Interrupt Flag */
 9832   
 9833   #else
 9834   
 9835         vuint16_t T3:1;                  /* deprecated name - please avoid */
 9836   
 9837   #endif
 9838   
 9839   #ifndef USE_FIELD_ALIASES_CTU
 9840   
 9841         vuint16_t T2_I:1;                /* Trigger 2  Interrupt Flag */
 9842   
 9843   #else
 9844   
 9845         vuint16_t T2:1;                  /* deprecated name - please avoid */
 9846   
 9847   #endif
 9848   
 9849   #ifndef USE_FIELD_ALIASES_CTU
 9850   
 9851         vuint16_t T1_I:1;                /* Trigger 1  Interrupt Flag */
 9852   
 9853   #else
 9854   
 9855         vuint16_t T1:1;                  /* deprecated name - please avoid */
 9856   
 9857   #endif
 9858   
 9859   #ifndef USE_FIELD_ALIASES_CTU
 9860   
 9861         vuint16_t T0_I:1;                /* Trigger 0  Interrupt Flag */
 9862   
 9863   #else
 9864   
 9865         vuint16_t T0:1;                  /* deprecated name - please avoid */
 9866   
 9867   #endif
 9868   
 9869   #ifndef USE_FIELD_ALIASES_CTU
 9870   
 9871         vuint16_t MRS_I:1;               /* MRS Interrupt Flag */
 9872   
 9873   #else
 9874   
 9875         vuint16_t MRS:1;                 /* deprecated name - please avoid */
 9876   
 9877   #endif
 9878   
 9879       } B;
 9880     } CTU_CTUIFR_16B_tag;
 9881   
 9882     typedef union {                      /* CTU Interrupt/DMA Register */
 9883       vuint16_t R;
 9884       struct {
 9885   
 9886   #ifndef USE_FIELD_ALIASES_CTU
 9887   
 9888         vuint16_t T7_I:1;                /* Trigger 7  Interrupt Enable */
 9889   
 9890   #else
 9891   
 9892         vuint16_t T7IE:1;                /* deprecated name - please avoid */
 9893   
 9894   #endif
 9895   
 9896   #ifndef USE_FIELD_ALIASES_CTU
 9897   
 9898         vuint16_t T6_I:1;                /* Trigger 6  Interrupt Enable */
 9899   
 9900   #else
 9901   
 9902         vuint16_t T6IE:1;                /* deprecated name - please avoid */
 9903   
 9904   #endif
 9905   
 9906   #ifndef USE_FIELD_ALIASES_CTU
 9907   
 9908         vuint16_t T5_I:1;                /* Trigger 5  Interrupt Enable */
 9909   
 9910   #else
 9911   
 9912         vuint16_t T5IE:1;                /* deprecated name - please avoid */
 9913   
 9914   #endif
 9915   
 9916   #ifndef USE_FIELD_ALIASES_CTU
 9917   
 9918         vuint16_t T4_I:1;                /* Trigger 4  Interrupt Enable */
 9919   
 9920   #else
 9921   
 9922         vuint16_t T4IE:1;                /* deprecated name - please avoid */
 9923   
 9924   #endif
 9925   
 9926   #ifndef USE_FIELD_ALIASES_CTU
 9927   
 9928         vuint16_t T3_I:1;                /* Trigger 3  Interrupt Enable */
 9929   
 9930   #else
 9931   
 9932         vuint16_t T3IE:1;                /* deprecated name - please avoid */
 9933   
 9934   #endif
 9935   
 9936   #ifndef USE_FIELD_ALIASES_CTU
 9937   
 9938         vuint16_t T2_I:1;                /* Trigger 2  Interrupt Enable */
 9939   
 9940   #else
 9941   
 9942         vuint16_t T2IE:1;                /* deprecated name - please avoid */
 9943   
 9944   #endif
 9945   
 9946   #ifndef USE_FIELD_ALIASES_CTU
 9947   
 9948         vuint16_t T1_I:1;                /* Trigger 1  Interrupt Enable */
 9949   
 9950   #else
 9951   
 9952         vuint16_t T1IE:1;                /* deprecated name - please avoid */
 9953   
 9954   #endif
 9955   
 9956   #ifndef USE_FIELD_ALIASES_CTU
 9957   
 9958         vuint16_t T0_I:1;                /* Trigger 0  Interrupt Enable */
 9959   
 9960   #else
 9961   
 9962         vuint16_t T0IE:1;                /* deprecated name - please avoid */
 9963   
 9964   #endif
 9965   
 9966        vuint16_t:
 9967         2;
 9968         vuint16_t SAF_CNT_B_EN:1;        /* Conversion time counter enabled */
 9969         vuint16_t SAF_CNT_A_EN:1;        /* Conversion time counter enabled */
 9970         vuint16_t DMA_DE:1;              /* DMA and gre bit */
 9971   
 9972   #ifndef USE_FIELD_ALIASES_CTU
 9973   
 9974         vuint16_t MRS_DMAE:1;            /* DMA Transfer Enable */
 9975   
 9976   #else
 9977   
 9978         vuint16_t MRSDMAE:1;             /* deprecated name - please avoid */
 9979   
 9980   #endif
 9981   
 9982   #ifndef USE_FIELD_ALIASES_CTU
 9983   
 9984         vuint16_t MRS_IE:1;              /* MRS Interrupt Enable */
 9985   
 9986   #else
 9987   
 9988         vuint16_t MRSIE:1;               /* deprecated name - please avoid */
 9989   
 9990   #endif
 9991   
 9992         vuint16_t IEE:1;                 /* Interrupt Error Enable */
 9993       } B;
 9994     } CTU_CTUIR_16B_tag;
 9995   
 9996     typedef union {                      /* Control On-Time Register */
 9997       vuint16_t R;
 9998       struct {
 9999        vuint16_t:
10000         8;
10001   
10002   #ifndef USE_FIELD_ALIASES_CTU
10003   
10004         vuint16_t COTR_COTR:8;           /* Control On-Time Register and Guard Time */
10005   
10006   #else
10007   
10008         vuint16_t COTR:8;                /* deprecated name - please avoid */
10009   
10010   #endif
10011   
10012       } B;
10013     } CTU_COTR_16B_tag;
10014   
10015     typedef union {                      /* CTU Control Register */
10016       vuint16_t R;
10017       struct {
10018   
10019   #ifndef USE_FIELD_ALIASES_CTU
10020   
10021         vuint16_t T7_SG:1;               /* Trigger 7 Software Generated */
10022   
10023   #else
10024   
10025         vuint16_t T7SG:1;                /* deprecated name - please avoid */
10026   
10027   #endif
10028   
10029   #ifndef USE_FIELD_ALIASES_CTU
10030   
10031         vuint16_t T6_SG:1;               /* Trigger 6 Software Generated */
10032   
10033   #else
10034   
10035         vuint16_t T6SG:1;                /* deprecated name - please avoid */
10036   
10037   #endif
10038   
10039   #ifndef USE_FIELD_ALIASES_CTU
10040   
10041         vuint16_t T5_SG:1;               /* Trigger 5 Software Generated */
10042   
10043   #else
10044   
10045         vuint16_t T5SG:1;                /* deprecated name - please avoid */
10046   
10047   #endif
10048   
10049   #ifndef USE_FIELD_ALIASES_CTU
10050   
10051         vuint16_t T4_SG:1;               /* Trigger 4 Software Generated */
10052   
10053   #else
10054   
10055         vuint16_t T4SG:1;                /* deprecated name - please avoid */
10056   
10057   #endif
10058   
10059   #ifndef USE_FIELD_ALIASES_CTU
10060   
10061         vuint16_t T3_SG:1;               /* Trigger 3 Software Generated */
10062   
10063   #else
10064   
10065         vuint16_t T3SG:1;                /* deprecated name - please avoid */
10066   
10067   #endif
10068   
10069   #ifndef USE_FIELD_ALIASES_CTU
10070   
10071         vuint16_t T2_SG:1;               /* Trigger 2 Software Generated */
10072   
10073   #else
10074   
10075         vuint16_t T2SG:1;                /* deprecated name - please avoid */
10076   
10077   #endif
10078   
10079   #ifndef USE_FIELD_ALIASES_CTU
10080   
10081         vuint16_t T1_SG:1;               /* Trigger 1 Software Generated */
10082   
10083   #else
10084   
10085         vuint16_t T1SG:1;                /* deprecated name - please avoid */
10086   
10087   #endif
10088   
10089   #ifndef USE_FIELD_ALIASES_CTU
10090   
10091         vuint16_t T0_SG:1;               /* Trigger 0 Software Generated */
10092   
10093   #else
10094   
10095         vuint16_t T0SG:1;                /* deprecated name - please avoid */
10096   
10097   #endif
10098   
10099   #ifndef USE_FIELD_ALIASES_CTU
10100   
10101         vuint16_t CTU_ADC_RESET:1;       /* CTU ADC State Machine Reset */
10102   
10103   #else
10104   
10105         vuint16_t CTUADCRESET:1;         /* deprecated name - please avoid */
10106   
10107   #endif
10108   
10109   #ifndef USE_FIELD_ALIASES_CTU
10110   
10111         vuint16_t CTU_ODIS:1;            /* CTU Output Disable */
10112   
10113   #else
10114   
10115         vuint16_t CTUODIS:1;             /* deprecated name - please avoid */
10116   
10117   #endif
10118   
10119   #ifndef USE_FIELD_ALIASES_CTU
10120   
10121         vuint16_t FILTER_EN:1;           /* Synchronize Filter Register value */
10122   
10123   #else
10124   
10125         vuint16_t FILTERENABLE:1;        /* deprecated name - please avoid */
10126   
10127   #endif
10128   
10129         vuint16_t CGRE:1;                /* Clear GRE */
10130         vuint16_t FGRE:1;                /* GRE Flag */
10131   
10132   #ifndef USE_FIELD_ALIASES_CTU
10133   
10134         vuint16_t MRS_SG:1;              /* MRS Software Generated */
10135   
10136   #else
10137   
10138         vuint16_t MRSSG:1;               /* deprecated name - please avoid */
10139   
10140   #endif
10141   
10142         vuint16_t GRE:1;                 /* General Reload Enable */
10143   
10144   #ifndef USE_FIELD_ALIASES_CTU
10145   
10146         vuint16_t TGSISR_RE:1;           /* TGSISR Reload Enable */
10147   
10148   #else
10149   
10150         vuint16_t TGSISRRE:1;            /* deprecated name - please avoid */
10151   
10152   #endif
10153   
10154       } B;
10155     } CTU_CTUCR_16B_tag;
10156   
10157     typedef union {                      /* CTU Digital Filter Register */
10158       vuint16_t R;
10159       struct {
10160        vuint16_t:
10161         8;
10162   
10163   #ifndef USE_FIELD_ALIASES_CTU
10164   
10165         vuint16_t FILTER_VALUE:8;        /* Filter Value */
10166   
10167   #else
10168   
10169         vuint16_t FILTERVALUE:8;         /* deprecated name - please avoid */
10170   
10171   #endif
10172   
10173       } B;
10174     } CTU_FILTER_16B_tag;
10175   
10176     typedef union {                      /* CTU Expected A Value Register */
10177       vuint16_t R;
10178       struct {
10179         vuint16_t EXPECTED_A_VALUE:16;   /* Expected A Value */
10180       } B;
10181     } CTU_EXPECTED_A_16B_tag;
10182   
10183     typedef union {                      /* CTU Expected B Value Register */
10184       vuint16_t R;
10185       struct {
10186         vuint16_t EXPECTED_B_VALUE:16;   /* Expected B Value */
10187       } B;
10188     } CTU_EXPECTED_B_16B_tag;
10189   
10190     typedef union {                      /* CTU Counter Range Register */
10191       vuint16_t R;
10192       struct {
10193        vuint16_t:
10194         8;
10195         vuint16_t CNT_RANGE_VALUE:8;     /* Counter Range Value */
10196       } B;
10197     } CTU_CNT_RANGE_16B_tag;
10198   
10199     /* Register layout for generated register(s) FRA... */
10200     typedef union {                      /*  */
10201       vuint32_t R;
10202     } CTU_FRA_32B_tag;
10203   
10204     /* Register layout for generated register(s) FLA... */
10205     typedef union {                      /*  */
10206       vuint32_t R;
10207     } CTU_FLA_32B_tag;
10208   
10209     typedef struct CTU_struct_tag {
10210       /* Trigger Generator Subunit Input Selection register */
10211       CTU_TGSISR_32B_tag TGSISR;         /* offset: 0x0000 size: 32 bit */
10212   
10213       /* Trigger Generator Subunit Control Register */
10214       CTU_TGSCR_16B_tag TGSCR;           /* offset: 0x0004 size: 16 bit */
10215       union {
10216         CTU_TCR_16B_tag TCR[8];          /* offset: 0x0006  (0x0002 x 8) */
10217         struct {
10218           CTU_TCR_16B_tag T0CR;          /* offset: 0x0006 size: 16 bit */
10219           CTU_TCR_16B_tag T1CR;          /* offset: 0x0008 size: 16 bit */
10220           CTU_TCR_16B_tag T2CR;          /* offset: 0x000A size: 16 bit */
10221           CTU_TCR_16B_tag T3CR;          /* offset: 0x000C size: 16 bit */
10222           CTU_TCR_16B_tag T4CR;          /* offset: 0x000E size: 16 bit */
10223           CTU_TCR_16B_tag T5CR;          /* offset: 0x0010 size: 16 bit */
10224           CTU_TCR_16B_tag T6CR;          /* offset: 0x0012 size: 16 bit */
10225           CTU_TCR_16B_tag T7CR;          /* offset: 0x0014 size: 16 bit */
10226         };
10227       };
10228   
10229       /* TGS Counter Compare Register */
10230       CTU_TGSCCR_16B_tag TGSCCR;         /* offset: 0x0016 size: 16 bit */
10231   
10232       /* TGS Counter Reload Register */
10233       CTU_TGSCRR_16B_tag TGSCRR;         /* offset: 0x0018 size: 16 bit */
10234       int8_t CTU_reserved_001A[2];
10235   
10236       /* Commands List Control Register 1 */
10237       CTU_CLCR1_32B_tag CLCR1;           /* offset: 0x001C size: 32 bit */
10238   
10239       /* Commands List Control Register 2 */
10240       CTU_CLCR2_32B_tag CLCR2;           /* offset: 0x0020 size: 32 bit */
10241   
10242       /* Trigger Handler Control Register 1 */
10243       CTU_THCR1_32B_tag THCR1;           /* offset: 0x0024 size: 32 bit */
10244   
10245       /* Trigger Handler Control Register 2 */
10246       CTU_THCR2_32B_tag THCR2;           /* offset: 0x0028 size: 32 bit */
10247       union {
10248         /* Command List Register. View: BIT13, BIT9 */
10249         CTU_CLR_16B_tag CLR[24];         /* offset: 0x002C  (0x0002 x 24) */
10250   
10251         /* Command List Register. View: (CMS=BIT13=)ST1 = 0, (BIT9=)ST0 = 0 */
10252         CTU_CLR_SCM_16B_tag CLR_SCM[24]; /* offset: 0x002C  (0x0002 x 24) */
10253   
10254         /* Command List Register. View: (CMS=BIT13=)ST1 = 1, (BIT9=)ST0 = DONT CARE */
10255         CTU_CLR_DCM_16B_tag CLR_DCM[24]; /* offset: 0x002C  (0x0002 x 24) */
10256         struct {
10257           /* Command List Register. View: (CMS=BIT13=)ST1 = 0, (BIT9=)ST0 = 0 */
10258           CTU_CLR_SCM_16B_tag CLR_SCM1;  /* offset: 0x002C size: 16 bit */
10259           CTU_CLR_SCM_16B_tag CLR_SCM2;  /* offset: 0x002E size: 16 bit */
10260           CTU_CLR_SCM_16B_tag CLR_SCM3;  /* offset: 0x0030 size: 16 bit */
10261           CTU_CLR_SCM_16B_tag CLR_SCM4;  /* offset: 0x0032 size: 16 bit */
10262           CTU_CLR_SCM_16B_tag CLR_SCM5;  /* offset: 0x0034 size: 16 bit */
10263           CTU_CLR_SCM_16B_tag CLR_SCM6;  /* offset: 0x0036 size: 16 bit */
10264           CTU_CLR_SCM_16B_tag CLR_SCM7;  /* offset: 0x0038 size: 16 bit */
10265           CTU_CLR_SCM_16B_tag CLR_SCM8;  /* offset: 0x003A size: 16 bit */
10266           CTU_CLR_SCM_16B_tag CLR_SCM9;  /* offset: 0x003C size: 16 bit */
10267           CTU_CLR_SCM_16B_tag CLR_SCM10; /* offset: 0x003E size: 16 bit */
10268           CTU_CLR_SCM_16B_tag CLR_SCM11; /* offset: 0x0040 size: 16 bit */
10269           CTU_CLR_SCM_16B_tag CLR_SCM12; /* offset: 0x0042 size: 16 bit */
10270           CTU_CLR_SCM_16B_tag CLR_SCM13; /* offset: 0x0044 size: 16 bit */
10271           CTU_CLR_SCM_16B_tag CLR_SCM14; /* offset: 0x0046 size: 16 bit */
10272           CTU_CLR_SCM_16B_tag CLR_SCM15; /* offset: 0x0048 size: 16 bit */
10273           CTU_CLR_SCM_16B_tag CLR_SCM16; /* offset: 0x004A size: 16 bit */
10274           CTU_CLR_SCM_16B_tag CLR_SCM17; /* offset: 0x004C size: 16 bit */
10275           CTU_CLR_SCM_16B_tag CLR_SCM18; /* offset: 0x004E size: 16 bit */
10276           CTU_CLR_SCM_16B_tag CLR_SCM19; /* offset: 0x0050 size: 16 bit */
10277           CTU_CLR_SCM_16B_tag CLR_SCM20; /* offset: 0x0052 size: 16 bit */
10278           CTU_CLR_SCM_16B_tag CLR_SCM21; /* offset: 0x0054 size: 16 bit */
10279           CTU_CLR_SCM_16B_tag CLR_SCM22; /* offset: 0x0056 size: 16 bit */
10280           CTU_CLR_SCM_16B_tag CLR_SCM23; /* offset: 0x0058 size: 16 bit */
10281           CTU_CLR_SCM_16B_tag CLR_SCM24; /* offset: 0x005A size: 16 bit */
10282         };
10283   
10284         struct {
10285           /* Command List Register. View: (CMS=BIT13=)ST1 = 1, (BIT9=)ST0 = DONT CARE */
10286           CTU_CLR_DCM_16B_tag CLR_DCM1;  /* offset: 0x002C size: 16 bit */
10287           CTU_CLR_DCM_16B_tag CLR_DCM2;  /* offset: 0x002E size: 16 bit */
10288           CTU_CLR_DCM_16B_tag CLR_DCM3;  /* offset: 0x0030 size: 16 bit */
10289           CTU_CLR_DCM_16B_tag CLR_DCM4;  /* offset: 0x0032 size: 16 bit */
10290           CTU_CLR_DCM_16B_tag CLR_DCM5;  /* offset: 0x0034 size: 16 bit */
10291           CTU_CLR_DCM_16B_tag CLR_DCM6;  /* offset: 0x0036 size: 16 bit */
10292           CTU_CLR_DCM_16B_tag CLR_DCM7;  /* offset: 0x0038 size: 16 bit */
10293           CTU_CLR_DCM_16B_tag CLR_DCM8;  /* offset: 0x003A size: 16 bit */
10294           CTU_CLR_DCM_16B_tag CLR_DCM9;  /* offset: 0x003C size: 16 bit */
10295           CTU_CLR_DCM_16B_tag CLR_DCM10; /* offset: 0x003E size: 16 bit */
10296           CTU_CLR_DCM_16B_tag CLR_DCM11; /* offset: 0x0040 size: 16 bit */
10297           CTU_CLR_DCM_16B_tag CLR_DCM12; /* offset: 0x0042 size: 16 bit */
10298           CTU_CLR_DCM_16B_tag CLR_DCM13; /* offset: 0x0044 size: 16 bit */
10299           CTU_CLR_DCM_16B_tag CLR_DCM14; /* offset: 0x0046 size: 16 bit */
10300           CTU_CLR_DCM_16B_tag CLR_DCM15; /* offset: 0x0048 size: 16 bit */
10301           CTU_CLR_DCM_16B_tag CLR_DCM16; /* offset: 0x004A size: 16 bit */
10302           CTU_CLR_DCM_16B_tag CLR_DCM17; /* offset: 0x004C size: 16 bit */
10303           CTU_CLR_DCM_16B_tag CLR_DCM18; /* offset: 0x004E size: 16 bit */
10304           CTU_CLR_DCM_16B_tag CLR_DCM19; /* offset: 0x0050 size: 16 bit */
10305           CTU_CLR_DCM_16B_tag CLR_DCM20; /* offset: 0x0052 size: 16 bit */
10306           CTU_CLR_DCM_16B_tag CLR_DCM21; /* offset: 0x0054 size: 16 bit */
10307           CTU_CLR_DCM_16B_tag CLR_DCM22; /* offset: 0x0056 size: 16 bit */
10308           CTU_CLR_DCM_16B_tag CLR_DCM23; /* offset: 0x0058 size: 16 bit */
10309           CTU_CLR_DCM_16B_tag CLR_DCM24; /* offset: 0x005A size: 16 bit */
10310         };
10311   
10312         struct {
10313           /* Command List Register. View: BIT13, BIT9 */
10314           CTU_CLR_16B_tag CLR1;          /* offset: 0x002C size: 16 bit */
10315           CTU_CLR_16B_tag CLR2;          /* offset: 0x002E size: 16 bit */
10316           CTU_CLR_16B_tag CLR3;          /* offset: 0x0030 size: 16 bit */
10317           CTU_CLR_16B_tag CLR4;          /* offset: 0x0032 size: 16 bit */
10318           CTU_CLR_16B_tag CLR5;          /* offset: 0x0034 size: 16 bit */
10319           CTU_CLR_16B_tag CLR6;          /* offset: 0x0036 size: 16 bit */
10320           CTU_CLR_16B_tag CLR7;          /* offset: 0x0038 size: 16 bit */
10321           CTU_CLR_16B_tag CLR8;          /* offset: 0x003A size: 16 bit */
10322           CTU_CLR_16B_tag CLR9;          /* offset: 0x003C size: 16 bit */
10323           CTU_CLR_16B_tag CLR10;         /* offset: 0x003E size: 16 bit */
10324           CTU_CLR_16B_tag CLR11;         /* offset: 0x0040 size: 16 bit */
10325           CTU_CLR_16B_tag CLR12;         /* offset: 0x0042 size: 16 bit */
10326           CTU_CLR_16B_tag CLR13;         /* offset: 0x0044 size: 16 bit */
10327           CTU_CLR_16B_tag CLR14;         /* offset: 0x0046 size: 16 bit */
10328           CTU_CLR_16B_tag CLR15;         /* offset: 0x0048 size: 16 bit */
10329           CTU_CLR_16B_tag CLR16;         /* offset: 0x004A size: 16 bit */
10330           CTU_CLR_16B_tag CLR17;         /* offset: 0x004C size: 16 bit */
10331           CTU_CLR_16B_tag CLR18;         /* offset: 0x004E size: 16 bit */
10332           CTU_CLR_16B_tag CLR19;         /* offset: 0x0050 size: 16 bit */
10333           CTU_CLR_16B_tag CLR20;         /* offset: 0x0052 size: 16 bit */
10334           CTU_CLR_16B_tag CLR21;         /* offset: 0x0054 size: 16 bit */
10335           CTU_CLR_16B_tag CLR22;         /* offset: 0x0056 size: 16 bit */
10336           CTU_CLR_16B_tag CLR23;         /* offset: 0x0058 size: 16 bit */
10337           CTU_CLR_16B_tag CLR24;         /* offset: 0x005A size: 16 bit */
10338         };
10339       };
10340   
10341       int8_t CTU_reserved_005C[16];
10342   
10343       /* Control Register */
10344       CTU_CR_16B_tag CR;                 /* offset: 0x006C size: 16 bit */
10345       int8_t CTU_reserved_006E[2];
10346   
10347       /* Control Register FIFO */
10348       CTU_FCR_32B_tag FCR;               /* offset: 0x0070 size: 32 bit */
10349   
10350       /* Threshold 1 Register */
10351       CTU_TH1_32B_tag TH1;               /* offset: 0x0074 size: 32 bit */
10352   
10353       /* Threshold 2 Register */
10354       CTU_TH2_32B_tag TH2;               /* offset: 0x0078 size: 32 bit */
10355       union {
10356         /* Status Register */
10357         CTU_STS_32B_tag STS;             /* offset: 0x007C size: 32 bit */
10358         CTU_STS_32B_tag STATUS;          /* deprecated - please avoid */
10359       };
10360   
10361       union {
10362         CTU_FRA_32B_tag FRA[8];          /* offset: 0x0080  (0x0004 x 8) */
10363   
10364         /* FIFO Right Aligned register */
10365         CTU_FR_32B_tag FR[8];            /* offset: 0x0080  (0x0004 x 8) */
10366         struct {
10367           /* FIFO Right Aligned register */
10368           CTU_FR_32B_tag FR0;            /* offset: 0x0080 size: 32 bit */
10369           CTU_FR_32B_tag FR1;            /* offset: 0x0084 size: 32 bit */
10370           CTU_FR_32B_tag FR2;            /* offset: 0x0088 size: 32 bit */
10371           CTU_FR_32B_tag FR3;            /* offset: 0x008C size: 32 bit */
10372           CTU_FR_32B_tag FR4;            /* offset: 0x0090 size: 32 bit */
10373           CTU_FR_32B_tag FR5;            /* offset: 0x0094 size: 32 bit */
10374           CTU_FR_32B_tag FR6;            /* offset: 0x0098 size: 32 bit */
10375           CTU_FR_32B_tag FR7;            /* offset: 0x009C size: 32 bit */
10376         };
10377       };
10378   
10379       union {
10380         CTU_FLA_32B_tag FLA[8];          /* offset: 0x00A0  (0x0004 x 8) */
10381   
10382         /* FIFO Left Aligned register */
10383         CTU_FL_32B_tag FL[8];            /* offset: 0x00A0  (0x0004 x 8) */
10384         struct {
10385           /* FIFO Left Aligned register */
10386           CTU_FL_32B_tag FL0;            /* offset: 0x00A0 size: 32 bit */
10387           CTU_FL_32B_tag FL1;            /* offset: 0x00A4 size: 32 bit */
10388           CTU_FL_32B_tag FL2;            /* offset: 0x00A8 size: 32 bit */
10389           CTU_FL_32B_tag FL3;            /* offset: 0x00AC size: 32 bit */
10390           CTU_FL_32B_tag FL4;            /* offset: 0x00B0 size: 32 bit */
10391           CTU_FL_32B_tag FL5;            /* offset: 0x00B4 size: 32 bit */
10392           CTU_FL_32B_tag FL6;            /* offset: 0x00B8 size: 32 bit */
10393           CTU_FL_32B_tag FL7;            /* offset: 0x00BC size: 32 bit */
10394         };
10395       };
10396   
10397       /* CTU Error Flag Register */
10398       CTU_CTUEFR_16B_tag CTUEFR;         /* offset: 0x00C0 size: 16 bit */
10399   
10400       /* CTU Interrupt Flag Register */
10401       CTU_CTUIFR_16B_tag CTUIFR;         /* offset: 0x00C2 size: 16 bit */
10402   
10403       /* CTU Interrupt/DMA Register */
10404       CTU_CTUIR_16B_tag CTUIR;           /* offset: 0x00C4 size: 16 bit */
10405   
10406       /* Control On-Time Register */
10407       CTU_COTR_16B_tag COTR;             /* offset: 0x00C6 size: 16 bit */
10408   
10409       /* CTU Control Register */
10410       CTU_CTUCR_16B_tag CTUCR;           /* offset: 0x00C8 size: 16 bit */
10411       union {
10412         /* CTU Digital Filter Register */
10413         CTU_FILTER_16B_tag FILTER;       /* offset: 0x00CA size: 16 bit */
10414         CTU_FILTER_16B_tag CTUFILTER;    /* deprecated - please avoid */
10415       };
10416   
10417       /* CTU Expected A Value Register */
10418       CTU_EXPECTED_A_16B_tag EXPECTED_A; /* offset: 0x00CC size: 16 bit */
10419   
10420       /* CTU Expected B Value Register */
10421       CTU_EXPECTED_B_16B_tag EXPECTED_B; /* offset: 0x00CE size: 16 bit */
10422   
10423       /* CTU Counter Range Register */
10424       CTU_CNT_RANGE_16B_tag CNT_RANGE;   /* offset: 0x00D0 size: 16 bit */
10425       int8_t CTU_reserved_00D2[16174];
10426     } CTU_tag;
10427   
10428   #define CTU                            (*(volatile CTU_tag *) 0xFFE0C000UL)
10429   
10430     /****************************************************************/
10431     /*                                                              */
10432     /* Module: mcTIMER  */
10433     /*                                                              */
10434     /****************************************************************/
10435   
10436     /* Register layout for all registers COMP1 ... */
10437     typedef union {                      /* Compare Register 1 */
10438       vuint16_t R;
10439       struct {
10440         vuint16_t COMP1:16;              /* deprecated definition -- do not use */
10441       } B;
10442     } mcTIMER_COMP1_16B_tag;
10443   
10444     /* Register layout for all registers COMP2 ... */
10445     typedef union {                      /* Compare Register 2 */
10446       vuint16_t R;
10447       struct {
10448         vuint16_t COMP2:16;              /* deprecated definition -- do not use */
10449       } B;
10450     } mcTIMER_COMP2_16B_tag;
10451   
10452     /* Register layout for all registers CAPT1 ... */
10453     typedef union {                      /* Capture Register 1 */
10454       vuint16_t R;
10455       struct {
10456         vuint16_t CAPT1:16;              /* deprecated definition -- do not use */
10457       } B;
10458     } mcTIMER_CAPT1_16B_tag;
10459   
10460     /* Register layout for all registers CAPT2 ... */
10461     typedef union {                      /* Capture Register 2 */
10462       vuint16_t R;
10463       struct {
10464         vuint16_t CAPT2:16;              /* deprecated definition -- do not use */
10465       } B;
10466     } mcTIMER_CAPT2_16B_tag;
10467   
10468     /* Register layout for all registers LOAD ... */
10469     typedef union {                      /* Load Register */
10470       vuint16_t R;
10471       struct {
10472         vuint16_t LOAD:16;               /* deprecated definition -- do not use */
10473       } B;
10474     } mcTIMER_LOAD_16B_tag;
10475   
10476     /* Register layout for all registers HOLD ... */
10477     typedef union {                      /* Hold Register */
10478       vuint16_t R;
10479       struct {
10480         vuint16_t HOLD:16;               /* deprecated definition -- do not use */
10481       } B;
10482     } mcTIMER_HOLD_16B_tag;
10483   
10484     /* Register layout for all registers CNTR ... */
10485     typedef union {                      /* Counter Register */
10486       vuint16_t R;
10487       struct {
10488         vuint16_t CNTR:16;               /* deprecated definition -- do not use */
10489       } B;
10490     } mcTIMER_CNTR_16B_tag;
10491   
10492     /* Register layout for all registers CTRL1 ... */
10493     typedef union {                      /* Control Register */
10494       vuint16_t R;
10495       struct {
10496         vuint16_t CNTMODE:3;             /* Count Mode */
10497         vuint16_t PRISRC:5;              /* Primary Count Source */
10498         vuint16_t ONCE:1;                /* Count Once */
10499         vuint16_t LENGTH:1;              /* Count Length */
10500         vuint16_t DIR:1;                 /* Count Direction */
10501         vuint16_t SECSRC:5;              /* Secondary Count Source */
10502       } B;
10503     } mcTIMER_CTRL1_16B_tag;
10504   
10505     /* Register layout for all registers CTRL2 ... */
10506     typedef union {                      /* Control Register 2 */
10507       vuint16_t R;
10508       struct {
10509         vuint16_t OEN:1;                 /* Output Enable */
10510         vuint16_t RDNT:1;                /* Redundant Channel Enable */
10511         vuint16_t INPUT:1;               /* External Input Signal */
10512         vuint16_t VAL:1;                 /* Forced OFLAG Value */
10513         vuint16_t FORCE:1;               /* Force the OFLAG output */
10514         vuint16_t COFRC:1;               /* Co-channel OFLAG Force */
10515         vuint16_t COINIT:2;              /* Co-channel Initialization */
10516         vuint16_t SIPS:1;                /* Secondary Source Input Polarity Select */
10517         vuint16_t PIPS:1;                /* Primary Source Input Polarity Select */
10518         vuint16_t OPS:1;                 /* Output Polarity Select */
10519         vuint16_t MSTR:1;                /* Master Mode */
10520         vuint16_t OUTMODE:4;             /* Output Mode */
10521       } B;
10522     } mcTIMER_CTRL2_16B_tag;
10523   
10524     /* Register layout for all registers CTRL3 ... */
10525     typedef union {                      /* Control Register 3 */
10526       vuint16_t R;
10527       struct {
10528         vuint16_t STPEN:1;               /* Stop Action Enable */
10529         vuint16_t ROC:2;                 /* Reload On Capture */
10530         vuint16_t FMODE:1;               /* Fault Safing Mode */
10531         vuint16_t FDIS:4;                /* Fault Disable Mask */
10532         vuint16_t C2FCNT:3;              /* CAPT2 FIFO Word Count */
10533         vuint16_t C1FCNT:3;              /* CAPT1 FIFO Word Count */
10534         vuint16_t DBGEN:2;               /* Debug Actions Enable */
10535       } B;
10536     } mcTIMER_CTRL3_16B_tag;
10537   
10538     /* Register layout for all registers STS ... */
10539     typedef union {                      /* Status Register */
10540       vuint16_t R;
10541       struct {
10542        vuint16_t:
10543         6;
10544         vuint16_t WDF:1;                 /* Watchdog Time-out Flag */
10545         vuint16_t RCF:1;                 /* Redundant Channel Flag */
10546         vuint16_t ICF2:1;                /* Input Capture 2 Flag */
10547         vuint16_t ICF1:1;                /* Input Capture 1 Flag */
10548         vuint16_t IEHF:1;                /* Input Edge High Flag */
10549         vuint16_t IELF:1;                /* Input Edge Low Flag */
10550         vuint16_t TOF:1;                 /* Timer Overflow Flag */
10551         vuint16_t TCF2:1;                /* Timer Compare 2 Flag */
10552         vuint16_t TCF1:1;                /* Timer Compare 1 Flag */
10553         vuint16_t TCF:1;                 /* Timer Compare Flag */
10554       } B;
10555     } mcTIMER_STS_16B_tag;
10556   
10557     /* Register layout for all registers INTDMA ... */
10558     typedef union {                      /* Interrupt and DMA Enable Register */
10559       vuint16_t R;
10560       struct {
10561         vuint16_t ICF2DE:1;              /* Input Capture 2 Flag DMA Enable */
10562         vuint16_t ICF1DE:1;              /* Input Capture 1 Flag DMA Enable */
10563         vuint16_t CMPLD2DE:1;            /* Comparator Load Register 2 Flag DMA Enable */
10564         vuint16_t CMPLD1DE:1;            /* Comparator Load Register 1 Flag DMA Enable */
10565        vuint16_t:
10566         2;
10567         vuint16_t WDFIE:1;               /* Watchdog Flag Interrupt Enable */
10568         vuint16_t RCFIE:1;               /* Redundant Channel Flag Interrupt Enable */
10569         vuint16_t ICF2IE:1;              /* Input Capture 2 Flag Interrupt Enable */
10570         vuint16_t ICF1IE:1;              /* Input Capture 1 Flag Interrupt Enable */
10571         vuint16_t IEHFIE:1;              /* Input Edge High Flag Interrupt Enable */
10572         vuint16_t IELFIE:1;              /* Input Edge Low Flag Interrupt Enable */
10573         vuint16_t TOFIE:1;               /* Timer Overflow Flag Interrupt Enable */
10574         vuint16_t TCF2IE:1;              /* Timer Compare 2 Flag Interrupt Enable */
10575         vuint16_t TCF1IE:1;              /* Timer Compare 1 Flag Interrupt Enable */
10576         vuint16_t TCFIE:1;               /* Timer Compare Flag Interrupt Enable */
10577       } B;
10578     } mcTIMER_INTDMA_16B_tag;
10579   
10580     /* Register layout for all registers CMPLD1 ... */
10581     typedef union {                      /* Comparator Load Register 1 */
10582       vuint16_t R;
10583       struct {
10584         vuint16_t CMPLD1:16;             /* deprecated definition -- do not use */
10585       } B;
10586     } mcTIMER_CMPLD1_16B_tag;
10587   
10588     /* Register layout for all registers CMPLD2 ... */
10589     typedef union {                      /* Comparator Load Register 2 */
10590       vuint16_t R;
10591       struct {
10592         vuint16_t CMPLD2:16;             /* deprecated definition -- do not use */
10593       } B;
10594     } mcTIMER_CMPLD2_16B_tag;
10595   
10596     /* Register layout for all registers CCCTRL ... */
10597     typedef union {                      /* Compare and Capture Control Register */
10598       vuint16_t R;
10599       struct {
10600         vuint16_t CLC2:3;                /* Compare Load Control 2 */
10601         vuint16_t CLC1:3;                /* Compare Load Control 1 */
10602         vuint16_t CMPMODE:2;             /* Compare Mode */
10603         vuint16_t CPT2MODE:2;            /* Capture 2 Mode Control */
10604         vuint16_t CPT1MODE:2;            /* Capture 1 Mode Control */
10605         vuint16_t CFWM:2;                /* Capture FIFO Water Mark */
10606         vuint16_t ONESHOT:1;             /* One Shot Capture Mode */
10607         vuint16_t ARM:1;                 /* Arm Capture */
10608       } B;
10609     } mcTIMER_CCCTRL_16B_tag;
10610   
10611     /* Register layout for all registers FILT ... */
10612     typedef union {                      /* Input Filter Register */
10613       vuint16_t R;
10614       struct {
10615        vuint16_t:
10616         5;
10617   
10618   #ifndef USE_FIELD_ALIASES_mcTIMER
10619   
10620         vuint16_t FILT_CNT:3;            /* Input Filter Sample Count */
10621   
10622   #else
10623   
10624         vuint16_t FILTCNT:3;             /* deprecated name - please avoid */
10625   
10626   #endif
10627   
10628   #ifndef USE_FIELD_ALIASES_mcTIMER
10629   
10630         vuint16_t FILT_PER:8;            /* Input Filter Sample Period */
10631   
10632   #else
10633   
10634         vuint16_t FILTPER:8;             /* deprecated name - please avoid */
10635   
10636   #endif
10637   
10638       } B;
10639     } mcTIMER_FILT_16B_tag;
10640   
10641     typedef union {                      /* Watchdog Time-out Register */
10642       vuint16_t R;
10643       struct {
10644         vuint16_t WDTOL:16;              /* deprecated definition -- do not use */
10645       } B;
10646     } mcTIMER_WDTOL_16B_tag;
10647   
10648     typedef union {                      /* Watchdog Time-out Register */
10649       vuint16_t R;
10650       struct {
10651         vuint16_t WDTOH:16;              /* deprecated definition -- do not use */
10652       } B;
10653     } mcTIMER_WDTOH_16B_tag;
10654   
10655     typedef union {                      /* Fault Control Register */
10656       vuint16_t R;
10657       struct {
10658        vuint16_t:
10659         3;
10660         vuint16_t FTEST:1;               /* Fault Test */
10661         vuint16_t FIE:4;                 /* Fault Interrupt Enable */
10662        vuint16_t:
10663         4;
10664         vuint16_t FLVL:4;                /* Fault Active Logic Level */
10665       } B;
10666     } mcTIMER_FCTRL_16B_tag;
10667   
10668     typedef union {                      /* Fault Status Register */
10669       vuint16_t R;
10670       struct {
10671        vuint16_t:
10672         4;
10673         vuint16_t FFPIN:4;               /* Filtered Fault Pin */
10674        vuint16_t:
10675         4;
10676         vuint16_t FFLAG:4;               /* Fault Flag */
10677       } B;
10678     } mcTIMER_FSTS_16B_tag;
10679   
10680     typedef union {                      /* Fault Filter Registers */
10681       vuint16_t R;
10682       struct {
10683        vuint16_t:
10684         5;
10685   
10686   #ifndef USE_FIELD_ALIASES_mcTIMER
10687   
10688         vuint16_t FFPIN:3;               /* Fault Filter Sample Count */
10689   
10690   #else
10691   
10692         vuint16_t FFILTCNT:3;            /* deprecated name - please avoid */
10693   
10694   #endif
10695   
10696   #ifndef USE_FIELD_ALIASES_mcTIMER
10697   
10698         vuint16_t FFILT_PER:8;           /* Fault Filter Sample Period */
10699   
10700   #else
10701   
10702         vuint16_t FFILTPER:8;            /* deprecated name - please avoid */
10703   
10704   #endif
10705   
10706       } B;
10707     } mcTIMER_FFILT_16B_tag;
10708   
10709     typedef union {                      /* Channel Enable Registers */
10710       vuint16_t R;
10711       struct {
10712        vuint16_t:
10713         8;
10714         vuint16_t ENBL:8;                /* Timer Channel Enable */
10715       } B;
10716     } mcTIMER_ENBL_16B_tag;
10717   
10718     typedef union {                      /* DMA Request 0 Select Registers */
10719       vuint16_t R;
10720       struct {
10721        vuint16_t:
10722         11;
10723         vuint16_t DREQ0V:5;              /* DMA Request Select */
10724       } B;
10725     } mcTIMER_DREQ0_16B_tag;
10726   
10727     typedef union {                      /* DMA Request 1 Select Registers */
10728       vuint16_t R;
10729       struct {
10730        vuint16_t:
10731         11;
10732         vuint16_t DREQ1V:5;              /* DMA Request Select */
10733       } B;
10734     } mcTIMER_DREQ1_16B_tag;
10735   
10736     typedef union {                      /* DMA Request 2 Select Registers */
10737       vuint16_t R;
10738       struct {
10739        vuint16_t:
10740         11;
10741         vuint16_t DREQ2V:5;              /* DMA Request Select */
10742       } B;
10743     } mcTIMER_DREQ2_16B_tag;
10744   
10745     typedef union {                      /* DMA Request 3 Select Registers */
10746       vuint16_t R;
10747       struct {
10748        vuint16_t:
10749         11;
10750         vuint16_t DREQ3V:5;              /* DMA Request Select */
10751       } B;
10752     } mcTIMER_DREQ3_16B_tag;
10753   
10754     /* Register layout for generated register(s) DREQ... */
10755     typedef union {                      /*  */
10756       vuint16_t R;
10757     } mcTIMER_DREQ_16B_tag;
10758   
10759     typedef struct mcTIMER_CHANNEL_struct_tag {
10760       /* Compare Register 1 */
10761       mcTIMER_COMP1_16B_tag COMP1;       /* relative offset: 0x0000 */
10762   
10763       /* Compare Register 2 */
10764       mcTIMER_COMP2_16B_tag COMP2;       /* relative offset: 0x0002 */
10765   
10766       /* Capture Register 1 */
10767       mcTIMER_CAPT1_16B_tag CAPT1;       /* relative offset: 0x0004 */
10768   
10769       /* Capture Register 2 */
10770       mcTIMER_CAPT2_16B_tag CAPT2;       /* relative offset: 0x0006 */
10771   
10772       /* Load Register */
10773       mcTIMER_LOAD_16B_tag LOAD;         /* relative offset: 0x0008 */
10774   
10775       /* Hold Register */
10776       mcTIMER_HOLD_16B_tag HOLD;         /* relative offset: 0x000A */
10777   
10778       /* Counter Register */
10779       mcTIMER_CNTR_16B_tag CNTR;         /* relative offset: 0x000C */
10780       union {
10781         /* Control Register */
10782         mcTIMER_CTRL1_16B_tag CTRL1;     /* relative offset: 0x000E */
10783         mcTIMER_CTRL1_16B_tag CTRL;      /* deprecated - please avoid */
10784       };
10785   
10786       /* Control Register 2 */
10787       mcTIMER_CTRL2_16B_tag CTRL2;       /* relative offset: 0x0010 */
10788   
10789       /* Control Register 3 */
10790       mcTIMER_CTRL3_16B_tag CTRL3;       /* relative offset: 0x0012 */
10791   
10792       /* Status Register */
10793       mcTIMER_STS_16B_tag STS;           /* relative offset: 0x0014 */
10794   
10795       /* Interrupt and DMA Enable Register */
10796       mcTIMER_INTDMA_16B_tag INTDMA;     /* relative offset: 0x0016 */
10797   
10798       /* Comparator Load Register 1 */
10799       mcTIMER_CMPLD1_16B_tag CMPLD1;     /* relative offset: 0x0018 */
10800   
10801       /* Comparator Load Register 2 */
10802       mcTIMER_CMPLD2_16B_tag CMPLD2;     /* relative offset: 0x001A */
10803   
10804       /* Compare and Capture Control Register */
10805       mcTIMER_CCCTRL_16B_tag CCCTRL;     /* relative offset: 0x001C */
10806   
10807       /* Input Filter Register */
10808       mcTIMER_FILT_16B_tag FILT;         /* relative offset: 0x001E */
10809     } mcTIMER_CHANNEL_tag;
10810   
10811     typedef struct mcTIMER_struct_tag {
10812       union {
10813         /*  Register set CHANNEL */
10814         mcTIMER_CHANNEL_tag CHANNEL[6];  /* offset: 0x0000  (0x0020 x 6) */
10815         struct {
10816           /* Compare Register 1 */
10817           mcTIMER_COMP1_16B_tag COMP10;  /* offset: 0x0000 size: 16 bit */
10818   
10819           /* Compare Register 2 */
10820           mcTIMER_COMP2_16B_tag COMP20;  /* offset: 0x0002 size: 16 bit */
10821   
10822           /* Capture Register 1 */
10823           mcTIMER_CAPT1_16B_tag CAPT10;  /* offset: 0x0004 size: 16 bit */
10824   
10825           /* Capture Register 2 */
10826           mcTIMER_CAPT2_16B_tag CAPT20;  /* offset: 0x0006 size: 16 bit */
10827   
10828           /* Load Register */
10829           mcTIMER_LOAD_16B_tag LOAD0;    /* offset: 0x0008 size: 16 bit */
10830   
10831           /* Hold Register */
10832           mcTIMER_HOLD_16B_tag HOLD0;    /* offset: 0x000A size: 16 bit */
10833   
10834           /* Counter Register */
10835           mcTIMER_CNTR_16B_tag CNTR0;    /* offset: 0x000C size: 16 bit */
10836   
10837           /* Control Register */
10838           mcTIMER_CTRL1_16B_tag CTRL10;  /* offset: 0x000E size: 16 bit */
10839   
10840           /* Control Register 2 */
10841           mcTIMER_CTRL2_16B_tag CTRL20;  /* offset: 0x0010 size: 16 bit */
10842   
10843           /* Control Register 3 */
10844           mcTIMER_CTRL3_16B_tag CTRL30;  /* offset: 0x0012 size: 16 bit */
10845   
10846           /* Status Register */
10847           mcTIMER_STS_16B_tag STS0;      /* offset: 0x0014 size: 16 bit */
10848   
10849           /* Interrupt and DMA Enable Register */
10850           mcTIMER_INTDMA_16B_tag INTDMA0;/* offset: 0x0016 size: 16 bit */
10851   
10852           /* Comparator Load Register 1 */
10853           mcTIMER_CMPLD1_16B_tag CMPLD10;/* offset: 0x0018 size: 16 bit */
10854   
10855           /* Comparator Load Register 2 */
10856           mcTIMER_CMPLD2_16B_tag CMPLD20;/* offset: 0x001A size: 16 bit */
10857   
10858           /* Compare and Capture Control Register */
10859           mcTIMER_CCCTRL_16B_tag CCCTRL0;/* offset: 0x001C size: 16 bit */
10860   
10861           /* Input Filter Register */
10862           mcTIMER_FILT_16B_tag FILT0;    /* offset: 0x001E size: 16 bit */
10863   
10864           /* Compare Register 1 */
10865           mcTIMER_COMP1_16B_tag COMP11;  /* offset: 0x0020 size: 16 bit */
10866   
10867           /* Compare Register 2 */
10868           mcTIMER_COMP2_16B_tag COMP21;  /* offset: 0x0022 size: 16 bit */
10869   
10870           /* Capture Register 1 */
10871           mcTIMER_CAPT1_16B_tag CAPT11;  /* offset: 0x0024 size: 16 bit */
10872   
10873           /* Capture Register 2 */
10874           mcTIMER_CAPT2_16B_tag CAPT21;  /* offset: 0x0026 size: 16 bit */
10875   
10876           /* Load Register */
10877           mcTIMER_LOAD_16B_tag LOAD1;    /* offset: 0x0028 size: 16 bit */
10878   
10879           /* Hold Register */
10880           mcTIMER_HOLD_16B_tag HOLD1;    /* offset: 0x002A size: 16 bit */
10881   
10882           /* Counter Register */
10883           mcTIMER_CNTR_16B_tag CNTR1;    /* offset: 0x002C size: 16 bit */
10884   
10885           /* Control Register */
10886           mcTIMER_CTRL1_16B_tag CTRL11;  /* offset: 0x002E size: 16 bit */
10887   
10888           /* Control Register 2 */
10889           mcTIMER_CTRL2_16B_tag CTRL21;  /* offset: 0x0030 size: 16 bit */
10890   
10891           /* Control Register 3 */
10892           mcTIMER_CTRL3_16B_tag CTRL31;  /* offset: 0x0032 size: 16 bit */
10893   
10894           /* Status Register */
10895           mcTIMER_STS_16B_tag STS1;      /* offset: 0x0034 size: 16 bit */
10896   
10897           /* Interrupt and DMA Enable Register */
10898           mcTIMER_INTDMA_16B_tag INTDMA1;/* offset: 0x0036 size: 16 bit */
10899   
10900           /* Comparator Load Register 1 */
10901           mcTIMER_CMPLD1_16B_tag CMPLD11;/* offset: 0x0038 size: 16 bit */
10902   
10903           /* Comparator Load Register 2 */
10904           mcTIMER_CMPLD2_16B_tag CMPLD21;/* offset: 0x003A size: 16 bit */
10905   
10906           /* Compare and Capture Control Register */
10907           mcTIMER_CCCTRL_16B_tag CCCTRL1;/* offset: 0x003C size: 16 bit */
10908   
10909           /* Input Filter Register */
10910           mcTIMER_FILT_16B_tag FILT1;    /* offset: 0x003E size: 16 bit */
10911   
10912           /* Compare Register 1 */
10913           mcTIMER_COMP1_16B_tag COMP12;  /* offset: 0x0040 size: 16 bit */
10914   
10915           /* Compare Register 2 */
10916           mcTIMER_COMP2_16B_tag COMP22;  /* offset: 0x0042 size: 16 bit */
10917   
10918           /* Capture Register 1 */
10919           mcTIMER_CAPT1_16B_tag CAPT12;  /* offset: 0x0044 size: 16 bit */
10920   
10921           /* Capture Register 2 */
10922           mcTIMER_CAPT2_16B_tag CAPT22;  /* offset: 0x0046 size: 16 bit */
10923   
10924           /* Load Register */
10925           mcTIMER_LOAD_16B_tag LOAD2;    /* offset: 0x0048 size: 16 bit */
10926   
10927           /* Hold Register */
10928           mcTIMER_HOLD_16B_tag HOLD2;    /* offset: 0x004A size: 16 bit */
10929   
10930           /* Counter Register */
10931           mcTIMER_CNTR_16B_tag CNTR2;    /* offset: 0x004C size: 16 bit */
10932   
10933           /* Control Register */
10934           mcTIMER_CTRL1_16B_tag CTRL12;  /* offset: 0x004E size: 16 bit */
10935   
10936           /* Control Register 2 */
10937           mcTIMER_CTRL2_16B_tag CTRL22;  /* offset: 0x0050 size: 16 bit */
10938   
10939           /* Control Register 3 */
10940           mcTIMER_CTRL3_16B_tag CTRL32;  /* offset: 0x0052 size: 16 bit */
10941   
10942           /* Status Register */
10943           mcTIMER_STS_16B_tag STS2;      /* offset: 0x0054 size: 16 bit */
10944   
10945           /* Interrupt and DMA Enable Register */
10946           mcTIMER_INTDMA_16B_tag INTDMA2;/* offset: 0x0056 size: 16 bit */
10947   
10948           /* Comparator Load Register 1 */
10949           mcTIMER_CMPLD1_16B_tag CMPLD12;/* offset: 0x0058 size: 16 bit */
10950   
10951           /* Comparator Load Register 2 */
10952           mcTIMER_CMPLD2_16B_tag CMPLD22;/* offset: 0x005A size: 16 bit */
10953   
10954           /* Compare and Capture Control Register */
10955           mcTIMER_CCCTRL_16B_tag CCCTRL2;/* offset: 0x005C size: 16 bit */
10956   
10957           /* Input Filter Register */
10958           mcTIMER_FILT_16B_tag FILT2;    /* offset: 0x005E size: 16 bit */
10959   
10960           /* Compare Register 1 */
10961           mcTIMER_COMP1_16B_tag COMP13;  /* offset: 0x0060 size: 16 bit */
10962   
10963           /* Compare Register 2 */
10964           mcTIMER_COMP2_16B_tag COMP23;  /* offset: 0x0062 size: 16 bit */
10965   
10966           /* Capture Register 1 */
10967           mcTIMER_CAPT1_16B_tag CAPT13;  /* offset: 0x0064 size: 16 bit */
10968   
10969           /* Capture Register 2 */
10970           mcTIMER_CAPT2_16B_tag CAPT23;  /* offset: 0x0066 size: 16 bit */
10971   
10972           /* Load Register */
10973           mcTIMER_LOAD_16B_tag LOAD3;    /* offset: 0x0068 size: 16 bit */
10974   
10975           /* Hold Register */
10976           mcTIMER_HOLD_16B_tag HOLD3;    /* offset: 0x006A size: 16 bit */
10977   
10978           /* Counter Register */
10979           mcTIMER_CNTR_16B_tag CNTR3;    /* offset: 0x006C size: 16 bit */
10980   
10981           /* Control Register */
10982           mcTIMER_CTRL1_16B_tag CTRL13;  /* offset: 0x006E size: 16 bit */
10983   
10984           /* Control Register 2 */
10985           mcTIMER_CTRL2_16B_tag CTRL23;  /* offset: 0x0070 size: 16 bit */
10986   
10987           /* Control Register 3 */
10988           mcTIMER_CTRL3_16B_tag CTRL33;  /* offset: 0x0072 size: 16 bit */
10989   
10990           /* Status Register */
10991           mcTIMER_STS_16B_tag STS3;      /* offset: 0x0074 size: 16 bit */
10992   
10993           /* Interrupt and DMA Enable Register */
10994           mcTIMER_INTDMA_16B_tag INTDMA3;/* offset: 0x0076 size: 16 bit */
10995   
10996           /* Comparator Load Register 1 */
10997           mcTIMER_CMPLD1_16B_tag CMPLD13;/* offset: 0x0078 size: 16 bit */
10998   
10999           /* Comparator Load Register 2 */
11000           mcTIMER_CMPLD2_16B_tag CMPLD23;/* offset: 0x007A size: 16 bit */
11001   
11002           /* Compare and Capture Control Register */
11003           mcTIMER_CCCTRL_16B_tag CCCTRL3;/* offset: 0x007C size: 16 bit */
11004   
11005           /* Input Filter Register */
11006           mcTIMER_FILT_16B_tag FILT3;    /* offset: 0x007E size: 16 bit */
11007   
11008           /* Compare Register 1 */
11009           mcTIMER_COMP1_16B_tag COMP14;  /* offset: 0x0080 size: 16 bit */
11010   
11011           /* Compare Register 2 */
11012           mcTIMER_COMP2_16B_tag COMP24;  /* offset: 0x0082 size: 16 bit */
11013   
11014           /* Capture Register 1 */
11015           mcTIMER_CAPT1_16B_tag CAPT14;  /* offset: 0x0084 size: 16 bit */
11016   
11017           /* Capture Register 2 */
11018           mcTIMER_CAPT2_16B_tag CAPT24;  /* offset: 0x0086 size: 16 bit */
11019   
11020           /* Load Register */
11021           mcTIMER_LOAD_16B_tag LOAD4;    /* offset: 0x0088 size: 16 bit */
11022   
11023           /* Hold Register */
11024           mcTIMER_HOLD_16B_tag HOLD4;    /* offset: 0x008A size: 16 bit */
11025   
11026           /* Counter Register */
11027           mcTIMER_CNTR_16B_tag CNTR4;    /* offset: 0x008C size: 16 bit */
11028   
11029           /* Control Register */
11030           mcTIMER_CTRL1_16B_tag CTRL14;  /* offset: 0x008E size: 16 bit */
11031   
11032           /* Control Register 2 */
11033           mcTIMER_CTRL2_16B_tag CTRL24;  /* offset: 0x0090 size: 16 bit */
11034   
11035           /* Control Register 3 */
11036           mcTIMER_CTRL3_16B_tag CTRL34;  /* offset: 0x0092 size: 16 bit */
11037   
11038           /* Status Register */
11039           mcTIMER_STS_16B_tag STS4;      /* offset: 0x0094 size: 16 bit */
11040   
11041           /* Interrupt and DMA Enable Register */
11042           mcTIMER_INTDMA_16B_tag INTDMA4;/* offset: 0x0096 size: 16 bit */
11043   
11044           /* Comparator Load Register 1 */
11045           mcTIMER_CMPLD1_16B_tag CMPLD14;/* offset: 0x0098 size: 16 bit */
11046   
11047           /* Comparator Load Register 2 */
11048           mcTIMER_CMPLD2_16B_tag CMPLD24;/* offset: 0x009A size: 16 bit */
11049   
11050           /* Compare and Capture Control Register */
11051           mcTIMER_CCCTRL_16B_tag CCCTRL4;/* offset: 0x009C size: 16 bit */
11052   
11053           /* Input Filter Register */
11054           mcTIMER_FILT_16B_tag FILT4;    /* offset: 0x009E size: 16 bit */
11055   
11056           /* Compare Register 1 */
11057           mcTIMER_COMP1_16B_tag COMP15;  /* offset: 0x00A0 size: 16 bit */
11058   
11059           /* Compare Register 2 */
11060           mcTIMER_COMP2_16B_tag COMP25;  /* offset: 0x00A2 size: 16 bit */
11061   
11062           /* Capture Register 1 */
11063           mcTIMER_CAPT1_16B_tag CAPT15;  /* offset: 0x00A4 size: 16 bit */
11064   
11065           /* Capture Register 2 */
11066           mcTIMER_CAPT2_16B_tag CAPT25;  /* offset: 0x00A6 size: 16 bit */
11067   
11068           /* Load Register */
11069           mcTIMER_LOAD_16B_tag LOAD5;    /* offset: 0x00A8 size: 16 bit */
11070   
11071           /* Hold Register */
11072           mcTIMER_HOLD_16B_tag HOLD5;    /* offset: 0x00AA size: 16 bit */
11073   
11074           /* Counter Register */
11075           mcTIMER_CNTR_16B_tag CNTR5;    /* offset: 0x00AC size: 16 bit */
11076   
11077           /* Control Register */
11078           mcTIMER_CTRL1_16B_tag CTRL15;  /* offset: 0x00AE size: 16 bit */
11079   
11080           /* Control Register 2 */
11081           mcTIMER_CTRL2_16B_tag CTRL25;  /* offset: 0x00B0 size: 16 bit */
11082   
11083           /* Control Register 3 */
11084           mcTIMER_CTRL3_16B_tag CTRL35;  /* offset: 0x00B2 size: 16 bit */
11085   
11086           /* Status Register */
11087           mcTIMER_STS_16B_tag STS5;      /* offset: 0x00B4 size: 16 bit */
11088   
11089           /* Interrupt and DMA Enable Register */
11090           mcTIMER_INTDMA_16B_tag INTDMA5;/* offset: 0x00B6 size: 16 bit */
11091   
11092           /* Comparator Load Register 1 */
11093           mcTIMER_CMPLD1_16B_tag CMPLD15;/* offset: 0x00B8 size: 16 bit */
11094   
11095           /* Comparator Load Register 2 */
11096           mcTIMER_CMPLD2_16B_tag CMPLD25;/* offset: 0x00BA size: 16 bit */
11097   
11098           /* Compare and Capture Control Register */
11099           mcTIMER_CCCTRL_16B_tag CCCTRL5;/* offset: 0x00BC size: 16 bit */
11100   
11101           /* Input Filter Register */
11102           mcTIMER_FILT_16B_tag FILT5;    /* offset: 0x00BE size: 16 bit */
11103         };
11104       };
11105   
11106       int8_t mcTIMER_reserved_00C0[64];
11107   
11108       /* Watchdog Time-out Register */
11109       mcTIMER_WDTOL_16B_tag WDTOL;       /* offset: 0x0100 size: 16 bit */
11110   
11111       /* Watchdog Time-out Register */
11112       mcTIMER_WDTOH_16B_tag WDTOH;       /* offset: 0x0102 size: 16 bit */
11113   
11114       /* Fault Control Register */
11115       mcTIMER_FCTRL_16B_tag FCTRL;       /* offset: 0x0104 size: 16 bit */
11116   
11117       /* Fault Status Register */
11118       mcTIMER_FSTS_16B_tag FSTS;         /* offset: 0x0106 size: 16 bit */
11119   
11120       /* Fault Filter Registers */
11121       mcTIMER_FFILT_16B_tag FFILT;       /* offset: 0x0108 size: 16 bit */
11122       int8_t mcTIMER_reserved_010A[2];
11123   
11124       /* Channel Enable Registers */
11125       mcTIMER_ENBL_16B_tag ENBL;         /* offset: 0x010C size: 16 bit */
11126       int8_t mcTIMER_reserved_010E[2];
11127       union {
11128         mcTIMER_DREQ_16B_tag DREQ[4];    /* offset: 0x0110  (0x0002 x 4) */
11129         struct {
11130           /* DMA Request 0 Select Registers */
11131           mcTIMER_DREQ0_16B_tag DREQ0;   /* offset: 0x0110 size: 16 bit */
11132   
11133           /* DMA Request 1 Select Registers */
11134           mcTIMER_DREQ1_16B_tag DREQ1;   /* offset: 0x0112 size: 16 bit */
11135   
11136           /* DMA Request 2 Select Registers */
11137           mcTIMER_DREQ2_16B_tag DREQ2;   /* offset: 0x0114 size: 16 bit */
11138   
11139           /* DMA Request 3 Select Registers */
11140           mcTIMER_DREQ3_16B_tag DREQ3;   /* offset: 0x0116 size: 16 bit */
11141         };
11142       };
11143   
11144       int8_t mcTIMER_reserved_0118[16104];
11145     } mcTIMER_tag;
11146   
11147   #define mcTIMER0                       (*(volatile mcTIMER_tag *) 0xFFE18000UL)
11148   #define mcTIMER1                       (*(volatile mcTIMER_tag *) 0xFFE1C000UL)
11149   #define mcTIMER2                       (*(volatile mcTIMER_tag *) 0xFFE20000UL)
11150   
11151     /****************************************************************/
11152     /*                                                              */
11153     /* Module: mcPWM  */
11154     /*                                                              */
11155     /****************************************************************/
11156   
11157     /* Register layout for all registers CNT ... */
11158     typedef union {                      /* Counter Register */
11159       vuint16_t R;
11160     } mcPWM_CNT_16B_tag;
11161   
11162     /* Register layout for all registers INIT ... */
11163     typedef union {                      /* Initial Counter Register */
11164       vuint16_t R;
11165     } mcPWM_INIT_16B_tag;
11166   
11167     /* Register layout for all registers CTRL2 ... */
11168     typedef union {                      /* Control 2 Register */
11169       vuint16_t R;
11170       struct {
11171         vuint16_t DBGEN:1;               /* Debug Enable */
11172         vuint16_t WAITEN:1;              /* Wait Enable */
11173         vuint16_t INDEP:1;               /* Independent or Complementary Pair Operation */
11174   
11175   #ifndef USE_FIELD_ALIASES_mcPWM
11176   
11177         vuint16_t PWM23_INIT:1;          /* PWM23 Initial Value */
11178   
11179   #else
11180   
11181         vuint16_t PWMA_INIT:1;           /* deprecated name - please avoid */
11182   
11183   #endif
11184   
11185   #ifndef USE_FIELD_ALIASES_mcPWM
11186   
11187         vuint16_t PWM45_INIT:1;          /* PWM23 Initial Value */
11188   
11189   #else
11190   
11191         vuint16_t PWMB_INIT:1;           /* deprecated name - please avoid */
11192   
11193   #endif
11194   
11195         vuint16_t PWMX_INIT:1;           /* PWMX Initial Value */
11196         vuint16_t INIT_SEL:2;            /* Initialization Control Select */
11197         vuint16_t FRCEN:1;               /* Force Initialization enable */
11198         vuint16_t FORCE:1;               /* Force Initialization */
11199         vuint16_t FORCE_SEL:3;           /* Force Source Select */
11200         vuint16_t RELOAD_SEL:1;          /* Reload Source Select */
11201         vuint16_t CLK_SEL:2;             /* Clock Source Select */
11202       } B;
11203     } mcPWM_CTRL2_16B_tag;
11204   
11205     /* Register layout for all registers CTRL1 ... */
11206     typedef union {                      /* Control Register */
11207       vuint16_t R;
11208       struct {
11209         vuint16_t LDFQ:4;                /* Load Frequency */
11210         vuint16_t HALF:1;                /* Half Cycle Reload */
11211         vuint16_t FULL:1;                /* Full Cycle Reload */
11212         vuint16_t DT:2;                  /* Deadtime */
11213        vuint16_t:
11214         1;
11215         vuint16_t PRSC:3;                /* Prescaler */
11216        vuint16_t:
11217         1;
11218         vuint16_t LDMOD:1;               /* Load Mode Select */
11219        vuint16_t:
11220         1;
11221   
11222   #ifndef USE_FIELD_ALIASES_mcPWM
11223   
11224         vuint16_t DBL_EN:1;              /* Double Switching Enable */
11225   
11226   #else
11227   
11228         vuint16_t DBLEN:1;               /* deprecated name - please avoid */
11229   
11230   #endif
11231   
11232       } B;
11233     } mcPWM_CTRL1_16B_tag;
11234   
11235     /* Register layout for all registers VAL_0 ... */
11236     typedef union {                      /* Value Register */
11237       vuint16_t R;
11238     } mcPWM_VAL_16B_tag;
11239   
11240     /* Register layout for all registers VAL_1 matches VAL */
11241   
11242     /* Register layout for all registers VAL_2 matches VAL */
11243   
11244     /* Register layout for all registers VAL_3 matches VAL */
11245   
11246     /* Register layout for all registers VAL_4 matches VAL */
11247   
11248     /* Register layout for all registers VAL_5 matches VAL */
11249   
11250     /* Register layout for all registers OCTRL ... */
11251     typedef union {                      /* Output Control Register */
11252       vuint16_t R;
11253       struct {
11254         vuint16_t PWMA_IN:1;             /* PWMA Input */
11255         vuint16_t PWMB_IN:1;             /* PWMB Input */
11256         vuint16_t PWMX_IN:1;             /* PWMX Input */
11257        vuint16_t:
11258         2;
11259         vuint16_t POLA:1;                /* PWMA Output Polarity */
11260         vuint16_t POLB:1;                /* PWMB Output Polarity */
11261         vuint16_t POLX:1;                /* PWMX Output Polarity */
11262        vuint16_t:
11263         2;
11264         vuint16_t PWMAFS:2;              /* PWMA Fault State */
11265         vuint16_t PWMBFS:2;              /* PWMB Fault State */
11266         vuint16_t PWMXFS:2;              /* PWMX Fault State */
11267       } B;
11268     } mcPWM_OCTRL_16B_tag;
11269   
11270     /* Register layout for all registers STS ... */
11271     typedef union {                      /* Status Register */
11272       vuint16_t R;
11273       struct {
11274        vuint16_t:
11275         1;
11276         vuint16_t RUF:1;                 /* Registers Updated Flag */
11277         vuint16_t REF:1;                 /* Reload Error Flag */
11278         vuint16_t RF:1;                  /* Reload Flag */
11279         vuint16_t CFA1:1;                /* Capture Flag A1 */
11280         vuint16_t CFA0:1;                /* Capture Flag A0 */
11281         vuint16_t CFB1:1;                /* Capture Flag B1 */
11282         vuint16_t CFB0:1;                /* Capture Flag B0 */
11283         vuint16_t CFX1:1;                /* Capture Flag X1 */
11284         vuint16_t CFX0:1;                /* Capture Flag X0 */
11285         vuint16_t CMPF:6;                /* Compare Flags */
11286       } B;
11287     } mcPWM_STS_16B_tag;
11288   
11289     /* Register layout for all registers INTEN ... */
11290     typedef union {                      /* Interrupt Enable Registers */
11291       vuint16_t R;
11292       struct {
11293        vuint16_t:
11294         2;
11295         vuint16_t REIE:1;                /* Reload Error Interrupt Enable */
11296         vuint16_t RIE:1;                 /* Reload Interrupt Enable */
11297         vuint16_t CA1IE:1;               /* Capture A1 Interrupt Enable */
11298         vuint16_t CA0IE:1;               /* Capture A0 Interrupt Enable */
11299         vuint16_t CB1IE:1;               /* Capture B1 Interrupt Enable */
11300         vuint16_t CB0IE:1;               /* Capture B0 Interrupt Enable */
11301         vuint16_t CX1IE:1;               /* Capture X1 Interrupt Enable */
11302         vuint16_t CX0IE:1;               /* Capture X0 Interrupt Enable */
11303         vuint16_t CMPIE:6;               /* Compare Interrupt Enables */
11304       } B;
11305     } mcPWM_INTEN_16B_tag;
11306   
11307     /* Register layout for all registers DMAEN ... */
11308     typedef union {                      /* DMA Enable Registers */
11309       vuint16_t R;
11310       struct {
11311        vuint16_t:
11312         6;
11313         vuint16_t VALDE:1;               /* Value Register DMA Enable */
11314         vuint16_t FAND:1;                /* FIFO Watermark AND Control */
11315         vuint16_t CAPTDE:2;              /* Capture DMA Enable Source Select */
11316         vuint16_t CA1DE:1;               /* Capture A1 FIFO DMA Enable */
11317         vuint16_t CA0DE:1;               /* Capture A0 FIFO DMA Enable */
11318         vuint16_t CB1DE:1;               /* Capture B1 FIFO DMA Enable */
11319         vuint16_t CB0DE:1;               /* Capture B0 FIFO DMA Enable */
11320         vuint16_t CX1DE:1;               /* Capture X1 FIFO DMA Enable */
11321         vuint16_t CX0DE:1;               /* Capture X0 FIFO DMA Enable */
11322       } B;
11323     } mcPWM_DMAEN_16B_tag;
11324   
11325     /* Register layout for all registers TCTRL ... */
11326     typedef union {                      /* Output Trigger Control  Registers */
11327       vuint16_t R;
11328       struct {
11329        vuint16_t:
11330         10;
11331         vuint16_t OUT_TRIG_EN:6;         /* Output Trigger Enables */
11332       } B;
11333     } mcPWM_TCTRL_16B_tag;
11334   
11335     /* Register layout for all registers DISMAP ... */
11336     typedef union {                      /* Fault Disable Mapping   Registers */
11337       vuint16_t R;
11338       struct {
11339        vuint16_t:
11340         4;
11341         vuint16_t DISX:4;                /* PWMX Fault Disable Mask */
11342         vuint16_t DISB:4;                /* PWMB Fault Disable Mask */
11343         vuint16_t DISA:4;                /* PWMA Fault Disable Mask */
11344       } B;
11345     } mcPWM_DISMAP_16B_tag;
11346   
11347     /* Register layout for all registers DTCNT0 ... */
11348     typedef union {                      /* Deadtime Count Register 0 */
11349       vuint16_t R;
11350       struct {
11351        vuint16_t:
11352         5;
11353         vuint16_t DTCNT0:11;             /* Deadtime Count Register 0 */
11354       } B;
11355     } mcPWM_DTCNT0_16B_tag;
11356   
11357     /* Register layout for all registers DTCNT1 ... */
11358     typedef union {                      /* Deadtime Count Register 1 */
11359       vuint16_t R;
11360       struct {
11361        vuint16_t:
11362         5;
11363         vuint16_t DTCNT1:11;             /* Deadtime Count Register 1 */
11364       } B;
11365     } mcPWM_DTCNT1_16B_tag;
11366   
11367     /* Register layout for all registers CAPTCTRLX ... */
11368     typedef union {                      /* Capture Control X Register */
11369       vuint16_t R;
11370       struct {
11371         vuint16_t CX1CNT:3;              /* Capture X1 FIFO Word Count */
11372         vuint16_t CX0CNT:3;              /* Capture X0 FIFO Word Count */
11373         vuint16_t CFXWM:2;               /* Capture X FIFOs Water Mark */
11374   
11375   #ifndef USE_FIELD_ALIASES_mcPWM
11376   
11377         vuint16_t EDGCNTXEN:1;           /* Edge Counter X Enable */
11378   
11379   #else
11380   
11381         vuint16_t EDGCNTX_EN:1;          /* deprecated name - please avoid */
11382   
11383   #endif
11384   
11385   #ifndef USE_FIELD_ALIASES_mcPWM
11386   
11387         vuint16_t INPSELX:1;             /* Input Select X */
11388   
11389   #else
11390   
11391         vuint16_t INP_SELX:1;            /* deprecated name - please avoid */
11392   
11393   #endif
11394   
11395         vuint16_t EDGX1:2;               /* Edge X 1 */
11396         vuint16_t EDGX0:2;               /* Edge X 0 */
11397         vuint16_t ONESHOTX:1;            /* One Shot Mode X */
11398         vuint16_t ARMX:1;                /* Arm X */
11399       } B;
11400     } mcPWM_CAPTCTRLX_16B_tag;
11401   
11402     /* Register layout for all registers CAPTCMPX ... */
11403     typedef union {                      /* Capture Compare X Register */
11404       vuint16_t R;
11405       struct {
11406         vuint16_t EDGCNTX:8;             /* Edge Counter X */
11407         vuint16_t EDGCMPX:8;             /* Edge Compare X */
11408       } B;
11409     } mcPWM_CAPTCMPX_16B_tag;
11410   
11411     /* Register layout for all registers CVAL0 ... */
11412     typedef union {                      /* Capture Value 0 Register */
11413       vuint16_t R;
11414       struct {
11415         vuint16_t CAPTVAL0:16;           /* Captured value from submodule counter */
11416       } B;
11417     } mcPWM_CVAL0_16B_tag;
11418   
11419     /* Register layout for all registers CVAL0CYC ... */
11420     typedef union {                      /* Capture Value 0 Cycle Register */
11421       vuint16_t R;
11422       struct {
11423        vuint16_t:
11424         12;
11425         vuint16_t CVAL0CYC:4;            /* Capture Value 0 Cycle */
11426       } B;
11427     } mcPWM_CVAL0CYC_16B_tag;
11428   
11429     /* Register layout for all registers CVAL1 ... */
11430     typedef union {                      /* Capture Value 1 Register */
11431       vuint16_t R;
11432       struct {
11433         vuint16_t CAPTVAL1:16;           /* Captured value from submodule counter */
11434       } B;
11435     } mcPWM_CVAL1_16B_tag;
11436   
11437     /* Register layout for all registers CVAL1CYC ... */
11438     typedef union {                      /* Capture Value 1 Cycle Register */
11439       vuint16_t R;
11440       struct {
11441        vuint16_t:
11442         12;
11443         vuint16_t CVAL1CYC:4;            /* Capture Value 1 Cycle */
11444       } B;
11445     } mcPWM_CVAL1CYC_16B_tag;
11446   
11447     typedef union {                      /* Output Enable Register */
11448       vuint16_t R;
11449       struct {
11450        vuint16_t:
11451         4;
11452         vuint16_t PWMA_EN:4;             /* PWMA Output Enables */
11453         vuint16_t PWMB_EN:4;             /* PWMB Output Enables */
11454         vuint16_t PWMX_EN:4;             /* PWMX Output Enables */
11455       } B;
11456     } mcPWM_OUTEN_16B_tag;
11457   
11458     typedef union {                      /* Mask Register */
11459       vuint16_t R;
11460       struct {
11461        vuint16_t:
11462         4;
11463         vuint16_t MASKA:4;               /* PWMA Masks */
11464         vuint16_t MASKB:4;               /* PWMB Masks */
11465         vuint16_t MASKX:4;               /* PWMX Masks */
11466       } B;
11467     } mcPWM_MASK_16B_tag;
11468   
11469     typedef union {                      /* Software Controlled Output Register */
11470       vuint16_t R;
11471       struct {
11472        vuint16_t:
11473         8;
11474   
11475   #ifndef USE_FIELD_ALIASES_mcPWM
11476   
11477         vuint16_t OUT23_3:1;             /* Software Controlled Output 23_3 */
11478   
11479   #else
11480   
11481         vuint16_t OUTA_3:1;              /* deprecated name - please avoid */
11482   
11483   #endif
11484   
11485   #ifndef USE_FIELD_ALIASES_mcPWM
11486   
11487         vuint16_t OUT45_3:1;             /* Software Controlled Output 45_3 */
11488   
11489   #else
11490   
11491         vuint16_t OUTB_3:1;              /* deprecated name - please avoid */
11492   
11493   #endif
11494   
11495   #ifndef USE_FIELD_ALIASES_mcPWM
11496   
11497         vuint16_t OUT23_2:1;             /* Software Controlled Output 23_2 */
11498   
11499   #else
11500   
11501         vuint16_t OUTA_2:1;              /* deprecated name - please avoid */
11502   
11503   #endif
11504   
11505   #ifndef USE_FIELD_ALIASES_mcPWM
11506   
11507         vuint16_t OUT45_2:1;             /* Software Controlled Output 45_2 */
11508   
11509   #else
11510   
11511         vuint16_t OUTB_2:1;              /* deprecated name - please avoid */
11512   
11513   #endif
11514   
11515   #ifndef USE_FIELD_ALIASES_mcPWM
11516   
11517         vuint16_t OUT23_1:1;             /* Software Controlled Output 23_1 */
11518   
11519   #else
11520   
11521         vuint16_t OUTA_1:1;              /* deprecated name - please avoid */
11522   
11523   #endif
11524   
11525   #ifndef USE_FIELD_ALIASES_mcPWM
11526   
11527         vuint16_t OUT45_1:1;             /* Software Controlled Output 45_1 */
11528   
11529   #else
11530   
11531         vuint16_t OUTB_1:1;              /* deprecated name - please avoid */
11532   
11533   #endif
11534   
11535   #ifndef USE_FIELD_ALIASES_mcPWM
11536   
11537         vuint16_t OUT23_0:1;             /* Software Controlled Output 23_0 */
11538   
11539   #else
11540   
11541         vuint16_t OUTA_0:1;              /* deprecated name - please avoid */
11542   
11543   #endif
11544   
11545   #ifndef USE_FIELD_ALIASES_mcPWM
11546   
11547         vuint16_t OUT45_0:1;             /* Software Controlled Output 45_0 */
11548   
11549   #else
11550   
11551         vuint16_t OUTB_0:1;              /* deprecated name - please avoid */
11552   
11553   #endif
11554   
11555       } B;
11556     } mcPWM_SWCOUT_16B_tag;
11557   
11558     typedef union {                      /* Deadtime Source Select Register */
11559       vuint16_t R;
11560       struct {
11561   
11562   #ifndef USE_FIELD_ALIASES_mcPWM
11563   
11564         vuint16_t SEL23_3:2;             /* PWM23_3 Control Select */
11565   
11566   #else
11567   
11568         vuint16_t SELA_3:2;              /* deprecated name - please avoid */
11569   
11570   #endif
11571   
11572   #ifndef USE_FIELD_ALIASES_mcPWM
11573   
11574         vuint16_t SEL45_3:2;             /* PWM45_3 Control Select */
11575   
11576   #else
11577   
11578         vuint16_t SELB_3:2;              /* deprecated name - please avoid */
11579   
11580   #endif
11581   
11582   #ifndef USE_FIELD_ALIASES_mcPWM
11583   
11584         vuint16_t SEL23_2:2;             /* PWM23_2 Control Select */
11585   
11586   #else
11587   
11588         vuint16_t SELA_2:2;              /* deprecated name - please avoid */
11589   
11590   #endif
11591   
11592   #ifndef USE_FIELD_ALIASES_mcPWM
11593   
11594         vuint16_t SEL45_2:2;             /* PWM45_2 Control Select */
11595   
11596   #else
11597   
11598         vuint16_t SELB_2:2;              /* deprecated name - please avoid */
11599   
11600   #endif
11601   
11602   #ifndef USE_FIELD_ALIASES_mcPWM
11603   
11604         vuint16_t SEL23_1:2;             /* PWM23_1 Control Select */
11605   
11606   #else
11607   
11608         vuint16_t SELA_1:2;              /* deprecated name - please avoid */
11609   
11610   #endif
11611   
11612   #ifndef USE_FIELD_ALIASES_mcPWM
11613   
11614         vuint16_t SEL45_1:2;             /* PWM45_1 Control Select */
11615   
11616   #else
11617   
11618         vuint16_t SELB_1:2;              /* deprecated name - please avoid */
11619   
11620   #endif
11621   
11622   #ifndef USE_FIELD_ALIASES_mcPWM
11623   
11624         vuint16_t SEL23_0:2;             /* PWM23_0 Control Select */
11625   
11626   #else
11627   
11628         vuint16_t SELA_0:2;              /* deprecated name - please avoid */
11629   
11630   #endif
11631   
11632   #ifndef USE_FIELD_ALIASES_mcPWM
11633   
11634         vuint16_t SEL45_0:2;             /* PWM45_0 Control Select */
11635   
11636   #else
11637   
11638         vuint16_t SELB_0:2;              /* deprecated name - please avoid */
11639   
11640   #endif
11641   
11642       } B;
11643     } mcPWM_DTSRCSEL_16B_tag;
11644   
11645     typedef union {                      /* Master Control Register */
11646       vuint16_t R;
11647       struct {
11648         vuint16_t IPOL:4;                /* Current Polarity */
11649         vuint16_t RUN:4;                 /* Run */
11650   
11651   #ifndef USE_FIELD_ALIASES_mcPWM
11652   
11653         vuint16_t CLOK:4;                /* Clear Load Okay */
11654   
11655   #else
11656   
11657         vuint16_t CLDOK:4;               /* deprecated name - please avoid */
11658   
11659   #endif
11660   
11661         vuint16_t LDOK:4;                /* Load Okay */
11662       } B;
11663     } mcPWM_MCTRL_16B_tag;
11664   
11665     typedef union {                      /* Fault Control Register */
11666       vuint16_t R;
11667       struct {
11668         vuint16_t FLVL:4;                /* Fault Level */
11669         vuint16_t FAUTO:4;               /* Automatic Fault Clearing */
11670         vuint16_t FSAFE:4;               /* Fault Safety Mode */
11671         vuint16_t FIE:4;                 /* Fault Interrupt Enables */
11672       } B;
11673     } mcPWM_FCTRL_16B_tag;
11674   
11675     typedef union {                      /* Fault Status Register */
11676       vuint16_t R;
11677       struct {
11678        vuint16_t:
11679         3;
11680         vuint16_t FTEST:1;               /* Fault Test */
11681         vuint16_t FFPIN:4;               /* Filtered Fault Pins */
11682        vuint16_t:
11683         4;
11684         vuint16_t FFLAG:4;               /* Fault Flags */
11685       } B;
11686     } mcPWM_FSTS_16B_tag;
11687   
11688     typedef union {                      /* Fault Filter Register */
11689       vuint16_t R;
11690       struct {
11691        vuint16_t:
11692         5;
11693         vuint16_t FILT_CNT:3;            /* Fault Filter Count */
11694         vuint16_t FILT_PER:8;            /* Fault Filter Period */
11695       } B;
11696     } mcPWM_FFILT_16B_tag;
11697   
11698     typedef struct mcPWM_SUBMOD_struct_tag {
11699       /* Counter Register */
11700       mcPWM_CNT_16B_tag CNT;             /* relative offset: 0x0000 */
11701   
11702       /* Initial Counter Register */
11703       mcPWM_INIT_16B_tag INIT;           /* relative offset: 0x0002 */
11704   
11705       /* Control 2 Register */
11706       mcPWM_CTRL2_16B_tag CTRL2;         /* relative offset: 0x0004 */
11707       union {
11708         /* Control Register */
11709         mcPWM_CTRL1_16B_tag CTRL1;       /* relative offset: 0x0006 */
11710         mcPWM_CTRL1_16B_tag CTRL;        /* deprecated - please avoid */
11711       };
11712   
11713       union {
11714         mcPWM_VAL_16B_tag VAL[6];        /* relative offset: 0x0008 */
11715         struct {
11716           /* Value Register */
11717           mcPWM_VAL_16B_tag VAL_0;       /* relative offset: 0x0008 */
11718           mcPWM_VAL_16B_tag VAL_1;       /* relative offset: 0x000A */
11719           mcPWM_VAL_16B_tag VAL_2;       /* relative offset: 0x000C */
11720           mcPWM_VAL_16B_tag VAL_3;       /* relative offset: 0x000E */
11721           mcPWM_VAL_16B_tag VAL_4;       /* relative offset: 0x0010 */
11722           mcPWM_VAL_16B_tag VAL_5;       /* relative offset: 0x0012 */
11723         };
11724       };
11725   
11726       int8_t mcPWM_SUBMOD_reserved_0014[4];
11727   
11728       /* Output Control Register */
11729       mcPWM_OCTRL_16B_tag OCTRL;         /* relative offset: 0x0018 */
11730   
11731       /* Status Register */
11732       mcPWM_STS_16B_tag STS;             /* relative offset: 0x001A */
11733   
11734       /* Interrupt Enable Registers */
11735       mcPWM_INTEN_16B_tag INTEN;         /* relative offset: 0x001C */
11736   
11737       /* DMA Enable Registers */
11738       mcPWM_DMAEN_16B_tag DMAEN;         /* relative offset: 0x001E */
11739   
11740       /* Output Trigger Control  Registers */
11741       mcPWM_TCTRL_16B_tag TCTRL;         /* relative offset: 0x0020 */
11742   
11743       /* Fault Disable Mapping   Registers */
11744       mcPWM_DISMAP_16B_tag DISMAP;       /* relative offset: 0x0022 */
11745   
11746       /* Deadtime Count Register 0 */
11747       mcPWM_DTCNT0_16B_tag DTCNT0;       /* relative offset: 0x0024 */
11748   
11749       /* Deadtime Count Register 1 */
11750       mcPWM_DTCNT1_16B_tag DTCNT1;       /* relative offset: 0x0026 */
11751       int8_t mcPWM_SUBMOD_reserved_0028[8];
11752   
11753       /* Capture Control X Register */
11754       mcPWM_CAPTCTRLX_16B_tag CAPTCTRLX; /* relative offset: 0x0030 */
11755       union {
11756         /* Capture Compare X Register */
11757         mcPWM_CAPTCMPX_16B_tag CAPTCMPX; /* relative offset: 0x0032 */
11758         mcPWM_CAPTCMPX_16B_tag CAPTCOMPX;/* deprecated - please avoid */
11759       };
11760   
11761       /* Capture Value 0 Register */
11762       mcPWM_CVAL0_16B_tag CVAL0;         /* relative offset: 0x0034 */
11763       union {
11764         /* Capture Value 0 Cycle Register */
11765         mcPWM_CVAL0CYC_16B_tag CVAL0CYC; /* relative offset: 0x0036 */
11766         mcPWM_CVAL0CYC_16B_tag CVAL0C;   /* deprecated - please avoid */
11767       };
11768   
11769       /* Capture Value 1 Register */
11770       mcPWM_CVAL1_16B_tag CVAL1;         /* relative offset: 0x0038 */
11771       union {
11772         /* Capture Value 1 Cycle Register */
11773         mcPWM_CVAL1CYC_16B_tag CVAL1CYC; /* relative offset: 0x003A */
11774         mcPWM_CVAL1CYC_16B_tag CVAL1C;   /* deprecated - please avoid */
11775       };
11776   
11777       int8_t mcPWM_SUBMOD_reserved_003C[20];
11778     } mcPWM_SUBMOD_tag;
11779   
11780     typedef struct mcPWM_struct_tag {
11781       union {
11782         /*  Register set SUBMOD */
11783         mcPWM_SUBMOD_tag SUBMOD[4];      /* offset: 0x0000  (0x0050 x 4) */
11784   
11785         /*  Alias name for SUBMOD */
11786         mcPWM_SUBMOD_tag SUB[4];         /* deprecated - please avoid */
11787         struct {
11788           /* Counter Register */
11789           mcPWM_CNT_16B_tag CNT0;        /* offset: 0x0000 size: 16 bit */
11790   
11791           /* Initial Counter Register */
11792           mcPWM_INIT_16B_tag INIT0;      /* offset: 0x0002 size: 16 bit */
11793   
11794           /* Control 2 Register */
11795           mcPWM_CTRL2_16B_tag CTRL20;    /* offset: 0x0004 size: 16 bit */
11796   
11797           /* Control Register */
11798           mcPWM_CTRL1_16B_tag CTRL10;    /* offset: 0x0006 size: 16 bit */
11799   
11800           /* Value Register */
11801           mcPWM_VAL_16B_tag VAL_00;      /* offset: 0x0008 size: 16 bit */
11802   
11803           /* Value Register */
11804           mcPWM_VAL_16B_tag VAL_10;      /* offset: 0x000A size: 16 bit */
11805   
11806           /* Value Register */
11807           mcPWM_VAL_16B_tag VAL_20;      /* offset: 0x000C size: 16 bit */
11808   
11809           /* Value Register */
11810           mcPWM_VAL_16B_tag VAL_30;      /* offset: 0x000E size: 16 bit */
11811   
11812           /* Value Register */
11813           mcPWM_VAL_16B_tag VAL_40;      /* offset: 0x0010 size: 16 bit */
11814   
11815           /* Value Register */
11816           mcPWM_VAL_16B_tag VAL_50;      /* offset: 0x0012 size: 16 bit */
11817           int8_t mcPWM_reserved_0014_I2[4];
11818   
11819           /* Output Control Register */
11820           mcPWM_OCTRL_16B_tag OCTRL0;    /* offset: 0x0018 size: 16 bit */
11821   
11822           /* Status Register */
11823           mcPWM_STS_16B_tag STS0;        /* offset: 0x001A size: 16 bit */
11824   
11825           /* Interrupt Enable Registers */
11826           mcPWM_INTEN_16B_tag INTEN0;    /* offset: 0x001C size: 16 bit */
11827   
11828           /* DMA Enable Registers */
11829           mcPWM_DMAEN_16B_tag DMAEN0;    /* offset: 0x001E size: 16 bit */
11830   
11831           /* Output Trigger Control  Registers */
11832           mcPWM_TCTRL_16B_tag TCTRL0;    /* offset: 0x0020 size: 16 bit */
11833   
11834           /* Fault Disable Mapping   Registers */
11835           mcPWM_DISMAP_16B_tag DISMAP0;  /* offset: 0x0022 size: 16 bit */
11836   
11837           /* Deadtime Count Register 0 */
11838           mcPWM_DTCNT0_16B_tag DTCNT00;  /* offset: 0x0024 size: 16 bit */
11839   
11840           /* Deadtime Count Register 1 */
11841           mcPWM_DTCNT1_16B_tag DTCNT10;  /* offset: 0x0026 size: 16 bit */
11842           int8_t mcPWM_reserved_0028_I2[8];
11843   
11844           /* Capture Control X Register */
11845           mcPWM_CAPTCTRLX_16B_tag CAPTCTRLX0;/* offset: 0x0030 size: 16 bit */
11846   
11847           /* Capture Compare X Register */
11848           mcPWM_CAPTCMPX_16B_tag CAPTCMPX0;/* offset: 0x0032 size: 16 bit */
11849   
11850           /* Capture Value 0 Register */
11851           mcPWM_CVAL0_16B_tag CVAL00;    /* offset: 0x0034 size: 16 bit */
11852   
11853           /* Capture Value 0 Cycle Register */
11854           mcPWM_CVAL0CYC_16B_tag CVAL0CYC0;/* offset: 0x0036 size: 16 bit */
11855   
11856           /* Capture Value 1 Register */
11857           mcPWM_CVAL1_16B_tag CVAL10;    /* offset: 0x0038 size: 16 bit */
11858   
11859           /* Capture Value 1 Cycle Register */
11860           mcPWM_CVAL1CYC_16B_tag CVAL1CYC0;/* offset: 0x003A size: 16 bit */
11861           int8_t mcPWM_reserved_003C_I2[20];
11862   
11863           /* Counter Register */
11864           mcPWM_CNT_16B_tag CNT1;        /* offset: 0x0050 size: 16 bit */
11865   
11866           /* Initial Counter Register */
11867           mcPWM_INIT_16B_tag INIT1;      /* offset: 0x0052 size: 16 bit */
11868   
11869           /* Control 2 Register */
11870           mcPWM_CTRL2_16B_tag CTRL21;    /* offset: 0x0054 size: 16 bit */
11871   
11872           /* Control Register */
11873           mcPWM_CTRL1_16B_tag CTRL11;    /* offset: 0x0056 size: 16 bit */
11874   
11875           /* Value Register */
11876           mcPWM_VAL_16B_tag VAL_01;      /* offset: 0x0058 size: 16 bit */
11877   
11878           /* Value Register */
11879           mcPWM_VAL_16B_tag VAL_11;      /* offset: 0x005A size: 16 bit */
11880   
11881           /* Value Register */
11882           mcPWM_VAL_16B_tag VAL_21;      /* offset: 0x005C size: 16 bit */
11883   
11884           /* Value Register */
11885           mcPWM_VAL_16B_tag VAL_31;      /* offset: 0x005E size: 16 bit */
11886   
11887           /* Value Register */
11888           mcPWM_VAL_16B_tag VAL_41;      /* offset: 0x0060 size: 16 bit */
11889   
11890           /* Value Register */
11891           mcPWM_VAL_16B_tag VAL_51;      /* offset: 0x0062 size: 16 bit */
11892           int8_t mcPWM_reserved_0064_I2[4];
11893   
11894           /* Output Control Register */
11895           mcPWM_OCTRL_16B_tag OCTRL1;    /* offset: 0x0068 size: 16 bit */
11896   
11897           /* Status Register */
11898           mcPWM_STS_16B_tag STS1;        /* offset: 0x006A size: 16 bit */
11899   
11900           /* Interrupt Enable Registers */
11901           mcPWM_INTEN_16B_tag INTEN1;    /* offset: 0x006C size: 16 bit */
11902   
11903           /* DMA Enable Registers */
11904           mcPWM_DMAEN_16B_tag DMAEN1;    /* offset: 0x006E size: 16 bit */
11905   
11906           /* Output Trigger Control  Registers */
11907           mcPWM_TCTRL_16B_tag TCTRL1;    /* offset: 0x0070 size: 16 bit */
11908   
11909           /* Fault Disable Mapping   Registers */
11910           mcPWM_DISMAP_16B_tag DISMAP1;  /* offset: 0x0072 size: 16 bit */
11911   
11912           /* Deadtime Count Register 0 */
11913           mcPWM_DTCNT0_16B_tag DTCNT01;  /* offset: 0x0074 size: 16 bit */
11914   
11915           /* Deadtime Count Register 1 */
11916           mcPWM_DTCNT1_16B_tag DTCNT11;  /* offset: 0x0076 size: 16 bit */
11917           int8_t mcPWM_reserved_0078_I2[8];
11918   
11919           /* Capture Control X Register */
11920           mcPWM_CAPTCTRLX_16B_tag CAPTCTRLX1;/* offset: 0x0080 size: 16 bit */
11921   
11922           /* Capture Compare X Register */
11923           mcPWM_CAPTCMPX_16B_tag CAPTCMPX1;/* offset: 0x0082 size: 16 bit */
11924   
11925           /* Capture Value 0 Register */
11926           mcPWM_CVAL0_16B_tag CVAL01;    /* offset: 0x0084 size: 16 bit */
11927   
11928           /* Capture Value 0 Cycle Register */
11929           mcPWM_CVAL0CYC_16B_tag CVAL0CYC1;/* offset: 0x0086 size: 16 bit */
11930   
11931           /* Capture Value 1 Register */
11932           mcPWM_CVAL1_16B_tag CVAL11;    /* offset: 0x0088 size: 16 bit */
11933   
11934           /* Capture Value 1 Cycle Register */
11935           mcPWM_CVAL1CYC_16B_tag CVAL1CYC1;/* offset: 0x008A size: 16 bit */
11936           int8_t mcPWM_reserved_008C_I2[20];
11937   
11938           /* Counter Register */
11939           mcPWM_CNT_16B_tag CNT2;        /* offset: 0x00A0 size: 16 bit */
11940   
11941           /* Initial Counter Register */
11942           mcPWM_INIT_16B_tag INIT2;      /* offset: 0x00A2 size: 16 bit */
11943   
11944           /* Control 2 Register */
11945           mcPWM_CTRL2_16B_tag CTRL22;    /* offset: 0x00A4 size: 16 bit */
11946   
11947           /* Control Register */
11948           mcPWM_CTRL1_16B_tag CTRL12;    /* offset: 0x00A6 size: 16 bit */
11949   
11950           /* Value Register */
11951           mcPWM_VAL_16B_tag VAL_02;      /* offset: 0x00A8 size: 16 bit */
11952   
11953           /* Value Register */
11954           mcPWM_VAL_16B_tag VAL_12;      /* offset: 0x00AA size: 16 bit */
11955   
11956           /* Value Register */
11957           mcPWM_VAL_16B_tag VAL_22;      /* offset: 0x00AC size: 16 bit */
11958   
11959           /* Value Register */
11960           mcPWM_VAL_16B_tag VAL_32;      /* offset: 0x00AE size: 16 bit */
11961   
11962           /* Value Register */
11963           mcPWM_VAL_16B_tag VAL_42;      /* offset: 0x00B0 size: 16 bit */
11964   
11965           /* Value Register */
11966           mcPWM_VAL_16B_tag VAL_52;      /* offset: 0x00B2 size: 16 bit */
11967           int8_t mcPWM_reserved_00B4_I2[4];
11968   
11969           /* Output Control Register */
11970           mcPWM_OCTRL_16B_tag OCTRL2;    /* offset: 0x00B8 size: 16 bit */
11971   
11972           /* Status Register */
11973           mcPWM_STS_16B_tag STS2;        /* offset: 0x00BA size: 16 bit */
11974   
11975           /* Interrupt Enable Registers */
11976           mcPWM_INTEN_16B_tag INTEN2;    /* offset: 0x00BC size: 16 bit */
11977   
11978           /* DMA Enable Registers */
11979           mcPWM_DMAEN_16B_tag DMAEN2;    /* offset: 0x00BE size: 16 bit */
11980   
11981           /* Output Trigger Control  Registers */
11982           mcPWM_TCTRL_16B_tag TCTRL2;    /* offset: 0x00C0 size: 16 bit */
11983   
11984           /* Fault Disable Mapping   Registers */
11985           mcPWM_DISMAP_16B_tag DISMAP2;  /* offset: 0x00C2 size: 16 bit */
11986   
11987           /* Deadtime Count Register 0 */
11988           mcPWM_DTCNT0_16B_tag DTCNT02;  /* offset: 0x00C4 size: 16 bit */
11989   
11990           /* Deadtime Count Register 1 */
11991           mcPWM_DTCNT1_16B_tag DTCNT12;  /* offset: 0x00C6 size: 16 bit */
11992           int8_t mcPWM_reserved_00C8_I2[8];
11993   
11994           /* Capture Control X Register */
11995           mcPWM_CAPTCTRLX_16B_tag CAPTCTRLX2;/* offset: 0x00D0 size: 16 bit */
11996   
11997           /* Capture Compare X Register */
11998           mcPWM_CAPTCMPX_16B_tag CAPTCMPX2;/* offset: 0x00D2 size: 16 bit */
11999   
12000           /* Capture Value 0 Register */
12001           mcPWM_CVAL0_16B_tag CVAL02;    /* offset: 0x00D4 size: 16 bit */
12002   
12003           /* Capture Value 0 Cycle Register */
12004           mcPWM_CVAL0CYC_16B_tag CVAL0CYC2;/* offset: 0x00D6 size: 16 bit */
12005   
12006           /* Capture Value 1 Register */
12007           mcPWM_CVAL1_16B_tag CVAL12;    /* offset: 0x00D8 size: 16 bit */
12008   
12009           /* Capture Value 1 Cycle Register */
12010           mcPWM_CVAL1CYC_16B_tag CVAL1CYC2;/* offset: 0x00DA size: 16 bit */
12011           int8_t mcPWM_reserved_00DC_I2[20];
12012   
12013           /* Counter Register */
12014           mcPWM_CNT_16B_tag CNT3;        /* offset: 0x00F0 size: 16 bit */
12015   
12016           /* Initial Counter Register */
12017           mcPWM_INIT_16B_tag INIT3;      /* offset: 0x00F2 size: 16 bit */
12018   
12019           /* Control 2 Register */
12020           mcPWM_CTRL2_16B_tag CTRL23;    /* offset: 0x00F4 size: 16 bit */
12021   
12022           /* Control Register */
12023           mcPWM_CTRL1_16B_tag CTRL13;    /* offset: 0x00F6 size: 16 bit */
12024   
12025           /* Value Register */
12026           mcPWM_VAL_16B_tag VAL_03;      /* offset: 0x00F8 size: 16 bit */
12027   
12028           /* Value Register */
12029           mcPWM_VAL_16B_tag VAL_13;      /* offset: 0x00FA size: 16 bit */
12030   
12031           /* Value Register */
12032           mcPWM_VAL_16B_tag VAL_23;      /* offset: 0x00FC size: 16 bit */
12033   
12034           /* Value Register */
12035           mcPWM_VAL_16B_tag VAL_33;      /* offset: 0x00FE size: 16 bit */
12036   
12037           /* Value Register */
12038           mcPWM_VAL_16B_tag VAL_43;      /* offset: 0x0100 size: 16 bit */
12039   
12040           /* Value Register */
12041           mcPWM_VAL_16B_tag VAL_53;      /* offset: 0x0102 size: 16 bit */
12042           int8_t mcPWM_reserved_0104_I2[4];
12043   
12044           /* Output Control Register */
12045           mcPWM_OCTRL_16B_tag OCTRL3;    /* offset: 0x0108 size: 16 bit */
12046   
12047           /* Status Register */
12048           mcPWM_STS_16B_tag STS3;        /* offset: 0x010A size: 16 bit */
12049   
12050           /* Interrupt Enable Registers */
12051           mcPWM_INTEN_16B_tag INTEN3;    /* offset: 0x010C size: 16 bit */
12052   
12053           /* DMA Enable Registers */
12054           mcPWM_DMAEN_16B_tag DMAEN3;    /* offset: 0x010E size: 16 bit */
12055   
12056           /* Output Trigger Control  Registers */
12057           mcPWM_TCTRL_16B_tag TCTRL3;    /* offset: 0x0110 size: 16 bit */
12058   
12059           /* Fault Disable Mapping   Registers */
12060           mcPWM_DISMAP_16B_tag DISMAP3;  /* offset: 0x0112 size: 16 bit */
12061   
12062           /* Deadtime Count Register 0 */
12063           mcPWM_DTCNT0_16B_tag DTCNT03;  /* offset: 0x0114 size: 16 bit */
12064   
12065           /* Deadtime Count Register 1 */
12066           mcPWM_DTCNT1_16B_tag DTCNT13;  /* offset: 0x0116 size: 16 bit */
12067           int8_t mcPWM_reserved_0118_I2[8];
12068   
12069           /* Capture Control X Register */
12070           mcPWM_CAPTCTRLX_16B_tag CAPTCTRLX3;/* offset: 0x0120 size: 16 bit */
12071   
12072           /* Capture Compare X Register */
12073           mcPWM_CAPTCMPX_16B_tag CAPTCMPX3;/* offset: 0x0122 size: 16 bit */
12074   
12075           /* Capture Value 0 Register */
12076           mcPWM_CVAL0_16B_tag CVAL03;    /* offset: 0x0124 size: 16 bit */
12077   
12078           /* Capture Value 0 Cycle Register */
12079           mcPWM_CVAL0CYC_16B_tag CVAL0CYC3;/* offset: 0x0126 size: 16 bit */
12080   
12081           /* Capture Value 1 Register */
12082           mcPWM_CVAL1_16B_tag CVAL13;    /* offset: 0x0128 size: 16 bit */
12083   
12084           /* Capture Value 1 Cycle Register */
12085           mcPWM_CVAL1CYC_16B_tag CVAL1CYC3;/* offset: 0x012A size: 16 bit */
12086           int8_t mcPWM_reserved_012C_E2[20];
12087         };
12088       };
12089   
12090       /* Output Enable Register */
12091       mcPWM_OUTEN_16B_tag OUTEN;         /* offset: 0x0140 size: 16 bit */
12092   
12093       /* Mask Register */
12094       mcPWM_MASK_16B_tag MASK;           /* offset: 0x0142 size: 16 bit */
12095   
12096       /* Software Controlled Output Register */
12097       mcPWM_SWCOUT_16B_tag SWCOUT;       /* offset: 0x0144 size: 16 bit */
12098   
12099       /* Deadtime Source Select Register */
12100       mcPWM_DTSRCSEL_16B_tag DTSRCSEL;   /* offset: 0x0146 size: 16 bit */
12101   
12102       /* Master Control Register */
12103       mcPWM_MCTRL_16B_tag MCTRL;         /* offset: 0x0148 size: 16 bit */
12104       int8_t mcPWM_reserved_014A[2];
12105   
12106       /* Fault Control Register */
12107       mcPWM_FCTRL_16B_tag FCTRL;         /* offset: 0x014C size: 16 bit */
12108   
12109       /* Fault Status Register */
12110       mcPWM_FSTS_16B_tag FSTS;           /* offset: 0x014E size: 16 bit */
12111   
12112       /* Fault Filter Register */
12113       mcPWM_FFILT_16B_tag FFILT;         /* offset: 0x0150 size: 16 bit */
12114       int8_t mcPWM_reserved_0152[16046];
12115     } mcPWM_tag;
12116   
12117   #define mcPWM_A                        (*(volatile mcPWM_tag *) 0xFFE24000UL)
12118   #define mcPWM_B                        (*(volatile mcPWM_tag *) 0xFFE28000UL)
12119   
12120     /****************************************************************/
12121     /*                                                              */
12122     /* Module: LINFLEX  */
12123     /*                                                              */
12124     /****************************************************************/
12125     typedef union {                      /* LIN Control Register */
12126       vuint32_t R;
12127       struct {
12128        vuint32_t:
12129         16;
12130         vuint32_t CCD:1;                 /* Checksum Calculation Disable */
12131         vuint32_t CFD:1;                 /* Checksum Field Disable */
12132         vuint32_t LASE:1;                /* LIN Auto Synchronization Enable */
12133   
12134   #ifndef USE_FIELD_ALIASES_LINFLEX
12135   
12136         vuint32_t AUTOWU:1;              /* Auto Wake Up */
12137   
12138   #else
12139   
12140         vuint32_t AWUM:1;                /* deprecated name - please avoid */
12141   
12142   #endif
12143   
12144         vuint32_t MBL:4;                 /* Master Break Length */
12145         vuint32_t BF:1;                  /* By-Pass Filter */
12146   
12147   #ifndef USE_FIELD_ALIASES_LINFLEX
12148   
12149         vuint32_t SLFM:1;                /* Selftest Mode */
12150   
12151   #else
12152   
12153         vuint32_t SFTM:1;                /* deprecated name - please avoid */
12154   
12155   #endif
12156   
12157         vuint32_t LBKM:1;                /* Loopback Mode */
12158         vuint32_t MME:1;                 /* Master Mode Enable */
12159   
12160   #ifndef USE_FIELD_ALIASES_LINFLEX
12161   
12162         vuint32_t SSBL:1;                /* Slave Mode Synch Break Length */
12163   
12164   #else
12165   
12166         vuint32_t SSDT:1;                /* deprecated name - please avoid */
12167   
12168   #endif
12169   
12170         vuint32_t RBLM:1;                /* Receiver Buffer Locked Mode */
12171         vuint32_t SLEEP:1;               /* Sleep Mode Request */
12172         vuint32_t INIT:1;                /* Initialization Mode Request */
12173       } B;
12174     } LINFLEX_LINCR1_32B_tag;
12175   
12176     typedef union {                      /* LIN Interrupt Enable Register */
12177       vuint32_t R;
12178       struct {
12179        vuint32_t:
12180         16;
12181         vuint32_t SZIE:1;                /* Stuck at Zero Interrupt Enable */
12182         vuint32_t OCIE:1;                /* Output Compare Interrupt Enable */
12183         vuint32_t BEIE:1;                /* Bit Error Interrupt Enable */
12184         vuint32_t CEIE:1;                /* Checksum Error Interrupt Enable */
12185         vuint32_t HEIE:1;                /* Header Error Interrupt Enable */
12186        vuint32_t:
12187         2;
12188         vuint32_t FEIE:1;                /* Frame Error Interrupt Enable */
12189         vuint32_t BOIE:1;                /* Buffer Overrun Error Interrupt Enable */
12190         vuint32_t LSIE:1;                /* LIN State Interrupt Enable */
12191         vuint32_t WUIE:1;                /* Wakeup Interrupt Enable */
12192         vuint32_t DBFIE:1;               /* Data Buffer Full Interrupt Enable */
12193   
12194   #ifndef USE_FIELD_ALIASES_LINFLEX
12195   
12196         vuint32_t DBEIE_TOIE:1;          /* Data Buffer Empty Interrupt Enable */
12197   
12198   #else
12199   
12200         vuint32_t DBEIE:1;               /* deprecated name - please avoid */
12201   
12202   #endif
12203   
12204         vuint32_t DRIE:1;                /* Data Reception complete Interrupt Enable */
12205         vuint32_t DTIE:1;                /* Data Transmitted Interrupt Enable */
12206         vuint32_t HRIE:1;                /* Header Received Interrupt Enable */
12207       } B;
12208     } LINFLEX_LINIER_32B_tag;
12209   
12210     typedef union {                      /* LIN Status Register */
12211       vuint32_t R;
12212       struct {
12213        vuint32_t:
12214         16;
12215         vuint32_t LINS:4;                /* LIN State */
12216        vuint32_t:
12217         2;
12218         vuint32_t RMB:1;                 /* Release Message Buffer */
12219        vuint32_t:
12220         1;
12221   
12222   #ifndef USE_FIELD_ALIASES_LINFLEX
12223   
12224         vuint32_t RXBUSY:1;              /* Receiver Busy Flag */
12225   
12226   #else
12227   
12228         vuint32_t RBSY:1;                /* deprecated name - please avoid */
12229   
12230   #endif
12231   
12232   #ifndef USE_FIELD_ALIASES_LINFLEX
12233   
12234         vuint32_t RDI:1;                 /* LIN Receive Signal */
12235   
12236   #else
12237   
12238         vuint32_t RPS:1;                 /* deprecated name - please avoid */
12239   
12240   #endif
12241   
12242         vuint32_t WUF:1;                 /* Wake Up Flag */
12243         vuint32_t DBFF:1;                /* Data Buffer Full Flag */
12244         vuint32_t DBEF:1;                /* Data Buffer Empty Flag */
12245         vuint32_t DRF:1;                 /* Data Reception Completed Flag */
12246         vuint32_t DTF:1;                 /* Data Transmission Completed Flag */
12247         vuint32_t HRF:1;                 /* Header Received Flag */
12248       } B;
12249     } LINFLEX_LINSR_32B_tag;
12250   
12251     typedef union {                      /* LIN Error Status Register */
12252       vuint32_t R;
12253       struct {
12254        vuint32_t:
12255         16;
12256         vuint32_t SZF:1;                 /* Stuck at Zero Flag */
12257         vuint32_t OCF:1;                 /* Output Compare Flag */
12258         vuint32_t BEF:1;                 /* Bit Error Flag */
12259         vuint32_t CEF:1;                 /* Checksum Error Flag */
12260         vuint32_t SFEF:1;                /* Sync Field Error Flag */
12261   
12262   #ifndef USE_FIELD_ALIASES_LINFLEX
12263   
12264         vuint32_t SDEF:1;                /* Sync Delimiter Error Flag */
12265   
12266   #else
12267   
12268         vuint32_t BDEF:1;                /* deprecated name - please avoid */
12269   
12270   #endif
12271   
12272         vuint32_t IDPEF:1;               /* ID Parity Error Flag */
12273         vuint32_t FEF:1;                 /* Framing Error Flag */
12274         vuint32_t BOF:1;                 /* Buffer Overrun Flag */
12275        vuint32_t:
12276         6;
12277         vuint32_t NF:1;                  /* Noise Flag */
12278       } B;
12279     } LINFLEX_LINESR_32B_tag;
12280   
12281     typedef union {                      /* UART Mode Control Register */
12282       vuint32_t R;
12283       struct {
12284        vuint32_t:
12285         16;
12286         vuint32_t TDFL_TFC:3;            /* Transmitter Data Field Length/TX FIFO Counter */
12287         vuint32_t RDFL_RFC0:3;           /* Reception Data Field Length/RX FIFO Counter */
12288         vuint32_t RFBM:1;                /* RX FIFO/ Buffer Mode */
12289         vuint32_t TFBM:1;                /* TX FIFO/ Buffer Mode */
12290         vuint32_t WL1:1;                 /* Word Length in UART mode - bit 1 */
12291         vuint32_t PC1:1;                 /* Parity Check - bit 1 */
12292         vuint32_t RXEN:1;                /* Receiver Enable */
12293         vuint32_t TXEN:1;                /* Transmitter Enable */
12294   
12295   #ifndef USE_FIELD_ALIASES_LINFLEX
12296   
12297         vuint32_t PC0:1;                 /* Parity Check - bit 0 */
12298   
12299   #else
12300   
12301         vuint32_t OP:1;                  /* deprecated name - please avoid */
12302   
12303   #endif
12304   
12305         vuint32_t PCE:1;                 /* Parity Control Enable */
12306   
12307   #ifndef USE_FIELD_ALIASES_LINFLEX
12308   
12309         vuint32_t WL0:1;                 /* Word Length in UART Mode - bit 0 */
12310   
12311   #else
12312   
12313         vuint32_t WL:1;                  /* deprecated name - please avoid */
12314   
12315   #endif
12316   
12317         vuint32_t UART:1;                /* UART Mode */
12318       } B;
12319     } LINFLEX_UARTCR_32B_tag;
12320   
12321     typedef union {                      /* UART Mode Status Register */
12322       vuint32_t R;
12323       struct {
12324        vuint32_t:
12325         16;
12326         vuint32_t SZF:1;                 /* Stuck at Zero Flag */
12327         vuint32_t OCF:1;                 /* Output Compare Flag */
12328         vuint32_t PE:4;                  /* Parity Error Flag */
12329         vuint32_t RMB:1;                 /* Release Message Buffer */
12330         vuint32_t FEF:1;                 /* Framing Error Flag */
12331         vuint32_t BOF:1;                 /* Buffer Overrun Flag */
12332         vuint32_t RDI:1;                 /* Receiver Data Input Signal */
12333         vuint32_t WUF:1;                 /* Wakeup Flag */
12334        vuint32_t:
12335         1;
12336         vuint32_t TO:1;                  /* Time Out */
12337   
12338   #ifndef USE_FIELD_ALIASES_LINFLEX
12339   
12340         vuint32_t DRF_RFE:1;             /* Data Reception Completed Flag/RX FIFO Empty Flag */
12341   
12342   #else
12343   
12344         vuint32_t DRF:1;                 /* deprecated name - please avoid */
12345   
12346   #endif
12347   
12348   #ifndef USE_FIELD_ALIASES_LINFLEX
12349   
12350         vuint32_t DTF_TFF:1;             /* Data Transmission Completed Flag/TX FIFO Full Flag */
12351   
12352   #else
12353   
12354         vuint32_t DTF:1;                 /* deprecated name - please avoid */
12355   
12356   #endif
12357   
12358         vuint32_t NF:1;                  /* Noise Flag */
12359       } B;
12360     } LINFLEX_UARTSR_32B_tag;
12361   
12362     typedef union {                      /* LIN Time-Out Control Status Register */
12363       vuint32_t R;
12364       struct {
12365        vuint32_t:
12366         21;
12367   
12368   #ifndef USE_FIELD_ALIASES_LINFLEX
12369   
12370         vuint32_t MODE:1;                /* Time-out Counter Mode */
12371   
12372   #else
12373   
12374         vuint32_t LTOM:1;                /* deprecated name - please avoid */
12375   
12376   #endif
12377   
12378         vuint32_t IOT:1;                 /* Idle on Timeout */
12379         vuint32_t TOCE:1;                /* Time-Out Counter Enable */
12380         vuint32_t CNT:8;                 /* Counter Value */
12381       } B;
12382     } LINFLEX_LINTCSR_32B_tag;
12383   
12384     typedef union {                      /* LIN Output Compare Register */
12385       vuint32_t R;
12386       struct {
12387        vuint32_t:
12388         16;
12389         vuint32_t OC2:8;                 /* Output Compare Value 2 */
12390         vuint32_t OC1:8;                 /* Output Compare Value 1 */
12391       } B;
12392     } LINFLEX_LINOCR_32B_tag;
12393   
12394     typedef union {                      /* LIN Time-Out Control Register */
12395       vuint32_t R;
12396       struct {
12397        vuint32_t:
12398         20;
12399         vuint32_t RTO:4;                 /* Response Time-Out Value */
12400        vuint32_t:
12401         1;
12402         vuint32_t HTO:7;                 /* Header Time-Out Value */
12403       } B;
12404     } LINFLEX_LINTOCR_32B_tag;
12405   
12406     typedef union {                      /* LIN Fractional Baud Rate Register */
12407       vuint32_t R;
12408       struct {
12409        vuint32_t:
12410         28;
12411   
12412   #ifndef USE_FIELD_ALIASES_LINFLEX
12413   
12414         vuint32_t FBR:4;                 /* Fractional Baud Rates */
12415   
12416   #else
12417   
12418         vuint32_t DIV_F:4;               /* deprecated name - please avoid */
12419   
12420   #endif
12421   
12422       } B;
12423     } LINFLEX_LINFBRR_32B_tag;
12424   
12425     typedef union {                      /* LIN Integer Baud Rate Register */
12426       vuint32_t R;
12427       struct {
12428        vuint32_t:
12429         13;
12430   
12431   #ifndef USE_FIELD_ALIASES_LINFLEX
12432   
12433         vuint32_t IBR:19;                /* Integer Baud Rates */
12434   
12435   #else
12436   
12437         vuint32_t DIV_M:19;              /* deprecated name - please avoid */
12438   
12439   #endif
12440   
12441       } B;
12442     } LINFLEX_LINIBRR_32B_tag;
12443   
12444     typedef union {                      /* LIN Checksum Field Register */
12445       vuint32_t R;
12446       struct {
12447        vuint32_t:
12448         24;
12449         vuint32_t CF:8;                  /* Checksum Bits */
12450       } B;
12451     } LINFLEX_LINCFR_32B_tag;
12452   
12453     typedef union {                      /* LIN Control Register 2 */
12454       vuint32_t R;
12455       struct {
12456        vuint32_t:
12457         17;
12458         vuint32_t IOBE:1;                /* Idle on Bit Error */
12459         vuint32_t IOPE:1;                /* Idle on Identifier Parity Error */
12460         vuint32_t WURQ:1;                /* Wakeup Generate Request */
12461         vuint32_t DDRQ:1;                /* Data Discard Request */
12462         vuint32_t DTRQ:1;                /* Data Transmission Request */
12463         vuint32_t ABRQ:1;                /* Abort Request */
12464         vuint32_t HTRQ:1;                /* Header Transmission Request */
12465        vuint32_t:
12466         8;
12467       } B;
12468     } LINFLEX_LINCR2_32B_tag;
12469   
12470     typedef union {                      /* Buffer Identifier Register */
12471       vuint32_t R;
12472       struct {
12473        vuint32_t:
12474         16;
12475         vuint32_t DFL:6;                 /* Data Field Length */
12476         vuint32_t DIR:1;                 /* Direction */
12477         vuint32_t CCS:1;                 /* Classic Checksum */
12478        vuint32_t:
12479         2;
12480         vuint32_t ID:6;                  /* Identifier */
12481       } B;
12482     } LINFLEX_BIDR_32B_tag;
12483   
12484     typedef union {                      /* Buffer Data Register Least Significant */
12485       vuint32_t R;
12486       struct {
12487         vuint32_t DATA3:8;               /* Data3 */
12488         vuint32_t DATA2:8;               /* Data2 */
12489         vuint32_t DATA1:8;               /* Data1 */
12490         vuint32_t DATA0:8;               /* Data0 */
12491       } B;
12492     } LINFLEX_BDRL_32B_tag;
12493   
12494     typedef union {                      /* Buffer Data Register Most Significant */
12495       vuint32_t R;
12496       struct {
12497         vuint32_t DATA7:8;               /* Data7 */
12498         vuint32_t DATA6:8;               /* Data6 */
12499         vuint32_t DATA5:8;               /* Data5 */
12500         vuint32_t DATA4:8;               /* Data4 */
12501       } B;
12502     } LINFLEX_BDRM_32B_tag;
12503   
12504     typedef union {                      /* Identifier Filter Enable Register */
12505       vuint32_t R;
12506       struct {
12507        vuint32_t:
12508         24;
12509         vuint32_t FACT:8;                /* Filter Active */
12510       } B;
12511     } LINFLEX_IFER_32B_tag;
12512   
12513     typedef union {                      /* Identifier Filter Match Index */
12514       vuint32_t R;
12515       struct {
12516        vuint32_t:
12517         28;
12518         vuint32_t IFMI_IFMI:4;           /* Filter Match Index */
12519       } B;
12520     } LINFLEX_IFMI_32B_tag;
12521   
12522     typedef union {                      /* Identifier Filter Mode Register */
12523       vuint32_t R;
12524       struct {
12525        vuint32_t:
12526         28;
12527         vuint32_t IFM:4;                 /* Filter Mode */
12528       } B;
12529     } LINFLEX_IFMR_32B_tag;
12530   
12531     /* Register layout for all registers IFCR ... */
12532     typedef union {                      /* Identifier Filter Control Register */
12533       vuint32_t R;
12534       struct {
12535        vuint32_t:
12536         16;
12537         vuint32_t DFL:6;                 /* Data Field Length */
12538         vuint32_t DIR:1;                 /* Direction */
12539         vuint32_t CCS:1;                 /* Classic Checksum */
12540        vuint32_t:
12541         2;
12542         vuint32_t ID:6;                  /* Identifier */
12543       } B;
12544     } LINFLEX_IFCR_32B_tag;
12545   
12546     typedef union {                      /* Global Control Register */
12547       vuint32_t R;
12548       struct {
12549        vuint32_t:
12550         26;
12551         vuint32_t TDFBM:1;               /* Transmit Data First Bit MSB */
12552         vuint32_t RDFBM:1;               /* Received Data First Bit MSB */
12553         vuint32_t TDLIS:1;               /* Transmit Data Level Inversion Selection */
12554         vuint32_t RDLIS:1;               /* Received Data Level Inversion Selection */
12555         vuint32_t STOP:1;                /* 1/2 stop bit configuration */
12556         vuint32_t SR:1;                  /* Soft Reset */
12557       } B;
12558     } LINFLEX_GCR_32B_tag;
12559   
12560     typedef union {                      /* UART Preset Time Out Register */
12561       vuint32_t R;
12562       struct {
12563        vuint32_t:
12564         20;
12565         vuint32_t PTO:12;                /* Preset Time Out */
12566       } B;
12567     } LINFLEX_UARTPTO_32B_tag;
12568   
12569     typedef union {                      /* UART Current Time Out Register */
12570       vuint32_t R;
12571       struct {
12572        vuint32_t:
12573         20;
12574         vuint32_t CTO:12;                /* Current Time Out */
12575       } B;
12576     } LINFLEX_UARTCTO_32B_tag;
12577   
12578     typedef union {                      /* DMA TX Enable Register */
12579       vuint32_t R;
12580       struct {
12581        vuint32_t:
12582         17;
12583         vuint32_t DTE:15;                /* DMA Tx channel Enable */
12584       } B;
12585     } LINFLEX_DMATXE_32B_tag;
12586   
12587     typedef union {                      /* DMA RX Enable Register */
12588       vuint32_t R;
12589       struct {
12590        vuint32_t:
12591         17;
12592         vuint32_t DRE:15;                /* DMA Rx channel Enable */
12593       } B;
12594     } LINFLEX_DMARXE_32B_tag;
12595   
12596     typedef struct LINFLEX_struct_tag {
12597       /* LIN Control Register */
12598       LINFLEX_LINCR1_32B_tag LINCR1;     /* offset: 0x0000 size: 32 bit */
12599   
12600       /* LIN Interrupt Enable Register */
12601       LINFLEX_LINIER_32B_tag LINIER;     /* offset: 0x0004 size: 32 bit */
12602   
12603       /* LIN Status Register */
12604       LINFLEX_LINSR_32B_tag LINSR;       /* offset: 0x0008 size: 32 bit */
12605   
12606       /* LIN Error Status Register */
12607       LINFLEX_LINESR_32B_tag LINESR;     /* offset: 0x000C size: 32 bit */
12608   
12609       /* UART Mode Control Register */
12610       LINFLEX_UARTCR_32B_tag UARTCR;     /* offset: 0x0010 size: 32 bit */
12611   
12612       /* UART Mode Status Register */
12613       LINFLEX_UARTSR_32B_tag UARTSR;     /* offset: 0x0014 size: 32 bit */
12614   
12615       /* LIN Time-Out Control Status Register */
12616       LINFLEX_LINTCSR_32B_tag LINTCSR;   /* offset: 0x0018 size: 32 bit */
12617   
12618       /* LIN Output Compare Register */
12619       LINFLEX_LINOCR_32B_tag LINOCR;     /* offset: 0x001C size: 32 bit */
12620   
12621       /* LIN Time-Out Control Register */
12622       LINFLEX_LINTOCR_32B_tag LINTOCR;   /* offset: 0x0020 size: 32 bit */
12623   
12624       /* LIN Fractional Baud Rate Register */
12625       LINFLEX_LINFBRR_32B_tag LINFBRR;   /* offset: 0x0024 size: 32 bit */
12626   
12627       /* LIN Integer Baud Rate Register */
12628       LINFLEX_LINIBRR_32B_tag LINIBRR;   /* offset: 0x0028 size: 32 bit */
12629   
12630       /* LIN Checksum Field Register */
12631       LINFLEX_LINCFR_32B_tag LINCFR;     /* offset: 0x002C size: 32 bit */
12632   
12633       /* LIN Control Register 2 */
12634       LINFLEX_LINCR2_32B_tag LINCR2;     /* offset: 0x0030 size: 32 bit */
12635   
12636       /* Buffer Identifier Register */
12637       LINFLEX_BIDR_32B_tag BIDR;         /* offset: 0x0034 size: 32 bit */
12638   
12639       /* Buffer Data Register Least Significant */
12640       LINFLEX_BDRL_32B_tag BDRL;         /* offset: 0x0038 size: 32 bit */
12641   
12642       /* Buffer Data Register Most Significant */
12643       LINFLEX_BDRM_32B_tag BDRM;         /* offset: 0x003C size: 32 bit */
12644   
12645       /* Identifier Filter Enable Register */
12646       LINFLEX_IFER_32B_tag IFER;         /* offset: 0x0040 size: 32 bit */
12647   
12648       /* Identifier Filter Match Index */
12649       LINFLEX_IFMI_32B_tag IFMI;         /* offset: 0x0044 size: 32 bit */
12650   
12651       /* Identifier Filter Mode Register */
12652       LINFLEX_IFMR_32B_tag IFMR;         /* offset: 0x0048 size: 32 bit */
12653       union {
12654         /* Identifier Filter Control Register */
12655         LINFLEX_IFCR_32B_tag IFCR[16];   /* offset: 0x004C  (0x0004 x 16) */
12656         struct {
12657           /* Identifier Filter Control Register */
12658           LINFLEX_IFCR_32B_tag IFCR0;    /* offset: 0x004C size: 32 bit */
12659           LINFLEX_IFCR_32B_tag IFCR1;    /* offset: 0x0050 size: 32 bit */
12660           LINFLEX_IFCR_32B_tag IFCR2;    /* offset: 0x0054 size: 32 bit */
12661           LINFLEX_IFCR_32B_tag IFCR3;    /* offset: 0x0058 size: 32 bit */
12662           LINFLEX_IFCR_32B_tag IFCR4;    /* offset: 0x005C size: 32 bit */
12663           LINFLEX_IFCR_32B_tag IFCR5;    /* offset: 0x0060 size: 32 bit */
12664           LINFLEX_IFCR_32B_tag IFCR6;    /* offset: 0x0064 size: 32 bit */
12665           LINFLEX_IFCR_32B_tag IFCR7;    /* offset: 0x0068 size: 32 bit */
12666           LINFLEX_IFCR_32B_tag IFCR8;    /* offset: 0x006C size: 32 bit */
12667           LINFLEX_IFCR_32B_tag IFCR9;    /* offset: 0x0070 size: 32 bit */
12668           LINFLEX_IFCR_32B_tag IFCR10;   /* offset: 0x0074 size: 32 bit */
12669           LINFLEX_IFCR_32B_tag IFCR11;   /* offset: 0x0078 size: 32 bit */
12670           LINFLEX_IFCR_32B_tag IFCR12;   /* offset: 0x007C size: 32 bit */
12671           LINFLEX_IFCR_32B_tag IFCR13;   /* offset: 0x0080 size: 32 bit */
12672           LINFLEX_IFCR_32B_tag IFCR14;   /* offset: 0x0084 size: 32 bit */
12673           LINFLEX_IFCR_32B_tag IFCR15;   /* offset: 0x0088 size: 32 bit */
12674         };
12675       };
12676   
12677       /* Global Control Register */
12678       LINFLEX_GCR_32B_tag GCR;           /* offset: 0x008C size: 32 bit */
12679   
12680       /* UART Preset Time Out Register */
12681       LINFLEX_UARTPTO_32B_tag UARTPTO;   /* offset: 0x0090 size: 32 bit */
12682   
12683       /* UART Current Time Out Register */
12684       LINFLEX_UARTCTO_32B_tag UARTCTO;   /* offset: 0x0094 size: 32 bit */
12685   
12686       /* DMA TX Enable Register */
12687       LINFLEX_DMATXE_32B_tag DMATXE;     /* offset: 0x0098 size: 32 bit */
12688   
12689       /* DMA RX Enable Register */
12690       LINFLEX_DMARXE_32B_tag DMARXE;     /* offset: 0x009C size: 32 bit */
12691       int8_t LINFLEX_reserved_00A0[16224];
12692     } LINFLEX_tag;
12693   
12694   #define LINFLEX0                       (*(volatile LINFLEX_tag *) 0xFFE40000UL)
12695   #define LINFLEX1                       (*(volatile LINFLEX_tag *) 0xFFE44000UL)
12696   
12697     /****************************************************************/
12698     /*                                                              */
12699     /* Module: CRC  */
12700     /*                                                              */
12701     /****************************************************************/
12702   
12703     /* Register layout for all registers CFG ... */
12704     typedef union {                      /* CRC_CFG - CRC Configuration register */
12705       vuint32_t R;
12706       vuint8_t BYTE[4];                  /* individual bytes can be accessed */
12707       vuint16_t HALF[2];                 /* individual halfwords can be accessed */
12708       vuint32_t WORD;                    /* individual words can be accessed */
12709       struct {
12710        vuint32_t:
12711         28;
12712         vuint32_t POLYG:2;               /* Polynomal selection: 00- CRC-CCITT, 01- CRC-32, 10+11- CRC-8 */
12713         vuint32_t SWAP:1;                /* SWAP selection */
12714         vuint32_t INV:1;                 /* INV selection */
12715       } B;
12716     } CRC_CFG_32B_tag;
12717   
12718     /* Register layout for all registers INP ... */
12719     typedef union {                      /* CRC_INP - CRC Input register */
12720       vuint32_t R;
12721       vuint8_t BYTE[4];                  /* individual bytes can be accessed */
12722       vuint16_t HALF[2];                 /* individual halfwords can be accessed */
12723       vuint32_t WORD;                    /* individual words can be accessed */
12724     } CRC_INP_32B_tag;
12725   
12726     /* Register layout for all registers CSTAT ... */
12727     typedef union {                      /* CRC_STATUS - CRC Status register */
12728       vuint32_t R;
12729       vuint8_t BYTE[4];                  /* individual bytes can be accessed */
12730       vuint16_t HALF[2];                 /* individual halfwords can be accessed */
12731       vuint32_t WORD;                    /* individual words can be accessed */
12732     } CRC_CSTAT_32B_tag;
12733   
12734     /* Register layout for all registers OUTP ... */
12735     typedef union {                      /* CRC_STATUS - CRC OUTPUT register */
12736       vuint32_t R;
12737       vuint8_t BYTE[4];                  /* individual bytes can be accessed */
12738       vuint16_t HALF[2];                 /* individual halfwords can be accessed */
12739       vuint32_t WORD;                    /* individual words can be accessed */
12740     } CRC_OUTP_32B_tag;
12741   
12742     typedef struct CRC_CNTX_struct_tag {
12743       /* CRC_CFG - CRC Configuration register */
12744       CRC_CFG_32B_tag CFG;               /* relative offset: 0x0000 */
12745   
12746       /* CRC_INP - CRC Input register */
12747       CRC_INP_32B_tag INP;               /* relative offset: 0x0004 */
12748   
12749       /* CRC_STATUS - CRC Status register */
12750       CRC_CSTAT_32B_tag CSTAT;           /* relative offset: 0x0008 */
12751   
12752       /* CRC_STATUS - CRC OUTPUT register */
12753       CRC_OUTP_32B_tag OUTP;             /* relative offset: 0x000C */
12754     } CRC_CNTX_tag;
12755   
12756     typedef struct CRC_struct_tag {
12757       union {
12758         /*  Register set CNTX */
12759         CRC_CNTX_tag CNTX[3];            /* offset: 0x0000  (0x0010 x 3) */
12760         struct {
12761           /* CRC_CFG - CRC Configuration register */
12762           CRC_CFG_32B_tag CFG0;          /* offset: 0x0000 size: 32 bit */
12763   
12764           /* CRC_INP - CRC Input register */
12765           CRC_INP_32B_tag INP0;          /* offset: 0x0004 size: 32 bit */
12766   
12767           /* CRC_STATUS - CRC Status register */
12768           CRC_CSTAT_32B_tag CSTAT0;      /* offset: 0x0008 size: 32 bit */
12769   
12770           /* CRC_STATUS - CRC OUTPUT register */
12771           CRC_OUTP_32B_tag OUTP0;        /* offset: 0x000C size: 32 bit */
12772   
12773           /* CRC_CFG - CRC Configuration register */
12774           CRC_CFG_32B_tag CFG1;          /* offset: 0x0010 size: 32 bit */
12775   
12776           /* CRC_INP - CRC Input register */
12777           CRC_INP_32B_tag INP1;          /* offset: 0x0014 size: 32 bit */
12778   
12779           /* CRC_STATUS - CRC Status register */
12780           CRC_CSTAT_32B_tag CSTAT1;      /* offset: 0x0018 size: 32 bit */
12781   
12782           /* CRC_STATUS - CRC OUTPUT register */
12783           CRC_OUTP_32B_tag OUTP1;        /* offset: 0x001C size: 32 bit */
12784   
12785           /* CRC_CFG - CRC Configuration register */
12786           CRC_CFG_32B_tag CFG2;          /* offset: 0x0020 size: 32 bit */
12787   
12788           /* CRC_INP - CRC Input register */
12789           CRC_INP_32B_tag INP2;          /* offset: 0x0024 size: 32 bit */
12790   
12791           /* CRC_STATUS - CRC Status register */
12792           CRC_CSTAT_32B_tag CSTAT2;      /* offset: 0x0028 size: 32 bit */
12793   
12794           /* CRC_STATUS - CRC OUTPUT register */
12795           CRC_OUTP_32B_tag OUTP2;        /* offset: 0x002C size: 32 bit */
12796         };
12797       };
12798   
12799       int8_t CRC_reserved_0030[16336];
12800     } CRC_tag;
12801   
12802   #define CRC                            (*(volatile CRC_tag *) 0xFFE68000UL)
12803   
12804     /****************************************************************/
12805     /*                                                              */
12806     /* Module: FCCU  */
12807     /*                                                              */
12808     /****************************************************************/
12809     typedef union {                      /* FCCU Control Register */
12810       vuint32_t R;
12811       struct {
12812        vuint32_t:
12813         23;
12814         vuint32_t NVML:1;                /* NVM configuration loaded */
12815         vuint32_t OPS:2;                 /* Operation status */
12816        vuint32_t:
12817         1;
12818         vuint32_t OPR:5;                 /* Operation run */
12819       } B;
12820     } FCCU_CTRL_32B_tag;
12821   
12822     typedef union {                      /* FCCU CTRL Key Register */
12823       vuint32_t R;
12824     } FCCU_CTRLK_32B_tag;
12825   
12826     typedef union {                      /* FCCU Configuration Register */
12827       vuint32_t R;
12828       struct {
12829        vuint32_t:
12830         10;
12831         vuint32_t RCCE1:1;               /* RCC1 enable */
12832         vuint32_t RCCE0:1;               /* RCC0 enable */
12833         vuint32_t SMRT:4;                /* Safe Mode Request Timer */
12834        vuint32_t:
12835         4;
12836         vuint32_t CM:1;                  /* Config mode */
12837         vuint32_t SM:1;                  /* Switching mode */
12838         vuint32_t PS:1;                  /* Polarity Selection */
12839         vuint32_t FOM:3;                 /* Fault Output Mode Selection */
12840         vuint32_t FOP:6;                 /* Fault Output Prescaler */
12841       } B;
12842     } FCCU_CFG_32B_tag;
12843   
12844     typedef union {                      /* FCCU CF Configuration Register 0 */
12845       vuint32_t R;
12846       struct {
12847         vuint32_t CFC31:1;               /* CF 31 configuration */
12848         vuint32_t CFC30:1;               /* CF 30 configuration */
12849         vuint32_t CFC29:1;               /* CF 29 configuration */
12850         vuint32_t CFC28:1;               /* CF 28 configuration */
12851         vuint32_t CFC27:1;               /* CF 27 configuration */
12852         vuint32_t CFC26:1;               /* CF 26 configuration */
12853         vuint32_t CFC25:1;               /* CF 25 configuration */
12854         vuint32_t CFC24:1;               /* CF 24 configuration */
12855         vuint32_t CFC23:1;               /* CF 23 configuration */
12856         vuint32_t CFC22:1;               /* CF 22 configuration */
12857         vuint32_t CFC21:1;               /* CF 21 configuration */
12858         vuint32_t CFC20:1;               /* CF 20 configuration */
12859         vuint32_t CFC19:1;               /* CF 19 configuration */
12860         vuint32_t CFC18:1;               /* CF 18 configuration */
12861         vuint32_t CFC17:1;               /* CF 17 configuration */
12862         vuint32_t CFC16:1;               /* CF 16 configuration */
12863         vuint32_t CFC15:1;               /* CF 15 configuration */
12864         vuint32_t CFC14:1;               /* CF 14 configuration */
12865         vuint32_t CFC13:1;               /* CF 13 configuration */
12866         vuint32_t CFC12:1;               /* CF 12 configuration */
12867         vuint32_t CFC11:1;               /* CF 11 configuration */
12868         vuint32_t CFC10:1;               /* CF 10 configuration */
12869         vuint32_t CFC9:1;                /* CF 9 configuration */
12870         vuint32_t CFC8:1;                /* CF 8 configuration */
12871         vuint32_t CFC7:1;                /* CF 7 configuration */
12872         vuint32_t CFC6:1;                /* CF 6 configuration */
12873         vuint32_t CFC5:1;                /* CF 5 configuration */
12874         vuint32_t CFC4:1;                /* CF 4 configuration */
12875         vuint32_t CFC3:1;                /* CF 3 configuration */
12876         vuint32_t CFC2:1;                /* CF 2 configuration */
12877         vuint32_t CFC1:1;                /* CF 1 configuration */
12878         vuint32_t CFC0:1;                /* CF 0 configuration */
12879       } B;
12880     } FCCU_CF_CFG0_32B_tag;
12881   
12882     typedef union {                      /* FCCU CF Configuration Register 1 */
12883       vuint32_t R;
12884       struct {
12885         vuint32_t CFC63:1;               /* CF 63 configuration */
12886         vuint32_t CFC62:1;               /* CF 62 configuration */
12887         vuint32_t CFC61:1;               /* CF 61 configuration */
12888         vuint32_t CFC60:1;               /* CF 60 configuration */
12889         vuint32_t CFC59:1;               /* CF 59 configuration */
12890         vuint32_t CFC58:1;               /* CF 58 configuration */
12891         vuint32_t CFC57:1;               /* CF 57 configuration */
12892         vuint32_t CFC56:1;               /* CF 56 configuration */
12893         vuint32_t CFC55:1;               /* CF 55 configuration */
12894         vuint32_t CFC54:1;               /* CF 54 configuration */
12895         vuint32_t CFC53:1;               /* CF 53 configuration */
12896         vuint32_t CFC52:1;               /* CF 52 configuration */
12897         vuint32_t CFC51:1;               /* CF 51 configuration */
12898         vuint32_t CFC50:1;               /* CF 50 configuration */
12899         vuint32_t CFC49:1;               /* CF 49 configuration */
12900         vuint32_t CFC48:1;               /* CF 48 configuration */
12901         vuint32_t CFC47:1;               /* CF 47 configuration */
12902         vuint32_t CFC46:1;               /* CF 46 configuration */
12903         vuint32_t CFC45:1;               /* CF 45 configuration */
12904         vuint32_t CFC44:1;               /* CF 44 configuration */
12905         vuint32_t CFC43:1;               /* CF 43 configuration */
12906         vuint32_t CFC42:1;               /* CF 42 configuration */
12907         vuint32_t CFC41:1;               /* CF 41 configuration */
12908         vuint32_t CFC40:1;               /* CF 40 configuration */
12909         vuint32_t CFC39:1;               /* CF 39 configuration */
12910         vuint32_t CFC38:1;               /* CF 38 configuration */
12911         vuint32_t CFC37:1;               /* CF 37 configuration */
12912         vuint32_t CFC36:1;               /* CF 36 configuration */
12913         vuint32_t CFC35:1;               /* CF 35 configuration */
12914         vuint32_t CFC34:1;               /* CF 34 configuration */
12915         vuint32_t CFC33:1;               /* CF 33 configuration */
12916         vuint32_t CFC32:1;               /* CF 32 configuration */
12917       } B;
12918     } FCCU_CF_CFG1_32B_tag;
12919   
12920     typedef union {                      /* FCCU CF Configuration Register 2 */
12921       vuint32_t R;
12922       struct {
12923         vuint32_t CFC95:1;               /* CF 95 configuration */
12924         vuint32_t CFC94:1;               /* CF 94 configuration */
12925         vuint32_t CFC93:1;               /* CF 93 configuration */
12926         vuint32_t CFC92:1;               /* CF 92 configuration */
12927         vuint32_t CFC91:1;               /* CF 91 configuration */
12928         vuint32_t CFC90:1;               /* CF 90 configuration */
12929         vuint32_t CFC89:1;               /* CF 89 configuration */
12930         vuint32_t CFC88:1;               /* CF 88 configuration */
12931         vuint32_t CFC87:1;               /* CF 87 configuration */
12932         vuint32_t CFC86:1;               /* CF 86 configuration */
12933         vuint32_t CFC85:1;               /* CF 85 configuration */
12934         vuint32_t CFC84:1;               /* CF 84 configuration */
12935         vuint32_t CFC83:1;               /* CF 83 configuration */
12936         vuint32_t CFC82:1;               /* CF 82 configuration */
12937         vuint32_t CFC81:1;               /* CF 81 configuration */
12938         vuint32_t CFC80:1;               /* CF 80 configuration */
12939         vuint32_t CFC79:1;               /* CF 79 configuration */
12940         vuint32_t CFC78:1;               /* CF 78 configuration */
12941         vuint32_t CFC77:1;               /* CF 77 configuration */
12942         vuint32_t CFC76:1;               /* CF 76 configuration */
12943         vuint32_t CFC75:1;               /* CF 75 configuration */
12944         vuint32_t CFC74:1;               /* CF 74 configuration */
12945         vuint32_t CFC73:1;               /* CF 73 configuration */
12946         vuint32_t CFC72:1;               /* CF 72 configuration */
12947         vuint32_t CFC71:1;               /* CF 71 configuration */
12948         vuint32_t CFC70:1;               /* CF 70 configuration */
12949         vuint32_t CFC69:1;               /* CF 69 configuration */
12950         vuint32_t CFC68:1;               /* CF 68 configuration */
12951         vuint32_t CFC67:1;               /* CF 67 configuration */
12952         vuint32_t CFC66:1;               /* CF 66 configuration */
12953         vuint32_t CFC65:1;               /* CF 65 configuration */
12954         vuint32_t CFC64:1;               /* CF 64 configuration */
12955       } B;
12956     } FCCU_CF_CFG2_32B_tag;
12957   
12958     typedef union {                      /* FCCU CF Configuration Register 3 */
12959       vuint32_t R;
12960       struct {
12961         vuint32_t CFC127:1;              /* CF 127 configuration */
12962         vuint32_t CFC126:1;              /* CF 126 configuration */
12963         vuint32_t CFC125:1;              /* CF 125 configuration */
12964         vuint32_t CFC124:1;              /* CF 124 configuration */
12965         vuint32_t CFC123:1;              /* CF 123 configuration */
12966         vuint32_t CFC122:1;              /* CF 122 configuration */
12967         vuint32_t CFC121:1;              /* CF 121 configuration */
12968         vuint32_t CFC120:1;              /* CF 120 configuration */
12969         vuint32_t CFC119:1;              /* CF 119 configuration */
12970         vuint32_t CFC118:1;              /* CF 118 configuration */
12971         vuint32_t CFC117:1;              /* CF 117 configuration */
12972         vuint32_t CFC116:1;              /* CF 116 configuration */
12973         vuint32_t CFC115:1;              /* CF 115 configuration */
12974         vuint32_t CFC114:1;              /* CF 114 configuration */
12975         vuint32_t CFC113:1;              /* CF 113 configuration */
12976         vuint32_t CFC112:1;              /* CF 112 configuration */
12977         vuint32_t CFC111:1;              /* CF 111 configuration */
12978         vuint32_t CFC110:1;              /* CF 110 configuration */
12979         vuint32_t CFC109:1;              /* CF 109 configuration */
12980         vuint32_t CFC108:1;              /* CF 108 configuration */
12981         vuint32_t CFC107:1;              /* CF 107 configuration */
12982         vuint32_t CFC106:1;              /* CF 106 configuration */
12983         vuint32_t CFC105:1;              /* CF 105 configuration */
12984         vuint32_t CFC104:1;              /* CF 104 configuration */
12985         vuint32_t CFC103:1;              /* CF 103 configuration */
12986         vuint32_t CFC102:1;              /* CF 102 configuration */
12987         vuint32_t CFC101:1;              /* CF 101 configuration */
12988         vuint32_t CFC100:1;              /* CF 100 configuration */
12989         vuint32_t CFC99:1;               /* CF 99 configuration */
12990         vuint32_t CFC98:1;               /* CF 98 configuration */
12991         vuint32_t CFC97:1;               /* CF 97 configuration */
12992         vuint32_t CFC96:1;               /* CF 96 configuration */
12993       } B;
12994     } FCCU_CF_CFG3_32B_tag;
12995   
12996     typedef union {                      /* FCCU NCF Configuration Register 0 */
12997       vuint32_t R;
12998       struct {
12999         vuint32_t NCFC31:1;              /* NCF 31 configuration */
13000         vuint32_t NCFC30:1;              /* NCF 30 configuration */
13001         vuint32_t NCFC29:1;              /* NCF 29 configuration */
13002         vuint32_t NCFC28:1;              /* NCF 28 configuration */
13003         vuint32_t NCFC27:1;              /* NCF 27 configuration */
13004         vuint32_t NCFC26:1;              /* NCF 26 configuration */
13005         vuint32_t NCFC25:1;              /* NCF 25 configuration */
13006         vuint32_t NCFC24:1;              /* NCF 24 configuration */
13007         vuint32_t NCFC23:1;              /* NCF 23 configuration */
13008         vuint32_t NCFC22:1;              /* NCF 22 configuration */
13009         vuint32_t NCFC21:1;              /* NCF 21 configuration */
13010         vuint32_t NCFC20:1;              /* NCF 20 configuration */
13011         vuint32_t NCFC19:1;              /* NCF 19 configuration */
13012         vuint32_t NCFC18:1;              /* NCF 18 configuration */
13013         vuint32_t NCFC17:1;              /* NCF 17 configuration */
13014         vuint32_t NCFC16:1;              /* NCF 16 configuration */
13015         vuint32_t NCFC15:1;              /* NCF 15 configuration */
13016         vuint32_t NCFC14:1;              /* NCF 14 configuration */
13017         vuint32_t NCFC13:1;              /* NCF 13 configuration */
13018         vuint32_t NCFC12:1;              /* NCF 12 configuration */
13019         vuint32_t NCFC11:1;              /* NCF 11 configuration */
13020         vuint32_t NCFC10:1;              /* NCF 10 configuration */
13021         vuint32_t NCFC9:1;               /* NCF 9 configuration */
13022         vuint32_t NCFC8:1;               /* NCF 8 configuration */
13023         vuint32_t NCFC7:1;               /* NCF 7 configuration */
13024         vuint32_t NCFC6:1;               /* NCF 6 configuration */
13025         vuint32_t NCFC5:1;               /* NCF 5 configuration */
13026         vuint32_t NCFC4:1;               /* NCF 4 configuration */
13027         vuint32_t NCFC3:1;               /* NCF 3 configuration */
13028         vuint32_t NCFC2:1;               /* NCF 2 configuration */
13029         vuint32_t NCFC1:1;               /* NCF 1 configuration */
13030         vuint32_t NCFC0:1;               /* NCF 0 configuration */
13031       } B;
13032     } FCCU_NCF_CFG0_32B_tag;
13033   
13034     typedef union {                      /* FCCU NCF Configuration Register 1 */
13035       vuint32_t R;
13036       struct {
13037         vuint32_t NCFC63:1;              /* NCF 63 configuration */
13038         vuint32_t NCFC62:1;              /* NCF 62 configuration */
13039         vuint32_t NCFC61:1;              /* NCF 61 configuration */
13040         vuint32_t NCFC60:1;              /* NCF 60 configuration */
13041         vuint32_t NCFC59:1;              /* NCF 59 configuration */
13042         vuint32_t NCFC58:1;              /* NCF 58 configuration */
13043         vuint32_t NCFC57:1;              /* NCF 57 configuration */
13044         vuint32_t NCFC56:1;              /* NCF 56 configuration */
13045         vuint32_t NCFC55:1;              /* NCF 55 configuration */
13046         vuint32_t NCFC54:1;              /* NCF 54 configuration */
13047         vuint32_t NCFC53:1;              /* NCF 53 configuration */
13048         vuint32_t NCFC52:1;              /* NCF 52 configuration */
13049         vuint32_t NCFC51:1;              /* NCF 51 configuration */
13050         vuint32_t NCFC50:1;              /* NCF 50 configuration */
13051         vuint32_t NCFC49:1;              /* NCF 49 configuration */
13052         vuint32_t NCFC48:1;              /* NCF 48 configuration */
13053         vuint32_t NCFC47:1;              /* NCF 47 configuration */
13054         vuint32_t NCFC46:1;              /* NCF 46 configuration */
13055         vuint32_t NCFC45:1;              /* NCF 45 configuration */
13056         vuint32_t NCFC44:1;              /* NCF 44 configuration */
13057         vuint32_t NCFC43:1;              /* NCF 43 configuration */
13058         vuint32_t NCFC42:1;              /* NCF 42 configuration */
13059         vuint32_t NCFC41:1;              /* NCF 41 configuration */
13060         vuint32_t NCFC40:1;              /* NCF 40 configuration */
13061         vuint32_t NCFC39:1;              /* NCF 39 configuration */
13062         vuint32_t NCFC38:1;              /* NCF 38 configuration */
13063         vuint32_t NCFC37:1;              /* NCF 37 configuration */
13064         vuint32_t NCFC36:1;              /* NCF 36 configuration */
13065         vuint32_t NCFC35:1;              /* NCF 35 configuration */
13066         vuint32_t NCFC34:1;              /* NCF 34 configuration */
13067         vuint32_t NCFC33:1;              /* NCF 33 configuration */
13068         vuint32_t NCFC32:1;              /* NCF 32 configuration */
13069       } B;
13070     } FCCU_NCF_CFG1_32B_tag;
13071   
13072     typedef union {                      /* FCCU NCF Configuration Register 2 */
13073       vuint32_t R;
13074       struct {
13075         vuint32_t NCFC95:1;              /* NCF 95 configuration */
13076         vuint32_t NCFC94:1;              /* NCF 94 configuration */
13077         vuint32_t NCFC93:1;              /* NCF 93 configuration */
13078         vuint32_t NCFC92:1;              /* NCF 92 configuration */
13079         vuint32_t NCFC91:1;              /* NCF 91 configuration */
13080         vuint32_t NCFC90:1;              /* NCF 90 configuration */
13081         vuint32_t NCFC89:1;              /* NCF 89 configuration */
13082         vuint32_t NCFC88:1;              /* NCF 88 configuration */
13083         vuint32_t NCFC87:1;              /* NCF 87 configuration */
13084         vuint32_t NCFC86:1;              /* NCF 86 configuration */
13085         vuint32_t NCFC85:1;              /* NCF 85 configuration */
13086         vuint32_t NCFC84:1;              /* NCF 84 configuration */
13087         vuint32_t NCFC83:1;              /* NCF 83 configuration */
13088         vuint32_t NCFC82:1;              /* NCF 82 configuration */
13089         vuint32_t NCFC81:1;              /* NCF 81 configuration */
13090         vuint32_t NCFC80:1;              /* NCF 80 configuration */
13091         vuint32_t NCFC79:1;              /* NCF 79 configuration */
13092         vuint32_t NCFC78:1;              /* NCF 78 configuration */
13093         vuint32_t NCFC77:1;              /* NCF 77 configuration */
13094         vuint32_t NCFC76:1;              /* NCF 76 configuration */
13095         vuint32_t NCFC75:1;              /* NCF 75 configuration */
13096         vuint32_t NCFC74:1;              /* NCF 74 configuration */
13097         vuint32_t NCFC73:1;              /* NCF 73 configuration */
13098         vuint32_t NCFC72:1;              /* NCF 72 configuration */
13099         vuint32_t NCFC71:1;              /* NCF 71 configuration */
13100         vuint32_t NCFC70:1;              /* NCF 70 configuration */
13101         vuint32_t NCFC69:1;              /* NCF 69 configuration */
13102         vuint32_t NCFC68:1;              /* NCF 68 configuration */
13103         vuint32_t NCFC67:1;              /* NCF 67 configuration */
13104         vuint32_t NCFC66:1;              /* NCF 66 configuration */
13105         vuint32_t NCFC65:1;              /* NCF 65 configuration */
13106         vuint32_t NCFC64:1;              /* NCF 64 configuration */
13107       } B;
13108     } FCCU_NCF_CFG2_32B_tag;
13109   
13110     typedef union {                      /* FCCU NCF Configuration Register 3 */
13111       vuint32_t R;
13112       struct {
13113         vuint32_t NCFC127:1;             /* NCF 127 configuration */
13114         vuint32_t NCFC126:1;             /* NCF 126 configuration */
13115         vuint32_t NCFC125:1;             /* NCF 125 configuration */
13116         vuint32_t NCFC124:1;             /* NCF 124 configuration */
13117         vuint32_t NCFC123:1;             /* NCF 123 configuration */
13118         vuint32_t NCFC122:1;             /* NCF 122 configuration */
13119         vuint32_t NCFC121:1;             /* NCF 121 configuration */
13120         vuint32_t NCFC120:1;             /* NCF 120 configuration */
13121         vuint32_t NCFC119:1;             /* NCF 119 configuration */
13122         vuint32_t NCFC118:1;             /* NCF 118 configuration */
13123         vuint32_t NCFC117:1;             /* NCF 117 configuration */
13124         vuint32_t NCFC116:1;             /* NCF 116 configuration */
13125         vuint32_t NCFC115:1;             /* NCF 115 configuration */
13126         vuint32_t NCFC114:1;             /* NCF 114 configuration */
13127         vuint32_t NCFC113:1;             /* NCF 113 configuration */
13128         vuint32_t NCFC112:1;             /* NCF 112 configuration */
13129         vuint32_t NCFC111:1;             /* NCF 111 configuration */
13130         vuint32_t NCFC110:1;             /* NCF 110 configuration */
13131         vuint32_t NCFC109:1;             /* NCF 109 configuration */
13132         vuint32_t NCFC108:1;             /* NCF 108 configuration */
13133         vuint32_t NCFC107:1;             /* NCF 107 configuration */
13134         vuint32_t NCFC106:1;             /* NCF 106 configuration */
13135         vuint32_t NCFC105:1;             /* NCF 105 configuration */
13136         vuint32_t NCFC104:1;             /* NCF 104 configuration */
13137         vuint32_t NCFC103:1;             /* NCF 103 configuration */
13138         vuint32_t NCFC102:1;             /* NCF 102 configuration */
13139         vuint32_t NCFC101:1;             /* NCF 101 configuration */
13140         vuint32_t NCFC100:1;             /* NCF 100 configuration */
13141         vuint32_t NCFC99:1;              /* NCF 99 configuration */
13142         vuint32_t NCFC98:1;              /* NCF 98 configuration */
13143         vuint32_t NCFC97:1;              /* NCF 97 configuration */
13144         vuint32_t NCFC96:1;              /* NCF 96 configuration */
13145       } B;
13146     } FCCU_NCF_CFG3_32B_tag;
13147   
13148     typedef union {                      /* FCCU CFS Configuration Register 0 */
13149       vuint32_t R;
13150       struct {
13151         vuint32_t CFSC15:2;              /* CF 15 state configuration */
13152         vuint32_t CFSC14:2;              /* CF 14 state configuration */
13153         vuint32_t CFSC13:2;              /* CF 13 state configuration */
13154         vuint32_t CFSC12:2;              /* CF 12 state configuration */
13155         vuint32_t CFSC11:2;              /* CF 11 state configuration */
13156         vuint32_t CFSC10:2;              /* CF 10 state configuration */
13157         vuint32_t CFSC9:2;               /* CF 9 state configuration */
13158         vuint32_t CFSC8:2;               /* CF 8 state configuration */
13159         vuint32_t CFSC7:2;               /* CF 7 state configuration */
13160         vuint32_t CFSC6:2;               /* CF 6 state configuration */
13161         vuint32_t CFSC5:2;               /* CF 5 state configuration */
13162         vuint32_t CFSC4:2;               /* CF 4 state configuration */
13163         vuint32_t CFSC3:2;               /* CF 3 state configuration */
13164         vuint32_t CFSC2:2;               /* CF 2 state configuration */
13165         vuint32_t CFSC1:2;               /* CF 1 state configuration */
13166         vuint32_t CFSC0:2;               /* CF 0 state configuration */
13167       } B;
13168     } FCCU_CFS_CFG0_32B_tag;
13169   
13170     typedef union {                      /* FCCU CFS Configuration Register 1 */
13171       vuint32_t R;
13172       struct {
13173         vuint32_t CFSC31:2;              /* CF 31 state configuration */
13174         vuint32_t CFSC30:2;              /* CF 30 state configuration */
13175         vuint32_t CFSC29:2;              /* CF 29 state configuration */
13176         vuint32_t CFSC28:2;              /* CF 28 state configuration */
13177         vuint32_t CFSC27:2;              /* CF 27 state configuration */
13178         vuint32_t CFSC26:2;              /* CF 26 state configuration */
13179         vuint32_t CFSC25:2;              /* CF 25 state configuration */
13180         vuint32_t CFSC24:2;              /* CF 24 state configuration */
13181         vuint32_t CFSC23:2;              /* CF 23 state configuration */
13182         vuint32_t CFSC22:2;              /* CF 22 state configuration */
13183         vuint32_t CFSC21:2;              /* CF 21 state configuration */
13184         vuint32_t CFSC20:2;              /* CF 20 state configuration */
13185         vuint32_t CFSC19:2;              /* CF 19 state configuration */
13186         vuint32_t CFSC18:2;              /* CF 18 state configuration */
13187         vuint32_t CFSC17:2;              /* CF 17 state configuration */
13188         vuint32_t CFSC16:2;              /* CF 16 state configuration */
13189       } B;
13190     } FCCU_CFS_CFG1_32B_tag;
13191   
13192     typedef union {                      /* FCCU CFS Configuration Register 2 */
13193       vuint32_t R;
13194       struct {
13195         vuint32_t CFSC47:2;              /* CF 47 state configuration */
13196         vuint32_t CFSC46:2;              /* CF 46 state configuration */
13197         vuint32_t CFSC45:2;              /* CF 45 state configuration */
13198         vuint32_t CFSC44:2;              /* CF 44 state configuration */
13199         vuint32_t CFSC43:2;              /* CF 43 state configuration */
13200         vuint32_t CFSC42:2;              /* CF 42 state configuration */
13201         vuint32_t CFSC41:2;              /* CF 41 state configuration */
13202         vuint32_t CFSC40:2;              /* CF 40 state configuration */
13203         vuint32_t CFSC39:2;              /* CF 39 state configuration */
13204         vuint32_t CFSC38:2;              /* CF 38 state configuration */
13205         vuint32_t CFSC37:2;              /* CF 37 state configuration */
13206         vuint32_t CFSC36:2;              /* CF 36 state configuration */
13207         vuint32_t CFSC35:2;              /* CF 35 state configuration */
13208         vuint32_t CFSC34:2;              /* CF 34 state configuration */
13209         vuint32_t CFSC33:2;              /* CF 33 state configuration */
13210         vuint32_t CFSC32:2;              /* CF 32 state configuration */
13211       } B;
13212     } FCCU_CFS_CFG2_32B_tag;
13213   
13214     typedef union {                      /* FCCU CFS Configuration Register 3 */
13215       vuint32_t R;
13216       struct {
13217         vuint32_t CFSC63:2;              /* CF 63 state configuration */
13218         vuint32_t CFSC62:2;              /* CF 62 state configuration */
13219         vuint32_t CFSC61:2;              /* CF 61 state configuration */
13220         vuint32_t CFSC60:2;              /* CF 60 state configuration */
13221         vuint32_t CFSC59:2;              /* CF 59 state configuration */
13222         vuint32_t CFSC58:2;              /* CF 58 state configuration */
13223         vuint32_t CFSC57:2;              /* CF 57 state configuration */
13224         vuint32_t CFSC56:2;              /* CF 56 state configuration */
13225         vuint32_t CFSC55:2;              /* CF 55 state configuration */
13226         vuint32_t CFSC54:2;              /* CF 54 state configuration */
13227         vuint32_t CFSC53:2;              /* CF 53 state configuration */
13228         vuint32_t CFSC52:2;              /* CF 52 state configuration */
13229         vuint32_t CFSC51:2;              /* CF 51 state configuration */
13230         vuint32_t CFSC50:2;              /* CF 50 state configuration */
13231         vuint32_t CFSC49:2;              /* CF 49 state configuration */
13232         vuint32_t CFSC48:2;              /* CF 48 state configuration */
13233       } B;
13234     } FCCU_CFS_CFG3_32B_tag;
13235   
13236     typedef union {                      /* FCCU CFS Configuration Register 4 */
13237       vuint32_t R;
13238       struct {
13239         vuint32_t CFSC79:2;              /* CF 79 state configuration */
13240         vuint32_t CFSC78:2;              /* CF 78 state configuration */
13241         vuint32_t CFSC77:2;              /* CF 77 state configuration */
13242         vuint32_t CFSC76:2;              /* CF 76 state configuration */
13243         vuint32_t CFSC75:2;              /* CF 75 state configuration */
13244         vuint32_t CFSC74:2;              /* CF 74 state configuration */
13245         vuint32_t CFSC73:2;              /* CF 73 state configuration */
13246         vuint32_t CFSC72:2;              /* CF 72 state configuration */
13247         vuint32_t CFSC71:2;              /* CF 71 state configuration */
13248         vuint32_t CFSC70:2;              /* CF 70 state configuration */
13249         vuint32_t CFSC69:2;              /* CF 69 state configuration */
13250         vuint32_t CFSC68:2;              /* CF 68 state configuration */
13251         vuint32_t CFSC67:2;              /* CF 67 state configuration */
13252         vuint32_t CFSC66:2;              /* CF 66 state configuration */
13253         vuint32_t CFSC65:2;              /* CF 65 state configuration */
13254         vuint32_t CFSC64:2;              /* CF 64 state configuration */
13255       } B;
13256     } FCCU_CFS_CFG4_32B_tag;
13257   
13258     typedef union {                      /* FCCU CFS Configuration Register 5 */
13259       vuint32_t R;
13260       struct {
13261         vuint32_t CFSC95:2;              /* CF 95 state configuration */
13262         vuint32_t CFSC94:2;              /* CF 94 state configuration */
13263         vuint32_t CFSC93:2;              /* CF 93 state configuration */
13264         vuint32_t CFSC92:2;              /* CF 92 state configuration */
13265         vuint32_t CFSC91:2;              /* CF 91 state configuration */
13266         vuint32_t CFSC90:2;              /* CF 90 state configuration */
13267         vuint32_t CFSC89:2;              /* CF 89 state configuration */
13268         vuint32_t CFSC88:2;              /* CF 88 state configuration */
13269         vuint32_t CFSC87:2;              /* CF 87 state configuration */
13270         vuint32_t CFSC86:2;              /* CF 86 state configuration */
13271         vuint32_t CFSC85:2;              /* CF 85 state configuration */
13272         vuint32_t CFSC84:2;              /* CF 84 state configuration */
13273         vuint32_t CFSC83:2;              /* CF 83 state configuration */
13274         vuint32_t CFSC82:2;              /* CF 82 state configuration */
13275         vuint32_t CFSC81:2;              /* CF 81 state configuration */
13276         vuint32_t CFSC80:2;              /* CF 80 state configuration */
13277       } B;
13278     } FCCU_CFS_CFG5_32B_tag;
13279   
13280     typedef union {                      /* FCCU CFS Configuration Register 6 */
13281       vuint32_t R;
13282       struct {
13283         vuint32_t CFSC111:2;             /* CF 111 state configuration */
13284         vuint32_t CFSC110:2;             /* CF 110 state configuration */
13285         vuint32_t CFSC109:2;             /* CF 109 state configuration */
13286         vuint32_t CFSC108:2;             /* CF 108 state configuration */
13287         vuint32_t CFSC107:2;             /* CF 107 state configuration */
13288         vuint32_t CFSC106:2;             /* CF 106 state configuration */
13289         vuint32_t CFSC105:2;             /* CF 105 state configuration */
13290         vuint32_t CFSC104:2;             /* CF 104 state configuration */
13291         vuint32_t CFSC103:2;             /* CF 103 state configuration */
13292         vuint32_t CFSC102:2;             /* CF 102 state configuration */
13293         vuint32_t CFSC101:2;             /* CF 101 state configuration */
13294         vuint32_t CFSC100:2;             /* CF 100 state configuration */
13295         vuint32_t CFSC99:2;              /* CF 99 state configuration */
13296         vuint32_t CFSC98:2;              /* CF 98 state configuration */
13297         vuint32_t CFSC97:2;              /* CF 97 state configuration */
13298         vuint32_t CFSC96:2;              /* CF 96 state configuration */
13299       } B;
13300     } FCCU_CFS_CFG6_32B_tag;
13301   
13302     typedef union {                      /* FCCU CFS Configuration Register 7 */
13303       vuint32_t R;
13304       struct {
13305         vuint32_t CFSC127:2;             /* CF 127 state configuration */
13306         vuint32_t CFSC126:2;             /* CF 126 state configuration */
13307         vuint32_t CFSC125:2;             /* CF 125 state configuration */
13308         vuint32_t CFSC124:2;             /* CF 124 state configuration */
13309         vuint32_t CFSC123:2;             /* CF 123 state configuration */
13310         vuint32_t CFSC122:2;             /* CF 122 state configuration */
13311         vuint32_t CFSC121:2;             /* CF 121 state configuration */
13312         vuint32_t CFSC120:2;             /* CF 120 state configuration */
13313         vuint32_t CFSC119:2;             /* CF 119 state configuration */
13314         vuint32_t CFSC118:2;             /* CF 118 state configuration */
13315         vuint32_t CFSC117:2;             /* CF 117 state configuration */
13316         vuint32_t CFSC116:2;             /* CF 116 state configuration */
13317         vuint32_t CFSC115:2;             /* CF 115 state configuration */
13318         vuint32_t CFSC114:2;             /* CF 114 state configuration */
13319         vuint32_t CFSC113:2;             /* CF 113 state configuration */
13320         vuint32_t CFSC112:2;             /* CF 112 state configuration */
13321       } B;
13322     } FCCU_CFS_CFG7_32B_tag;
13323   
13324     typedef union {                      /* FCCU NCFS Configuration Register 0 */
13325       vuint32_t R;
13326       struct {
13327         vuint32_t NCFSC15:2;             /* NCF 15 state configuration */
13328         vuint32_t NCFSC14:2;             /* NCF 14 state configuration */
13329         vuint32_t NCFSC13:2;             /* NCF 13 state configuration */
13330         vuint32_t NCFSC12:2;             /* NCF 12 state configuration */
13331         vuint32_t NCFSC11:2;             /* NCF 11 state configuration */
13332         vuint32_t NCFSC10:2;             /* NCF 10 state configuration */
13333         vuint32_t NCFSC9:2;              /* NCF 9 state configuration */
13334         vuint32_t NCFSC8:2;              /* NCF 8 state configuration */
13335         vuint32_t NCFSC7:2;              /* NCF 7 state configuration */
13336         vuint32_t NCFSC6:2;              /* NCF 6 state configuration */
13337         vuint32_t NCFSC5:2;              /* NCF 5 state configuration */
13338         vuint32_t NCFSC4:2;              /* NCF 4 state configuration */
13339         vuint32_t NCFSC3:2;              /* NCF 3 state configuration */
13340         vuint32_t NCFSC2:2;              /* NCF 2 state configuration */
13341         vuint32_t NCFSC1:2;              /* NCF 1 state configuration */
13342         vuint32_t NCFSC0:2;              /* NCF 0 state configuration */
13343       } B;
13344     } FCCU_NCFS_CFG0_32B_tag;
13345   
13346     typedef union {                      /* FCCU NCFS Configuration Register 1 */
13347       vuint32_t R;
13348       struct {
13349         vuint32_t NCFSC31:2;             /* NCF 31 state configuration */
13350         vuint32_t NCFSC30:2;             /* NCF 30 state configuration */
13351         vuint32_t NCFSC29:2;             /* NCF 29 state configuration */
13352         vuint32_t NCFSC28:2;             /* NCF 28 state configuration */
13353         vuint32_t NCFSC27:2;             /* NCF 27 state configuration */
13354         vuint32_t NCFSC26:2;             /* NCF 26 state configuration */
13355         vuint32_t NCFSC25:2;             /* NCF 25 state configuration */
13356         vuint32_t NCFSC24:2;             /* NCF 24 state configuration */
13357         vuint32_t NCFSC23:2;             /* NCF 23 state configuration */
13358         vuint32_t NCFSC22:2;             /* NCF 22 state configuration */
13359         vuint32_t NCFSC21:2;             /* NCF 21 state configuration */
13360         vuint32_t NCFSC20:2;             /* NCF 20 state configuration */
13361         vuint32_t NCFSC19:2;             /* NCF 19 state configuration */
13362         vuint32_t NCFSC18:2;             /* NCF 18 state configuration */
13363         vuint32_t NCFSC17:2;             /* NCF 17 state configuration */
13364         vuint32_t NCFSC16:2;             /* NCF 16 state configuration */
13365       } B;
13366     } FCCU_NCFS_CFG1_32B_tag;
13367   
13368     typedef union {                      /* FCCU NCFS Configuration Register 2 */
13369       vuint32_t R;
13370       struct {
13371         vuint32_t NCFSC47:2;             /* NCF 47 state configuration */
13372         vuint32_t NCFSC46:2;             /* NCF 46 state configuration */
13373         vuint32_t NCFSC45:2;             /* NCF 45 state configuration */
13374         vuint32_t NCFSC44:2;             /* NCF 44 state configuration */
13375         vuint32_t NCFSC43:2;             /* NCF 43 state configuration */
13376         vuint32_t NCFSC42:2;             /* NCF 42 state configuration */
13377         vuint32_t NCFSC41:2;             /* NCF 41 state configuration */
13378         vuint32_t NCFSC40:2;             /* NCF 40 state configuration */
13379         vuint32_t NCFSC39:2;             /* NCF 39 state configuration */
13380         vuint32_t NCFSC38:2;             /* NCF 38 state configuration */
13381         vuint32_t NCFSC37:2;             /* NCF 37 state configuration */
13382         vuint32_t NCFSC36:2;             /* NCF 36 state configuration */
13383         vuint32_t NCFSC35:2;             /* NCF 35 state configuration */
13384         vuint32_t NCFSC34:2;             /* NCF 34 state configuration */
13385         vuint32_t NCFSC33:2;             /* NCF 33 state configuration */
13386         vuint32_t NCFSC32:2;             /* NCF 32 state configuration */
13387       } B;
13388     } FCCU_NCFS_CFG2_32B_tag;
13389   
13390     typedef union {                      /* FCCU NCFS Configuration Register 3 */
13391       vuint32_t R;
13392       struct {
13393         vuint32_t NCFSC63:2;             /* NCF 63 state configuration */
13394         vuint32_t NCFSC62:2;             /* NCF 62 state configuration */
13395         vuint32_t NCFSC61:2;             /* NCF 61 state configuration */
13396         vuint32_t NCFSC60:2;             /* NCF 60 state configuration */
13397         vuint32_t NCFSC59:2;             /* NCF 59 state configuration */
13398         vuint32_t NCFSC58:2;             /* NCF 58 state configuration */
13399         vuint32_t NCFSC57:2;             /* NCF 57 state configuration */
13400         vuint32_t NCFSC56:2;             /* NCF 56 state configuration */
13401         vuint32_t NCFSC55:2;             /* NCF 55 state configuration */
13402         vuint32_t NCFSC54:2;             /* NCF 54 state configuration */
13403         vuint32_t NCFSC53:2;             /* NCF 53 state configuration */
13404         vuint32_t NCFSC52:2;             /* NCF 52 state configuration */
13405         vuint32_t NCFSC51:2;             /* NCF 51 state configuration */
13406         vuint32_t NCFSC50:2;             /* NCF 50 state configuration */
13407         vuint32_t NCFSC49:2;             /* NCF 49 state configuration */
13408         vuint32_t NCFSC48:2;             /* NCF 48 state configuration */
13409       } B;
13410     } FCCU_NCFS_CFG3_32B_tag;
13411   
13412     typedef union {                      /* FCCU NCFS Configuration Register 4 */
13413       vuint32_t R;
13414       struct {
13415         vuint32_t NCFSC79:2;             /* NCF 79 state configuration */
13416         vuint32_t NCFSC78:2;             /* NCF 78 state configuration */
13417         vuint32_t NCFSC77:2;             /* NCF 77 state configuration */
13418         vuint32_t NCFSC76:2;             /* NCF 76 state configuration */
13419         vuint32_t NCFSC75:2;             /* NCF 75 state configuration */
13420         vuint32_t NCFSC74:2;             /* NCF 74 state configuration */
13421         vuint32_t NCFSC73:2;             /* NCF 73 state configuration */
13422         vuint32_t NCFSC72:2;             /* NCF 72 state configuration */
13423         vuint32_t NCFSC71:2;             /* NCF 71 state configuration */
13424         vuint32_t NCFSC70:2;             /* NCF 70 state configuration */
13425         vuint32_t NCFSC69:2;             /* NCF 69 state configuration */
13426         vuint32_t NCFSC68:2;             /* NCF 68 state configuration */
13427         vuint32_t NCFSC67:2;             /* NCF 67 state configuration */
13428         vuint32_t NCFSC66:2;             /* NCF 66 state configuration */
13429         vuint32_t NCFSC65:2;             /* NCF 65 state configuration */
13430         vuint32_t NCFSC64:2;             /* NCF 64 state configuration */
13431       } B;
13432     } FCCU_NCFS_CFG4_32B_tag;
13433   
13434     typedef union {                      /* FCCU NCFS Configuration Register 5 */
13435       vuint32_t R;
13436       struct {
13437         vuint32_t NCFSC95:2;             /* NCF 95 state configuration */
13438         vuint32_t NCFSC94:2;             /* NCF 94 state configuration */
13439         vuint32_t NCFSC93:2;             /* NCF 93 state configuration */
13440         vuint32_t NCFSC92:2;             /* NCF 92 state configuration */
13441         vuint32_t NCFSC91:2;             /* NCF 91 state configuration */
13442         vuint32_t NCFSC90:2;             /* NCF 90 state configuration */
13443         vuint32_t NCFSC89:2;             /* NCF 89 state configuration */
13444         vuint32_t NCFSC88:2;             /* NCF 88 state configuration */
13445         vuint32_t NCFSC87:2;             /* NCF 87 state configuration */
13446         vuint32_t NCFSC86:2;             /* NCF 86 state configuration */
13447         vuint32_t NCFSC85:2;             /* NCF 85 state configuration */
13448         vuint32_t NCFSC84:2;             /* NCF 84 state configuration */
13449         vuint32_t NCFSC83:2;             /* NCF 83 state configuration */
13450         vuint32_t NCFSC82:2;             /* NCF 82 state configuration */
13451         vuint32_t NCFSC81:2;             /* NCF 81 state configuration */
13452         vuint32_t NCFSC80:2;             /* NCF 80 state configuration */
13453       } B;
13454     } FCCU_NCFS_CFG5_32B_tag;
13455   
13456     typedef union {                      /* FCCU NCFS Configuration Register 6 */
13457       vuint32_t R;
13458       struct {
13459         vuint32_t NCFSC111:2;            /* NCF 111 state configuration */
13460         vuint32_t NCFSC110:2;            /* NCF 110 state configuration */
13461         vuint32_t NCFSC109:2;            /* NCF 109 state configuration */
13462         vuint32_t NCFSC108:2;            /* NCF 108 state configuration */
13463         vuint32_t NCFSC107:2;            /* NCF 107 state configuration */
13464         vuint32_t NCFSC106:2;            /* NCF 106 state configuration */
13465         vuint32_t NCFSC105:2;            /* NCF 105 state configuration */
13466         vuint32_t NCFSC104:2;            /* NCF 104 state configuration */
13467         vuint32_t NCFSC103:2;            /* NCF 103 state configuration */
13468         vuint32_t NCFSC102:2;            /* NCF 102 state configuration */
13469         vuint32_t NCFSC101:2;            /* NCF 101 state configuration */
13470         vuint32_t NCFSC100:2;            /* NCF 100 state configuration */
13471         vuint32_t NCFSC99:2;             /* NCF 99 state configuration */
13472         vuint32_t NCFSC98:2;             /* NCF 98 state configuration */
13473         vuint32_t NCFSC97:2;             /* NCF 97 state configuration */
13474         vuint32_t NCFSC96:2;             /* NCF 96 state configuration */
13475       } B;
13476     } FCCU_NCFS_CFG6_32B_tag;
13477   
13478     typedef union {                      /* FCCU NCFS Configuration Register 7 */
13479       vuint32_t R;
13480       struct {
13481         vuint32_t NCFSC127:2;            /* NCF 127 state configuration */
13482         vuint32_t NCFSC126:2;            /* NCF 126 state configuration */
13483         vuint32_t NCFSC125:2;            /* NCF 125 state configuration */
13484         vuint32_t NCFSC124:2;            /* NCF 124 state configuration */
13485         vuint32_t NCFSC123:2;            /* NCF 123 state configuration */
13486         vuint32_t NCFSC122:2;            /* NCF 122 state configuration */
13487         vuint32_t NCFSC121:2;            /* NCF 121 state configuration */
13488         vuint32_t NCFSC120:2;            /* NCF 120 state configuration */
13489         vuint32_t NCFSC119:2;            /* NCF 119 state configuration */
13490         vuint32_t NCFSC118:2;            /* NCF 118 state configuration */
13491         vuint32_t NCFSC117:2;            /* NCF 117 state configuration */
13492         vuint32_t NCFSC116:2;            /* NCF 116 state configuration */
13493         vuint32_t NCFSC115:2;            /* NCF 115 state configuration */
13494         vuint32_t NCFSC114:2;            /* NCF 114 state configuration */
13495         vuint32_t NCFSC113:2;            /* NCF 113 state configuration */
13496         vuint32_t NCFSC112:2;            /* NCF 112 state configuration */
13497       } B;
13498     } FCCU_NCFS_CFG7_32B_tag;
13499   
13500     typedef union {                      /* FCCU CF Status Register 0 */
13501       vuint32_t R;
13502       struct {
13503         vuint32_t CFS31:1;               /* CF 31 status */
13504         vuint32_t CFS30:1;               /* CF 30 status */
13505         vuint32_t CFS29:1;               /* CF 29 status */
13506         vuint32_t CFS28:1;               /* CF 28 status */
13507         vuint32_t CFS27:1;               /* CF 27 status */
13508         vuint32_t CFS26:1;               /* CF 26 status */
13509         vuint32_t CFS25:1;               /* CF 25 status */
13510         vuint32_t CFS24:1;               /* CF 24 status */
13511         vuint32_t CFS23:1;               /* CF 23 status */
13512         vuint32_t CFS22:1;               /* CF 22 status */
13513         vuint32_t CFS21:1;               /* CF 21 status */
13514         vuint32_t CFS20:1;               /* CF 20 status */
13515         vuint32_t CFS19:1;               /* CF 19 status */
13516         vuint32_t CFS18:1;               /* CF 18 status */
13517         vuint32_t CFS17:1;               /* CF 17 status */
13518         vuint32_t CFS16:1;               /* CF 16 status */
13519         vuint32_t CFS15:1;               /* CF 15 status */
13520         vuint32_t CFS14:1;               /* CF 14 status */
13521         vuint32_t CFS13:1;               /* CF 13 status */
13522         vuint32_t CFS12:1;               /* CF 12 status */
13523         vuint32_t CFS11:1;               /* CF 11 status */
13524         vuint32_t CFS10:1;               /* CF 10 status */
13525         vuint32_t CFS9:1;                /* CF 9 status */
13526         vuint32_t CFS8:1;                /* CF 8 status */
13527         vuint32_t CFS7:1;                /* CF 7 status */
13528         vuint32_t CFS6:1;                /* CF 6 status */
13529         vuint32_t CFS5:1;                /* CF 5 status */
13530         vuint32_t CFS4:1;                /* CF 4 status */
13531         vuint32_t CFS3:1;                /* CF 3 status */
13532         vuint32_t CFS2:1;                /* CF 2 status */
13533         vuint32_t CFS1:1;                /* CF 1 status */
13534         vuint32_t CFS0:1;                /* CF 0 status */
13535       } B;
13536     } FCCU_CF_S0_32B_tag;
13537   
13538     typedef union {                      /* FCCU CF Status Register 1 */
13539       vuint32_t R;
13540       struct {
13541         vuint32_t CFS63:1;               /* CF 63 status */
13542         vuint32_t CFS62:1;               /* CF 62 status */
13543         vuint32_t CFS61:1;               /* CF 61 status */
13544         vuint32_t CFS60:1;               /* CF 60 status */
13545         vuint32_t CFS59:1;               /* CF 59 status */
13546         vuint32_t CFS58:1;               /* CF 58 status */
13547         vuint32_t CFS57:1;               /* CF 57 status */
13548         vuint32_t CFS56:1;               /* CF 56 status */
13549         vuint32_t CFS55:1;               /* CF 55 status */
13550         vuint32_t CFS54:1;               /* CF 54 status */
13551         vuint32_t CFS53:1;               /* CF 53 status */
13552         vuint32_t CFS52:1;               /* CF 52 status */
13553         vuint32_t CFS51:1;               /* CF 51 status */
13554         vuint32_t CFS50:1;               /* CF 50 status */
13555         vuint32_t CFS49:1;               /* CF 49 status */
13556         vuint32_t CFS48:1;               /* CF 48 status */
13557         vuint32_t CFS47:1;               /* CF 47 status */
13558         vuint32_t CFS46:1;               /* CF 46 status */
13559         vuint32_t CFS45:1;               /* CF 45 status */
13560         vuint32_t CFS44:1;               /* CF 44 status */
13561         vuint32_t CFS43:1;               /* CF 43 status */
13562         vuint32_t CFS42:1;               /* CF 42 status */
13563         vuint32_t CFS41:1;               /* CF 41 status */
13564         vuint32_t CFS40:1;               /* CF 40 status */
13565         vuint32_t CFS39:1;               /* CF 39 status */
13566         vuint32_t CFS38:1;               /* CF 38 status */
13567         vuint32_t CFS37:1;               /* CF 37 status */
13568         vuint32_t CFS36:1;               /* CF 36 status */
13569         vuint32_t CFS35:1;               /* CF 35 status */
13570         vuint32_t CFS34:1;               /* CF 34 status */
13571         vuint32_t CFS33:1;               /* CF 33 status */
13572         vuint32_t CFS32:1;               /* CF 32 status */
13573       } B;
13574     } FCCU_CF_S1_32B_tag;
13575   
13576     typedef union {                      /* FCCU CF Status Register 2 */
13577       vuint32_t R;
13578       struct {
13579         vuint32_t CFS95:1;               /* CF 95 status */
13580         vuint32_t CFS94:1;               /* CF 94 status */
13581         vuint32_t CFS93:1;               /* CF 93 status */
13582         vuint32_t CFS92:1;               /* CF 92 status */
13583         vuint32_t CFS91:1;               /* CF 91 status */
13584         vuint32_t CFS90:1;               /* CF 90 status */
13585         vuint32_t CFS89:1;               /* CF 89 status */
13586         vuint32_t CFS88:1;               /* CF 88 status */
13587         vuint32_t CFS87:1;               /* CF 87 status */
13588         vuint32_t CFS86:1;               /* CF 86 status */
13589         vuint32_t CFS85:1;               /* CF 85 status */
13590         vuint32_t CFS84:1;               /* CF 84 status */
13591         vuint32_t CFS83:1;               /* CF 83 status */
13592         vuint32_t CFS82:1;               /* CF 82 status */
13593         vuint32_t CFS81:1;               /* CF 81 status */
13594         vuint32_t CFS80:1;               /* CF 80 status */
13595         vuint32_t CFS79:1;               /* CF 79 status */
13596         vuint32_t CFS78:1;               /* CF 78 status */
13597         vuint32_t CFS77:1;               /* CF 77 status */
13598         vuint32_t CFS76:1;               /* CF 76 status */
13599         vuint32_t CFS75:1;               /* CF 75 status */
13600         vuint32_t CFS74:1;               /* CF 74 status */
13601         vuint32_t CFS73:1;               /* CF 73 status */
13602         vuint32_t CFS72:1;               /* CF 72 status */
13603         vuint32_t CFS71:1;               /* CF 71 status */
13604         vuint32_t CFS70:1;               /* CF 70 status */
13605         vuint32_t CFS69:1;               /* CF 69 status */
13606         vuint32_t CFS68:1;               /* CF 68 status */
13607         vuint32_t CFS67:1;               /* CF 67 status */
13608         vuint32_t CFS66:1;               /* CF 66 status */
13609         vuint32_t CFS65:1;               /* CF 65 status */
13610         vuint32_t CFS64:1;               /* CF 64 status */
13611       } B;
13612     } FCCU_CF_S2_32B_tag;
13613   
13614     typedef union {                      /* FCCU CF Status Register 3 */
13615       vuint32_t R;
13616       struct {
13617         vuint32_t CFS127:1;              /* CF 127 status */
13618         vuint32_t CFS126:1;              /* CF 126 status */
13619         vuint32_t CFS125:1;              /* CF 125 status */
13620         vuint32_t CFS124:1;              /* CF 124 status */
13621         vuint32_t CFS123:1;              /* CF 123 status */
13622         vuint32_t CFS122:1;              /* CF 122 status */
13623         vuint32_t CFS121:1;              /* CF 121 status */
13624         vuint32_t CFS120:1;              /* CF 120 status */
13625         vuint32_t CFS119:1;              /* CF 119 status */
13626         vuint32_t CFS118:1;              /* CF 118 status */
13627         vuint32_t CFS117:1;              /* CF 117 status */
13628         vuint32_t CFS116:1;              /* CF 116 status */
13629         vuint32_t CFS115:1;              /* CF 115 status */
13630         vuint32_t CFS114:1;              /* CF 114 status */
13631         vuint32_t CFS113:1;              /* CF 113 status */
13632         vuint32_t CFS112:1;              /* CF 112 status */
13633         vuint32_t CFS111:1;              /* CF 111 status */
13634         vuint32_t CFS110:1;              /* CF 110 status */
13635         vuint32_t CFS109:1;              /* CF 109 status */
13636         vuint32_t CFS108:1;              /* CF 108 status */
13637         vuint32_t CFS107:1;              /* CF 107 status */
13638         vuint32_t CFS106:1;              /* CF 106 status */
13639         vuint32_t CFS105:1;              /* CF 105 status */
13640         vuint32_t CFS104:1;              /* CF 104 status */
13641         vuint32_t CFS103:1;              /* CF 103 status */
13642         vuint32_t CFS102:1;              /* CF 102 status */
13643         vuint32_t CFS101:1;              /* CF 101 status */
13644         vuint32_t CFS100:1;              /* CF 100 status */
13645         vuint32_t CFS99:1;               /* CF 99 status */
13646         vuint32_t CFS98:1;               /* CF 98 status */
13647         vuint32_t CFS97:1;               /* CF 97 status */
13648         vuint32_t CFS96:1;               /* CF 96 status */
13649       } B;
13650     } FCCU_CF_S3_32B_tag;
13651   
13652     typedef union {                      /* FCCU_CFK - FCCU CF Key Register */
13653       vuint32_t R;
13654     } FCCU_CFK_32B_tag;
13655   
13656     typedef union {                      /* FCCU NCF Status Register 0 */
13657       vuint32_t R;
13658       struct {
13659         vuint32_t NCFS31:1;              /* NCF 31 status */
13660         vuint32_t NCFS30:1;              /* NCF 30 status */
13661         vuint32_t NCFS29:1;              /* NCF 29 status */
13662         vuint32_t NCFS28:1;              /* NCF 28 status */
13663         vuint32_t NCFS27:1;              /* NCF 27 status */
13664         vuint32_t NCFS26:1;              /* NCF 26 status */
13665         vuint32_t NCFS25:1;              /* NCF 25 status */
13666         vuint32_t NCFS24:1;              /* NCF 24 status */
13667         vuint32_t NCFS23:1;              /* NCF 23 status */
13668         vuint32_t NCFS22:1;              /* NCF 22 status */
13669         vuint32_t NCFS21:1;              /* NCF 21 status */
13670         vuint32_t NCFS20:1;              /* NCF 20 status */
13671         vuint32_t NCFS19:1;              /* NCF 19 status */
13672         vuint32_t NCFS18:1;              /* NCF 18 status */
13673         vuint32_t NCFS17:1;              /* NCF 17 status */
13674         vuint32_t NCFS16:1;              /* NCF 16 status */
13675         vuint32_t NCFS15:1;              /* NCF 15 status */
13676         vuint32_t NCFS14:1;              /* NCF 14 status */
13677         vuint32_t NCFS13:1;              /* NCF 13 status */
13678         vuint32_t NCFS12:1;              /* NCF 12 status */
13679         vuint32_t NCFS11:1;              /* NCF 11 status */
13680         vuint32_t NCFS10:1;              /* NCF 10 status */
13681         vuint32_t NCFS9:1;               /* NCF 9 status */
13682         vuint32_t NCFS8:1;               /* NCF 8 status */
13683         vuint32_t NCFS7:1;               /* NCF 7 status */
13684         vuint32_t NCFS6:1;               /* NCF 6 status */
13685         vuint32_t NCFS5:1;               /* NCF 5 status */
13686         vuint32_t NCFS4:1;               /* NCF 4 status */
13687         vuint32_t NCFS3:1;               /* NCF 3 status */
13688         vuint32_t NCFS2:1;               /* NCF 2 status */
13689         vuint32_t NCFS1:1;               /* NCF 1 status */
13690         vuint32_t NCFS0:1;               /* NCF 0 status */
13691       } B;
13692     } FCCU_NCF_S0_32B_tag;
13693   
13694     typedef union {                      /* FCCU NCF Status Register 1 */
13695       vuint32_t R;
13696       struct {
13697         vuint32_t NCFS63:1;              /* NCF 63 status */
13698         vuint32_t NCFS62:1;              /* NCF 62 status */
13699         vuint32_t NCFS61:1;              /* NCF 61 status */
13700         vuint32_t NCFS60:1;              /* NCF 60 status */
13701         vuint32_t NCFS59:1;              /* NCF 59 status */
13702         vuint32_t NCFS58:1;              /* NCF 58 status */
13703         vuint32_t NCFS57:1;              /* NCF 57 status */
13704         vuint32_t NCFS56:1;              /* NCF 56 status */
13705         vuint32_t NCFS55:1;              /* NCF 55 status */
13706         vuint32_t NCFS54:1;              /* NCF 54 status */
13707         vuint32_t NCFS53:1;              /* NCF 53 status */
13708         vuint32_t NCFS52:1;              /* NCF 52 status */
13709         vuint32_t NCFS51:1;              /* NCF 51 status */
13710         vuint32_t NCFS50:1;              /* NCF 50 status */
13711         vuint32_t NCFS49:1;              /* NCF 49 status */
13712         vuint32_t NCFS48:1;              /* NCF 48 status */
13713         vuint32_t NCFS47:1;              /* NCF 47 status */
13714         vuint32_t NCFS46:1;              /* NCF 46 status */
13715         vuint32_t NCFS45:1;              /* NCF 45 status */
13716         vuint32_t NCFS44:1;              /* NCF 44 status */
13717         vuint32_t NCFS43:1;              /* NCF 43 status */
13718         vuint32_t NCFS42:1;              /* NCF 42 status */
13719         vuint32_t NCFS41:1;              /* NCF 41 status */
13720         vuint32_t NCFS40:1;              /* NCF 40 status */
13721         vuint32_t NCFS39:1;              /* NCF 39 status */
13722         vuint32_t NCFS38:1;              /* NCF 38 status */
13723         vuint32_t NCFS37:1;              /* NCF 37 status */
13724         vuint32_t NCFS36:1;              /* NCF 36 status */
13725         vuint32_t NCFS35:1;              /* NCF 35 status */
13726         vuint32_t NCFS34:1;              /* NCF 34 status */
13727         vuint32_t NCFS33:1;              /* NCF 33 status */
13728         vuint32_t NCFS32:1;              /* NCF 32 status */
13729       } B;
13730     } FCCU_NCF_S1_32B_tag;
13731   
13732     typedef union {                      /* FCCU NCF Status Register 2 */
13733       vuint32_t R;
13734       struct {
13735         vuint32_t NCFS95:1;              /* NCF 95 status */
13736         vuint32_t NCFS94:1;              /* NCF 94 status */
13737         vuint32_t NCFS93:1;              /* NCF 93 status */
13738         vuint32_t NCFS92:1;              /* NCF 92 status */
13739         vuint32_t NCFS91:1;              /* NCF 91 status */
13740         vuint32_t NCFS90:1;              /* NCF 90 status */
13741         vuint32_t NCFS89:1;              /* NCF 89 status */
13742         vuint32_t NCFS88:1;              /* NCF 88 status */
13743         vuint32_t NCFS87:1;              /* NCF 87 status */
13744         vuint32_t NCFS86:1;              /* NCF 86 status */
13745         vuint32_t NCFS85:1;              /* NCF 85 status */
13746         vuint32_t NCFS84:1;              /* NCF 84 status */
13747         vuint32_t NCFS83:1;              /* NCF 83 status */
13748         vuint32_t NCFS82:1;              /* NCF 82 status */
13749         vuint32_t NCFS81:1;              /* NCF 81 status */
13750         vuint32_t NCFS80:1;              /* NCF 80 status */
13751         vuint32_t NCFS79:1;              /* NCF 79 status */
13752         vuint32_t NCFS78:1;              /* NCF 78 status */
13753         vuint32_t NCFS77:1;              /* NCF 77 status */
13754         vuint32_t NCFS76:1;              /* NCF 76 status */
13755         vuint32_t NCFS75:1;              /* NCF 75 status */
13756         vuint32_t NCFS74:1;              /* NCF 74 status */
13757         vuint32_t NCFS73:1;              /* NCF 73 status */
13758         vuint32_t NCFS72:1;              /* NCF 72 status */
13759         vuint32_t NCFS71:1;              /* NCF 71 status */
13760         vuint32_t NCFS70:1;              /* NCF 70 status */
13761         vuint32_t NCFS69:1;              /* NCF 69 status */
13762         vuint32_t NCFS68:1;              /* NCF 68 status */
13763         vuint32_t NCFS67:1;              /* NCF 67 status */
13764         vuint32_t NCFS66:1;              /* NCF 66 status */
13765         vuint32_t NCFS65:1;              /* NCF 65 status */
13766         vuint32_t NCFS64:1;              /* NCF 64 status */
13767       } B;
13768     } FCCU_NCF_S2_32B_tag;
13769   
13770     typedef union {                      /* FCCU NCF Status Register 3 */
13771       vuint32_t R;
13772       struct {
13773         vuint32_t NCFS127:1;             /* NCF 127 status */
13774         vuint32_t NCFS126:1;             /* NCF 126 status */
13775         vuint32_t NCFS125:1;             /* NCF 125 status */
13776         vuint32_t NCFS124:1;             /* NCF 124 status */
13777         vuint32_t NCFS123:1;             /* NCF 123 status */
13778         vuint32_t NCFS122:1;             /* NCF 122 status */
13779         vuint32_t NCFS121:1;             /* NCF 121 status */
13780         vuint32_t NCFS120:1;             /* NCF 120 status */
13781         vuint32_t NCFS119:1;             /* NCF 119 status */
13782         vuint32_t NCFS118:1;             /* NCF 118 status */
13783         vuint32_t NCFS117:1;             /* NCF 117 status */
13784         vuint32_t NCFS116:1;             /* NCF 116 status */
13785         vuint32_t NCFS115:1;             /* NCF 115 status */
13786         vuint32_t NCFS114:1;             /* NCF 114 status */
13787         vuint32_t NCFS113:1;             /* NCF 113 status */
13788         vuint32_t NCFS112:1;             /* NCF 112 status */
13789         vuint32_t NCFS111:1;             /* NCF 111 status */
13790         vuint32_t NCFS110:1;             /* NCF 110 status */
13791         vuint32_t NCFS109:1;             /* NCF 109 status */
13792         vuint32_t NCFS108:1;             /* NCF 108 status */
13793         vuint32_t NCFS107:1;             /* NCF 107 status */
13794         vuint32_t NCFS106:1;             /* NCF 106 status */
13795         vuint32_t NCFS105:1;             /* NCF 105 status */
13796         vuint32_t NCFS104:1;             /* NCF 104 status */
13797         vuint32_t NCFS103:1;             /* NCF 103 status */
13798         vuint32_t NCFS102:1;             /* NCF 102 status */
13799         vuint32_t NCFS101:1;             /* NCF 101 status */
13800         vuint32_t NCFS100:1;             /* NCF 100 status */
13801         vuint32_t NCFS99:1;              /* NCF 99 status */
13802         vuint32_t NCFS98:1;              /* NCF 98 status */
13803         vuint32_t NCFS97:1;              /* NCF 97 status */
13804         vuint32_t NCFS96:1;              /* NCF 96 status */
13805       } B;
13806     } FCCU_NCF_S3_32B_tag;
13807   
13808     typedef union {                      /* FCCU_NCFK - FCCU NCF Key Register */
13809       vuint32_t R;
13810     } FCCU_NCFK_32B_tag;
13811   
13812     typedef union {                      /* FCCU NCF Enable Register 0 */
13813       vuint32_t R;
13814       struct {
13815         vuint32_t NCFE31:1;              /* NCF 31 enable */
13816         vuint32_t NCFE30:1;              /* NCF 30 enable */
13817         vuint32_t NCFE29:1;              /* NCF 29 enable */
13818         vuint32_t NCFE28:1;              /* NCF 28 enable */
13819         vuint32_t NCFE27:1;              /* NCF 27 enable */
13820         vuint32_t NCFE26:1;              /* NCF 26 enable */
13821         vuint32_t NCFE25:1;              /* NCF 25 enable */
13822         vuint32_t NCFE24:1;              /* NCF 24 enable */
13823         vuint32_t NCFE23:1;              /* NCF 23 enable */
13824         vuint32_t NCFE22:1;              /* NCF 22 enable */
13825         vuint32_t NCFE21:1;              /* NCF 21 enable */
13826         vuint32_t NCFE20:1;              /* NCF 20 enable */
13827         vuint32_t NCFE19:1;              /* NCF 19 enable */
13828         vuint32_t NCFE18:1;              /* NCF 18 enable */
13829         vuint32_t NCFE17:1;              /* NCF 17 enable */
13830         vuint32_t NCFE16:1;              /* NCF 16 enable */
13831         vuint32_t NCFE15:1;              /* NCF 15 enable */
13832         vuint32_t NCFE14:1;              /* NCF 14 enable */
13833         vuint32_t NCFE13:1;              /* NCF 13 enable */
13834         vuint32_t NCFE12:1;              /* NCF 12 enable */
13835         vuint32_t NCFE11:1;              /* NCF 11 enable */
13836         vuint32_t NCFE10:1;              /* NCF 10 enable */
13837         vuint32_t NCFE9:1;               /* NCF 9 enable */
13838         vuint32_t NCFE8:1;               /* NCF 8 enable */
13839         vuint32_t NCFE7:1;               /* NCF 7 enable */
13840         vuint32_t NCFE6:1;               /* NCF 6 enable */
13841         vuint32_t NCFE5:1;               /* NCF 5 enable */
13842         vuint32_t NCFE4:1;               /* NCF 4 enable */
13843         vuint32_t NCFE3:1;               /* NCF 3 enable */
13844         vuint32_t NCFE2:1;               /* NCF 2 enable */
13845         vuint32_t NCFE1:1;               /* NCF 1 enable */
13846         vuint32_t NCFE0:1;               /* NCF 0 enable */
13847       } B;
13848     } FCCU_NCF_E0_32B_tag;
13849   
13850     typedef union {                      /* FCCU NCF Enable Register 1 */
13851       vuint32_t R;
13852       struct {
13853         vuint32_t NCFE63:1;              /* NCF 63 enable */
13854         vuint32_t NCFE62:1;              /* NCF 62 enable */
13855         vuint32_t NCFE61:1;              /* NCF 61 enable */
13856         vuint32_t NCFE60:1;              /* NCF 60 enable */
13857         vuint32_t NCFE59:1;              /* NCF 59 enable */
13858         vuint32_t NCFE58:1;              /* NCF 58 enable */
13859         vuint32_t NCFE57:1;              /* NCF 57 enable */
13860         vuint32_t NCFE56:1;              /* NCF 56 enable */
13861         vuint32_t NCFE55:1;              /* NCF 55 enable */
13862         vuint32_t NCFE54:1;              /* NCF 54 enable */
13863         vuint32_t NCFE53:1;              /* NCF 53 enable */
13864         vuint32_t NCFE52:1;              /* NCF 52 enable */
13865         vuint32_t NCFE51:1;              /* NCF 51 enable */
13866         vuint32_t NCFE50:1;              /* NCF 50 enable */
13867         vuint32_t NCFE49:1;              /* NCF 49 enable */
13868         vuint32_t NCFE48:1;              /* NCF 48 enable */
13869         vuint32_t NCFE47:1;              /* NCF 47 enable */
13870         vuint32_t NCFE46:1;              /* NCF 46 enable */
13871         vuint32_t NCFE45:1;              /* NCF 45 enable */
13872         vuint32_t NCFE44:1;              /* NCF 44 enable */
13873         vuint32_t NCFE43:1;              /* NCF 43 enable */
13874         vuint32_t NCFE42:1;              /* NCF 42 enable */
13875         vuint32_t NCFE41:1;              /* NCF 41 enable */
13876         vuint32_t NCFE40:1;              /* NCF 40 enable */
13877         vuint32_t NCFE39:1;              /* NCF 39 enable */
13878         vuint32_t NCFE38:1;              /* NCF 38 enable */
13879         vuint32_t NCFE37:1;              /* NCF 37 enable */
13880         vuint32_t NCFE36:1;              /* NCF 36 enable */
13881         vuint32_t NCFE35:1;              /* NCF 35 enable */
13882         vuint32_t NCFE34:1;              /* NCF 34 enable */
13883         vuint32_t NCFE33:1;              /* NCF 33 enable */
13884         vuint32_t NCFE32:1;              /* NCF 32 enable */
13885       } B;
13886     } FCCU_NCF_E1_32B_tag;
13887   
13888     typedef union {                      /* FCCU NCF Enable Register 2 */
13889       vuint32_t R;
13890       struct {
13891         vuint32_t NCFE95:1;              /* NCF 95 enable */
13892         vuint32_t NCFE94:1;              /* NCF 94 enable */
13893         vuint32_t NCFE93:1;              /* NCF 93 enable */
13894         vuint32_t NCFE92:1;              /* NCF 92 enable */
13895         vuint32_t NCFE91:1;              /* NCF 91 enable */
13896         vuint32_t NCFE90:1;              /* NCF 90 enable */
13897         vuint32_t NCFE89:1;              /* NCF 89 enable */
13898         vuint32_t NCFE88:1;              /* NCF 88 enable */
13899         vuint32_t NCFE87:1;              /* NCF 87 enable */
13900         vuint32_t NCFE86:1;              /* NCF 86 enable */
13901         vuint32_t NCFE85:1;              /* NCF 85 enable */
13902         vuint32_t NCFE84:1;              /* NCF 84 enable */
13903         vuint32_t NCFE83:1;              /* NCF 83 enable */
13904         vuint32_t NCFE82:1;              /* NCF 82 enable */
13905         vuint32_t NCFE81:1;              /* NCF 81 enable */
13906         vuint32_t NCFE80:1;              /* NCF 80 enable */
13907         vuint32_t NCFE79:1;              /* NCF 79 enable */
13908         vuint32_t NCFE78:1;              /* NCF 78 enable */
13909         vuint32_t NCFE77:1;              /* NCF 77 enable */
13910         vuint32_t NCFE76:1;              /* NCF 76 enable */
13911         vuint32_t NCFE75:1;              /* NCF 75 enable */
13912         vuint32_t NCFE74:1;              /* NCF 74 enable */
13913         vuint32_t NCFE73:1;              /* NCF 73 enable */
13914         vuint32_t NCFE72:1;              /* NCF 72 enable */
13915         vuint32_t NCFE71:1;              /* NCF 71 enable */
13916         vuint32_t NCFE70:1;              /* NCF 70 enable */
13917         vuint32_t NCFE69:1;              /* NCF 69 enable */
13918         vuint32_t NCFE68:1;              /* NCF 68 enable */
13919         vuint32_t NCFE67:1;              /* NCF 67 enable */
13920         vuint32_t NCFE66:1;              /* NCF 66 enable */
13921         vuint32_t NCFE65:1;              /* NCF 65 enable */
13922         vuint32_t NCFE64:1;              /* NCF 64 enable */
13923       } B;
13924     } FCCU_NCF_E2_32B_tag;
13925   
13926     typedef union {                      /* FCCU NCF Enable Register 3 */
13927       vuint32_t R;
13928       struct {
13929         vuint32_t NCFE127:1;             /* NCF 127 enable */
13930         vuint32_t NCFE126:1;             /* NCF 126 enable */
13931         vuint32_t NCFE125:1;             /* NCF 125 enable */
13932         vuint32_t NCFE124:1;             /* NCF 124 enable */
13933         vuint32_t NCFE123:1;             /* NCF 123 enable */
13934         vuint32_t NCFE122:1;             /* NCF 122 enable */
13935         vuint32_t NCFE121:1;             /* NCF 121 enable */
13936         vuint32_t NCFE120:1;             /* NCF 120 enable */
13937         vuint32_t NCFE119:1;             /* NCF 119 enable */
13938         vuint32_t NCFE118:1;             /* NCF 118 enable */
13939         vuint32_t NCFE117:1;             /* NCF 117 enable */
13940         vuint32_t NCFE116:1;             /* NCF 116 enable */
13941         vuint32_t NCFE115:1;             /* NCF 115 enable */
13942         vuint32_t NCFE114:1;             /* NCF 114 enable */
13943         vuint32_t NCFE113:1;             /* NCF 113 enable */
13944         vuint32_t NCFE112:1;             /* NCF 112 enable */
13945         vuint32_t NCFE111:1;             /* NCF 111 enable */
13946         vuint32_t NCFE110:1;             /* NCF 110 enable */
13947         vuint32_t NCFE109:1;             /* NCF 109 enable */
13948         vuint32_t NCFE108:1;             /* NCF 108 enable */
13949         vuint32_t NCFE107:1;             /* NCF 107 enable */
13950         vuint32_t NCFE106:1;             /* NCF 106 enable */
13951         vuint32_t NCFE105:1;             /* NCF 105 enable */
13952         vuint32_t NCFE104:1;             /* NCF 104 enable */
13953         vuint32_t NCFE103:1;             /* NCF 103 enable */
13954         vuint32_t NCFE102:1;             /* NCF 102 enable */
13955         vuint32_t NCFE101:1;             /* NCF 101 enable */
13956         vuint32_t NCFE100:1;             /* NCF 100 enable */
13957         vuint32_t NCFE99:1;              /* NCF 99 enable */
13958         vuint32_t NCFE98:1;              /* NCF 98 enable */
13959         vuint32_t NCFE97:1;              /* NCF 97 enable */
13960         vuint32_t NCFE96:1;              /* NCF 96 enable */
13961       } B;
13962     } FCCU_NCF_E3_32B_tag;
13963   
13964     typedef union {                      /* FCCU NCF Time-out Enable Register 0 */
13965       vuint32_t R;
13966       struct {
13967         vuint32_t NCFTOE31:1;            /* NCF 31 time-out enable */
13968         vuint32_t NCFTOE30:1;            /* NCF 30 time-out enable */
13969         vuint32_t NCFTOE29:1;            /* NCF 29 time-out enable */
13970         vuint32_t NCFTOE28:1;            /* NCF 28 time-out enable */
13971         vuint32_t NCFTOE27:1;            /* NCF 27 time-out enable */
13972         vuint32_t NCFTOE26:1;            /* NCF 26 time-out enable */
13973         vuint32_t NCFTOE25:1;            /* NCF 25 time-out enable */
13974         vuint32_t NCFTOE24:1;            /* NCF 24 time-out enable */
13975         vuint32_t NCFTOE23:1;            /* NCF 23 time-out enable */
13976         vuint32_t NCFTOE22:1;            /* NCF 22 time-out enable */
13977         vuint32_t NCFTOE21:1;            /* NCF 21 time-out enable */
13978         vuint32_t NCFTOE20:1;            /* NCF 20 time-out enable */
13979         vuint32_t NCFTOE19:1;            /* NCF 19 time-out enable */
13980         vuint32_t NCFTOE18:1;            /* NCF 18 time-out enable */
13981         vuint32_t NCFTOE17:1;            /* NCF 17 time-out enable */
13982         vuint32_t NCFTOE16:1;            /* NCF 16 time-out enable */
13983         vuint32_t NCFTOE15:1;            /* NCF 15 time-out enable */
13984         vuint32_t NCFTOE14:1;            /* NCF 14 time-out enable */
13985         vuint32_t NCFTOE13:1;            /* NCF 13 time-out enable */
13986         vuint32_t NCFTOE12:1;            /* NCF 12 time-out enable */
13987         vuint32_t NCFTOE11:1;            /* NCF 11 time-out enable */
13988         vuint32_t NCFTOE10:1;            /* NCF 10 time-out enable */
13989         vuint32_t NCFTOE9:1;             /* NCF 9 time-out enable */
13990         vuint32_t NCFTOE8:1;             /* NCF 8 time-out enable */
13991         vuint32_t NCFTOE7:1;             /* NCF 7 time-out enable */
13992         vuint32_t NCFTOE6:1;             /* NCF 6 time-out enable */
13993         vuint32_t NCFTOE5:1;             /* NCF 5 time-out enable */
13994         vuint32_t NCFTOE4:1;             /* NCF 4 time-out enable */
13995         vuint32_t NCFTOE3:1;             /* NCF 3 time-out enable */
13996         vuint32_t NCFTOE2:1;             /* NCF 2 time-out enable */
13997         vuint32_t NCFTOE1:1;             /* NCF 1 time-out enable */
13998         vuint32_t NCFTOE0:1;             /* NCF 0 time-out enable */
13999       } B;
14000     } FCCU_NCF_TOE0_32B_tag;
14001   
14002     typedef union {                      /* FCCU NCF Time-out Enable Register 1 */
14003       vuint32_t R;
14004       struct {
14005         vuint32_t NCFTOE63:1;            /* NCF 63 time-out enable */
14006         vuint32_t NCFTOE62:1;            /* NCF 62 time-out enable */
14007         vuint32_t NCFTOE61:1;            /* NCF 61 time-out enable */
14008         vuint32_t NCFTOE60:1;            /* NCF 60 time-out enable */
14009         vuint32_t NCFTOE59:1;            /* NCF 59 time-out enable */
14010         vuint32_t NCFTOE58:1;            /* NCF 58 time-out enable */
14011         vuint32_t NCFTOE57:1;            /* NCF 57 time-out enable */
14012         vuint32_t NCFTOE56:1;            /* NCF 56 time-out enable */
14013         vuint32_t NCFTOE55:1;            /* NCF 55 time-out enable */
14014         vuint32_t NCFTOE54:1;            /* NCF 54 time-out enable */
14015         vuint32_t NCFTOE53:1;            /* NCF 53 time-out enable */
14016         vuint32_t NCFTOE52:1;            /* NCF 52 time-out enable */
14017         vuint32_t NCFTOE51:1;            /* NCF 51 time-out enable */
14018         vuint32_t NCFTOE50:1;            /* NCF 50 time-out enable */
14019         vuint32_t NCFTOE49:1;            /* NCF 49 time-out enable */
14020         vuint32_t NCFTOE48:1;            /* NCF 48 time-out enable */
14021         vuint32_t NCFTOE47:1;            /* NCF 47 time-out enable */
14022         vuint32_t NCFTOE46:1;            /* NCF 46 time-out enable */
14023         vuint32_t NCFTOE45:1;            /* NCF 45 time-out enable */
14024         vuint32_t NCFTOE44:1;            /* NCF 44 time-out enable */
14025         vuint32_t NCFTOE43:1;            /* NCF 43 time-out enable */
14026         vuint32_t NCFTOE42:1;            /* NCF 42 time-out enable */
14027         vuint32_t NCFTOE41:1;            /* NCF 41 time-out enable */
14028         vuint32_t NCFTOE40:1;            /* NCF 40 time-out enable */
14029         vuint32_t NCFTOE39:1;            /* NCF 39 time-out enable */
14030         vuint32_t NCFTOE38:1;            /* NCF 38 time-out enable */
14031         vuint32_t NCFTOE37:1;            /* NCF 37 time-out enable */
14032         vuint32_t NCFTOE36:1;            /* NCF 36 time-out enable */
14033         vuint32_t NCFTOE35:1;            /* NCF 35 time-out enable */
14034         vuint32_t NCFTOE34:1;            /* NCF 34 time-out enable */
14035         vuint32_t NCFTOE33:1;            /* NCF 33 time-out enable */
14036         vuint32_t NCFTOE32:1;            /* NCF 32 time-out enable */
14037       } B;
14038     } FCCU_NCF_TOE1_32B_tag;
14039   
14040     typedef union {                      /* FCCU NCF Time-out Enable Register 2 */
14041       vuint32_t R;
14042       struct {
14043         vuint32_t NCFTOE95:1;            /* NCF 95 time-out enable */
14044         vuint32_t NCFTOE94:1;            /* NCF 94 time-out enable */
14045         vuint32_t NCFTOE93:1;            /* NCF 93 time-out enable */
14046         vuint32_t NCFTOE92:1;            /* NCF 92 time-out enable */
14047         vuint32_t NCFTOE91:1;            /* NCF 91 time-out enable */
14048         vuint32_t NCFTOE90:1;            /* NCF 90 time-out enable */
14049         vuint32_t NCFTOE89:1;            /* NCF 89 time-out enable */
14050         vuint32_t NCFTOE88:1;            /* NCF 88 time-out enable */
14051         vuint32_t NCFTOE87:1;            /* NCF 87 time-out enable */
14052         vuint32_t NCFTOE86:1;            /* NCF 86 time-out enable */
14053         vuint32_t NCFTOE85:1;            /* NCF 85 time-out enable */
14054         vuint32_t NCFTOE84:1;            /* NCF 84 time-out enable */
14055         vuint32_t NCFTOE83:1;            /* NCF 83 time-out enable */
14056         vuint32_t NCFTOE82:1;            /* NCF 82 time-out enable */
14057         vuint32_t NCFTOE81:1;            /* NCF 81 time-out enable */
14058         vuint32_t NCFTOE80:1;            /* NCF 80 time-out enable */
14059         vuint32_t NCFTOE79:1;            /* NCF 79 time-out enable */
14060         vuint32_t NCFTOE78:1;            /* NCF 78 time-out enable */
14061         vuint32_t NCFTOE77:1;            /* NCF 77 time-out enable */
14062         vuint32_t NCFTOE76:1;            /* NCF 76 time-out enable */
14063         vuint32_t NCFTOE75:1;            /* NCF 75 time-out enable */
14064         vuint32_t NCFTOE74:1;            /* NCF 74 time-out enable */
14065         vuint32_t NCFTOE73:1;            /* NCF 73 time-out enable */
14066         vuint32_t NCFTOE72:1;            /* NCF 72 time-out enable */
14067         vuint32_t NCFTOE71:1;            /* NCF 71 time-out enable */
14068         vuint32_t NCFTOE70:1;            /* NCF 70 time-out enable */
14069         vuint32_t NCFTOE69:1;            /* NCF 69 time-out enable */
14070         vuint32_t NCFTOE68:1;            /* NCF 68 time-out enable */
14071         vuint32_t NCFTOE67:1;            /* NCF 67 time-out enable */
14072         vuint32_t NCFTOE66:1;            /* NCF 66 time-out enable */
14073         vuint32_t NCFTOE65:1;            /* NCF 65 time-out enable */
14074         vuint32_t NCFTOE64:1;            /* NCF 64 time-out enable */
14075       } B;
14076     } FCCU_NCF_TOE2_32B_tag;
14077   
14078     typedef union {                      /* FCCU NCF Time-out Enable Register 3 */
14079       vuint32_t R;
14080       struct {
14081         vuint32_t NCFTOE127:1;           /* NCF 127 time-out enable */
14082         vuint32_t NCFTOE126:1;           /* NCF 126 time-out enable */
14083         vuint32_t NCFTOE125:1;           /* NCF 125 time-out enable */
14084         vuint32_t NCFTOE124:1;           /* NCF 124 time-out enable */
14085         vuint32_t NCFTOE123:1;           /* NCF 123 time-out enable */
14086         vuint32_t NCFTOE122:1;           /* NCF 122 time-out enable */
14087         vuint32_t NCFTOE121:1;           /* NCF 121 time-out enable */
14088         vuint32_t NCFTOE120:1;           /* NCF 120 time-out enable */
14089         vuint32_t NCFTOE119:1;           /* NCF 119 time-out enable */
14090         vuint32_t NCFTOE118:1;           /* NCF 118 time-out enable */
14091         vuint32_t NCFTOE117:1;           /* NCF 117 time-out enable */
14092         vuint32_t NCFTOE116:1;           /* NCF 116 time-out enable */
14093         vuint32_t NCFTOE115:1;           /* NCF 115 time-out enable */
14094         vuint32_t NCFTOE114:1;           /* NCF 114 time-out enable */
14095         vuint32_t NCFTOE113:1;           /* NCF 113 time-out enable */
14096         vuint32_t NCFTOE112:1;           /* NCF 112 time-out enable */
14097         vuint32_t NCFTOE111:1;           /* NCF 111 time-out enable */
14098         vuint32_t NCFTOE110:1;           /* NCF 110 time-out enable */
14099         vuint32_t NCFTOE109:1;           /* NCF 109 time-out enable */
14100         vuint32_t NCFTOE108:1;           /* NCF 108 time-out enable */
14101         vuint32_t NCFTOE107:1;           /* NCF 107 time-out enable */
14102         vuint32_t NCFTOE106:1;           /* NCF 106 time-out enable */
14103         vuint32_t NCFTOE105:1;           /* NCF 105 time-out enable */
14104         vuint32_t NCFTOE104:1;           /* NCF 104 time-out enable */
14105         vuint32_t NCFTOE103:1;           /* NCF 103 time-out enable */
14106         vuint32_t NCFTOE102:1;           /* NCF 102 time-out enable */
14107         vuint32_t NCFTOE101:1;           /* NCF 101 time-out enable */
14108         vuint32_t NCFTOE100:1;           /* NCF 100 time-out enable */
14109         vuint32_t NCFTOE99:1;            /* NCF 99 time-out enable */
14110         vuint32_t NCFTOE98:1;            /* NCF 98 time-out enable */
14111         vuint32_t NCFTOE97:1;            /* NCF 97 time-out enable */
14112         vuint32_t NCFTOE96:1;            /* NCF 96 time-out enable */
14113       } B;
14114     } FCCU_NCF_TOE3_32B_tag;
14115   
14116     typedef union {                      /* FCCU_NCF_TO - FCCU NCF Time-out Register */
14117       vuint32_t R;
14118     } FCCU_NCF_TO_32B_tag;
14119   
14120     typedef union {                      /* FCCU_CFG_TO - FCCU CFG Timeout Register */
14121       vuint32_t R;
14122       struct {
14123        vuint32_t:
14124         29;
14125         vuint32_t TO:3;                  /* Configuration time-out */
14126       } B;
14127     } FCCU_CFG_TO_32B_tag;
14128   
14129     typedef union {                      /* FCCU_EINOUT - FCCU IO Control Register */
14130       vuint32_t R;
14131       struct {
14132        vuint32_t:
14133         26;
14134         vuint32_t EIN1:1;                /* Error input 1 */
14135         vuint32_t EIN0:1;                /* Error input 0 */
14136        vuint32_t:
14137         2;
14138         vuint32_t EOUT1:1;               /* Error out 1 */
14139         vuint32_t EOUT0:1;               /* Error out 0 */
14140       } B;
14141     } FCCU_EINOUT_32B_tag;
14142   
14143     typedef union {                      /* FCCU_STAT - FCCU Status Register */
14144       vuint32_t R;
14145       struct {
14146        vuint32_t:
14147         29;
14148         vuint32_t STATUS:3;              /* FCCU status */
14149       } B;
14150     } FCCU_STAT_32B_tag;
14151   
14152     typedef union {                      /* FCCU_NAFS - FCCU NA Freeze Status Register */
14153       vuint32_t R;
14154       struct {
14155        vuint32_t:
14156         24;
14157         vuint32_t N2AFSTATUS:8;          /* Normal to Alarm Frozen Status */
14158       } B;
14159     } FCCU_NAFS_32B_tag;
14160   
14161     typedef union {                      /* FCCU_AFFS - FCCU AF Freeze Status Register */
14162       vuint32_t R;
14163       struct {
14164        vuint32_t:
14165         22;
14166         vuint32_t AFFS_SRC:2;            /* Fault source */
14167         vuint32_t A2AFSTATUS:8;          /* Alarm to Fault Frozen Status */
14168       } B;
14169     } FCCU_AFFS_32B_tag;
14170   
14171     typedef union {                      /* FCCU_NFFS - FCCU NF Freeze Status Register */
14172       vuint32_t R;
14173       struct {
14174        vuint32_t:
14175         22;
14176         vuint32_t NFFS_SRC:2;            /* Fault source */
14177         vuint32_t NFFS_NFFS:8;           /* Normal to Fault Frozen Status */
14178       } B;
14179     } FCCU_NFFS_32B_tag;
14180   
14181     typedef union {                      /* FCCU_FAFS - FCCU FA Freeze Status Register */
14182       vuint32_t R;
14183       struct {
14184        vuint32_t:
14185         24;
14186         vuint32_t FAFS_FAFS:8;           /* Fault to Normal Frozen Status */
14187       } B;
14188     } FCCU_FAFS_32B_tag;
14189   
14190     typedef union {                      /* FCCU_SCFS - FCCU SC Freeze Status Register */
14191       vuint32_t R;
14192       struct {
14193        vuint32_t:
14194         30;
14195         vuint32_t RCCS1:1;               /* RCC1 Status */
14196         vuint32_t RCCS0:1;               /* RCC0 Status */
14197       } B;
14198     } FCCU_SCFS_32B_tag;
14199   
14200     typedef union {                      /* FCCU_CFF - FCCU CF Fake Register */
14201       vuint32_t R;
14202       struct {
14203        vuint32_t:
14204         25;
14205         vuint32_t FCFC:7;                /* Fake critical fault code */
14206       } B;
14207     } FCCU_CFF_32B_tag;
14208   
14209     typedef union {                      /* FCCU_NCFF - FCCU NCF Fake Register */
14210       vuint32_t R;
14211       struct {
14212        vuint32_t:
14213         25;
14214         vuint32_t FNCFC:7;               /* Fake non-critical fault code */
14215       } B;
14216     } FCCU_NCFF_32B_tag;
14217   
14218     typedef union {                      /* FCCU_IRQ_STAT - FCCU IRQ Status Register */
14219       vuint32_t R;
14220       struct {
14221        vuint32_t:
14222         29;
14223         vuint32_t NMI_STAT:1;            /* NMI Interrupt Status */
14224         vuint32_t ALRM_STAT:1;           /* Alarm Interrupt Status */
14225         vuint32_t CFG_TO_STAT:1;         /* Configuration Time-out Status */
14226       } B;
14227     } FCCU_IRQ_STAT_32B_tag;
14228   
14229     typedef union {                      /* FCCU_IRQ_EN - FCCU IRQ Enable Register */
14230       vuint32_t R;
14231       struct {
14232        vuint32_t:
14233         31;
14234         vuint32_t CFG_TO_IEN:1;          /* Configuration Time-out Interrupt Enable */
14235       } B;
14236     } FCCU_IRQ_EN_32B_tag;
14237   
14238     typedef union {                      /* FCCU_XTMR - FCCU XTMR Register */
14239       vuint32_t R;
14240       struct {
14241         vuint32_t XTMR_XTMR:32;          /* Alarm/Watchdog/safe request timer */
14242       } B;
14243     } FCCU_XTMR_32B_tag;
14244   
14245     typedef union {                      /* FCCU_MCS - FCCU MCS Register */
14246       vuint32_t R;
14247       struct {
14248         vuint32_t VL3:1;                 /* Valid */
14249         vuint32_t FS3:1;                 /* Fault Status */
14250        vuint32_t:
14251         2;
14252         vuint32_t MCS3:4;                /* Magic Carpet oldest state */
14253         vuint32_t VL2:1;                 /* Valid */
14254         vuint32_t FS2:1;                 /* Fault Status */
14255        vuint32_t:
14256         2;
14257         vuint32_t MCS2:4;                /* Magic Carpet previous-previous state */
14258         vuint32_t VL1:1;                 /* Valid */
14259         vuint32_t FS1:1;                 /* Fault Status */
14260        vuint32_t:
14261         2;
14262         vuint32_t MCS1:4;                /* Magic Carpet previous state */
14263         vuint32_t VL0:1;                 /* Valid */
14264         vuint32_t FS0:1;                 /* Fault Status */
14265        vuint32_t:
14266         2;
14267         vuint32_t MCS0:4;                /* Magic Carpet latest state */
14268       } B;
14269     } FCCU_MCS_32B_tag;
14270   
14271     /* Register layout for generated register(s) CF_CFG... */
14272     typedef union {                      /*  */
14273       vuint32_t R;
14274     } FCCU_CF_CFG_32B_tag;
14275   
14276     /* Register layout for generated register(s) NCF_CFG... */
14277     typedef union {                      /*  */
14278       vuint32_t R;
14279     } FCCU_NCF_CFG_32B_tag;
14280   
14281     /* Register layout for generated register(s) CFS_CFG... */
14282     typedef union {                      /*  */
14283       vuint32_t R;
14284     } FCCU_CFS_CFG_32B_tag;
14285   
14286     /* Register layout for generated register(s) NCFS_CFG... */
14287     typedef union {                      /*  */
14288       vuint32_t R;
14289     } FCCU_NCFS_CFG_32B_tag;
14290   
14291     /* Register layout for generated register(s) CF_S... */
14292     typedef union {                      /*  */
14293       vuint32_t R;
14294     } FCCU_CF_S_32B_tag;
14295   
14296     /* Register layout for generated register(s) NCF_S... */
14297     typedef union {                      /*  */
14298       vuint32_t R;
14299     } FCCU_NCF_S_32B_tag;
14300   
14301     /* Register layout for generated register(s) NCF_E... */
14302     typedef union {                      /*  */
14303       vuint32_t R;
14304     } FCCU_NCF_E_32B_tag;
14305   
14306     /* Register layout for generated register(s) NCF_TOE... */
14307     typedef union {                      /*  */
14308       vuint32_t R;
14309     } FCCU_NCF_TOE_32B_tag;
14310   
14311     typedef struct FCCU_struct_tag {
14312       /* FCCU Control Register */
14313       FCCU_CTRL_32B_tag CTRL;            /* offset: 0x0000 size: 32 bit */
14314   
14315       /* FCCU CTRL Key Register */
14316       FCCU_CTRLK_32B_tag CTRLK;          /* offset: 0x0004 size: 32 bit */
14317   
14318       /* FCCU Configuration Register */
14319       FCCU_CFG_32B_tag CFG;              /* offset: 0x0008 size: 32 bit */
14320       union {
14321         FCCU_CF_CFG_32B_tag CF_CFG[4];   /* offset: 0x000C  (0x0004 x 4) */
14322         struct {
14323           /* FCCU CF Configuration Register 0 */
14324           FCCU_CF_CFG0_32B_tag CF_CFG0;  /* offset: 0x000C size: 32 bit */
14325   
14326           /* FCCU CF Configuration Register 1 */
14327           FCCU_CF_CFG1_32B_tag CF_CFG1;  /* offset: 0x0010 size: 32 bit */
14328   
14329           /* FCCU CF Configuration Register 2 */
14330           FCCU_CF_CFG2_32B_tag CF_CFG2;  /* offset: 0x0014 size: 32 bit */
14331   
14332           /* FCCU CF Configuration Register 3 */
14333           FCCU_CF_CFG3_32B_tag CF_CFG3;  /* offset: 0x0018 size: 32 bit */
14334         };
14335       };
14336   
14337       union {
14338         FCCU_NCF_CFG_32B_tag NCF_CFG[4]; /* offset: 0x001C  (0x0004 x 4) */
14339         struct {
14340           /* FCCU NCF Configuration Register 0 */
14341           FCCU_NCF_CFG0_32B_tag NCF_CFG0;/* offset: 0x001C size: 32 bit */
14342   
14343           /* FCCU NCF Configuration Register 1 */
14344           FCCU_NCF_CFG1_32B_tag NCF_CFG1;/* offset: 0x0020 size: 32 bit */
14345   
14346           /* FCCU NCF Configuration Register 2 */
14347           FCCU_NCF_CFG2_32B_tag NCF_CFG2;/* offset: 0x0024 size: 32 bit */
14348   
14349           /* FCCU NCF Configuration Register 3 */
14350           FCCU_NCF_CFG3_32B_tag NCF_CFG3;/* offset: 0x0028 size: 32 bit */
14351         };
14352       };
14353   
14354       union {
14355         FCCU_CFS_CFG_32B_tag CFS_CFG[8]; /* offset: 0x002C  (0x0004 x 8) */
14356         struct {
14357           /* FCCU CFS Configuration Register 0 */
14358           FCCU_CFS_CFG0_32B_tag CFS_CFG0;/* offset: 0x002C size: 32 bit */
14359   
14360           /* FCCU CFS Configuration Register 1 */
14361           FCCU_CFS_CFG1_32B_tag CFS_CFG1;/* offset: 0x0030 size: 32 bit */
14362   
14363           /* FCCU CFS Configuration Register 2 */
14364           FCCU_CFS_CFG2_32B_tag CFS_CFG2;/* offset: 0x0034 size: 32 bit */
14365   
14366           /* FCCU CFS Configuration Register 3 */
14367           FCCU_CFS_CFG3_32B_tag CFS_CFG3;/* offset: 0x0038 size: 32 bit */
14368   
14369           /* FCCU CFS Configuration Register 4 */
14370           FCCU_CFS_CFG4_32B_tag CFS_CFG4;/* offset: 0x003C size: 32 bit */
14371   
14372           /* FCCU CFS Configuration Register 5 */
14373           FCCU_CFS_CFG5_32B_tag CFS_CFG5;/* offset: 0x0040 size: 32 bit */
14374   
14375           /* FCCU CFS Configuration Register 6 */
14376           FCCU_CFS_CFG6_32B_tag CFS_CFG6;/* offset: 0x0044 size: 32 bit */
14377   
14378           /* FCCU CFS Configuration Register 7 */
14379           FCCU_CFS_CFG7_32B_tag CFS_CFG7;/* offset: 0x0048 size: 32 bit */
14380         };
14381       };
14382   
14383       union {
14384         FCCU_NCFS_CFG_32B_tag NCFS_CFG[8];/* offset: 0x004C  (0x0004 x 8) */
14385         struct {
14386           /* FCCU NCFS Configuration Register 0 */
14387           FCCU_NCFS_CFG0_32B_tag NCFS_CFG0;/* offset: 0x004C size: 32 bit */
14388   
14389           /* FCCU NCFS Configuration Register 1 */
14390           FCCU_NCFS_CFG1_32B_tag NCFS_CFG1;/* offset: 0x0050 size: 32 bit */
14391   
14392           /* FCCU NCFS Configuration Register 2 */
14393           FCCU_NCFS_CFG2_32B_tag NCFS_CFG2;/* offset: 0x0054 size: 32 bit */
14394   
14395           /* FCCU NCFS Configuration Register 3 */
14396           FCCU_NCFS_CFG3_32B_tag NCFS_CFG3;/* offset: 0x0058 size: 32 bit */
14397   
14398           /* FCCU NCFS Configuration Register 4 */
14399           FCCU_NCFS_CFG4_32B_tag NCFS_CFG4;/* offset: 0x005C size: 32 bit */
14400   
14401           /* FCCU NCFS Configuration Register 5 */
14402           FCCU_NCFS_CFG5_32B_tag NCFS_CFG5;/* offset: 0x0060 size: 32 bit */
14403   
14404           /* FCCU NCFS Configuration Register 6 */
14405           FCCU_NCFS_CFG6_32B_tag NCFS_CFG6;/* offset: 0x0064 size: 32 bit */
14406   
14407           /* FCCU NCFS Configuration Register 7 */
14408           FCCU_NCFS_CFG7_32B_tag NCFS_CFG7;/* offset: 0x0068 size: 32 bit */
14409         };
14410       };
14411   
14412       union {
14413         FCCU_CF_S_32B_tag CF_S[4];       /* offset: 0x006C  (0x0004 x 4) */
14414         struct {
14415           /* FCCU CF Status Register 0 */
14416           FCCU_CF_S0_32B_tag CF_S0;      /* offset: 0x006C size: 32 bit */
14417   
14418           /* FCCU CF Status Register 1 */
14419           FCCU_CF_S1_32B_tag CF_S1;      /* offset: 0x0070 size: 32 bit */
14420   
14421           /* FCCU CF Status Register 2 */
14422           FCCU_CF_S2_32B_tag CF_S2;      /* offset: 0x0074 size: 32 bit */
14423   
14424           /* FCCU CF Status Register 3 */
14425           FCCU_CF_S3_32B_tag CF_S3;      /* offset: 0x0078 size: 32 bit */
14426         };
14427       };
14428   
14429       /* FCCU_CFK - FCCU CF Key Register */
14430       FCCU_CFK_32B_tag CFK;              /* offset: 0x007C size: 32 bit */
14431       union {
14432         FCCU_NCF_S_32B_tag NCF_S[4];     /* offset: 0x0080  (0x0004 x 4) */
14433         struct {
14434           /* FCCU NCF Status Register 0 */
14435           FCCU_NCF_S0_32B_tag NCF_S0;    /* offset: 0x0080 size: 32 bit */
14436   
14437           /* FCCU NCF Status Register 1 */
14438           FCCU_NCF_S1_32B_tag NCF_S1;    /* offset: 0x0084 size: 32 bit */
14439   
14440           /* FCCU NCF Status Register 2 */
14441           FCCU_NCF_S2_32B_tag NCF_S2;    /* offset: 0x0088 size: 32 bit */
14442   
14443           /* FCCU NCF Status Register 3 */
14444           FCCU_NCF_S3_32B_tag NCF_S3;    /* offset: 0x008C size: 32 bit */
14445         };
14446       };
14447   
14448       /* FCCU_NCFK - FCCU NCF Key Register */
14449       FCCU_NCFK_32B_tag NCFK;            /* offset: 0x0090 size: 32 bit */
14450       union {
14451         FCCU_NCF_E_32B_tag NCF_E[4];     /* offset: 0x0094  (0x0004 x 4) */
14452         struct {
14453           /* FCCU NCF Enable Register 0 */
14454           FCCU_NCF_E0_32B_tag NCF_E0;    /* offset: 0x0094 size: 32 bit */
14455   
14456           /* FCCU NCF Enable Register 1 */
14457           FCCU_NCF_E1_32B_tag NCF_E1;    /* offset: 0x0098 size: 32 bit */
14458   
14459           /* FCCU NCF Enable Register 2 */
14460           FCCU_NCF_E2_32B_tag NCF_E2;    /* offset: 0x009C size: 32 bit */
14461   
14462           /* FCCU NCF Enable Register 3 */
14463           FCCU_NCF_E3_32B_tag NCF_E3;    /* offset: 0x00A0 size: 32 bit */
14464         };
14465       };
14466   
14467       union {
14468         FCCU_NCF_TOE_32B_tag NCF_TOE[4]; /* offset: 0x00A4  (0x0004 x 4) */
14469         struct {
14470           /* FCCU NCF Time-out Enable Register 0 */
14471           FCCU_NCF_TOE0_32B_tag NCF_TOE0;/* offset: 0x00A4 size: 32 bit */
14472   
14473           /* FCCU NCF Time-out Enable Register 1 */
14474           FCCU_NCF_TOE1_32B_tag NCF_TOE1;/* offset: 0x00A8 size: 32 bit */
14475   
14476           /* FCCU NCF Time-out Enable Register 2 */
14477           FCCU_NCF_TOE2_32B_tag NCF_TOE2;/* offset: 0x00AC size: 32 bit */
14478   
14479           /* FCCU NCF Time-out Enable Register 3 */
14480           FCCU_NCF_TOE3_32B_tag NCF_TOE3;/* offset: 0x00B0 size: 32 bit */
14481         };
14482       };
14483   
14484       /* FCCU_NCF_TO - FCCU NCF Time-out Register */
14485       FCCU_NCF_TO_32B_tag NCF_TO;        /* offset: 0x00B4 size: 32 bit */
14486   
14487       /* FCCU_CFG_TO - FCCU CFG Timeout Register */
14488       FCCU_CFG_TO_32B_tag CFG_TO;        /* offset: 0x00B8 size: 32 bit */
14489   
14490       /* FCCU_EINOUT - FCCU IO Control Register */
14491       FCCU_EINOUT_32B_tag EINOUT;        /* offset: 0x00BC size: 32 bit */
14492   
14493       /* FCCU_STAT - FCCU Status Register */
14494       FCCU_STAT_32B_tag STAT;            /* offset: 0x00C0 size: 32 bit */
14495   
14496       /* FCCU_NAFS - FCCU NA Freeze Status Register */
14497       FCCU_NAFS_32B_tag NAFS;            /* offset: 0x00C4 size: 32 bit */
14498   
14499       /* FCCU_AFFS - FCCU AF Freeze Status Register */
14500       FCCU_AFFS_32B_tag AFFS;            /* offset: 0x00C8 size: 32 bit */
14501   
14502       /* FCCU_NFFS - FCCU NF Freeze Status Register */
14503       FCCU_NFFS_32B_tag NFFS;            /* offset: 0x00CC size: 32 bit */
14504   
14505       /* FCCU_FAFS - FCCU FA Freeze Status Register */
14506       FCCU_FAFS_32B_tag FAFS;            /* offset: 0x00D0 size: 32 bit */
14507   
14508       /* FCCU_SCFS - FCCU SC Freeze Status Register */
14509       FCCU_SCFS_32B_tag SCFS;            /* offset: 0x00D4 size: 32 bit */
14510   
14511       /* FCCU_CFF - FCCU CF Fake Register */
14512       FCCU_CFF_32B_tag CFF;              /* offset: 0x00D8 size: 32 bit */
14513   
14514       /* FCCU_NCFF - FCCU NCF Fake Register */
14515       FCCU_NCFF_32B_tag NCFF;            /* offset: 0x00DC size: 32 bit */
14516   
14517       /* FCCU_IRQ_STAT - FCCU IRQ Status Register */
14518       FCCU_IRQ_STAT_32B_tag IRQ_STAT;    /* offset: 0x00E0 size: 32 bit */
14519   
14520       /* FCCU_IRQ_EN - FCCU IRQ Enable Register */
14521       FCCU_IRQ_EN_32B_tag IRQ_EN;        /* offset: 0x00E4 size: 32 bit */
14522   
14523       /* FCCU_XTMR - FCCU XTMR Register */
14524       FCCU_XTMR_32B_tag XTMR;            /* offset: 0x00E8 size: 32 bit */
14525   
14526       /* FCCU_MCS - FCCU MCS Register */
14527       FCCU_MCS_32B_tag MCS;              /* offset: 0x00EC size: 32 bit */
14528       int8_t FCCU_reserved_00F0[16144];
14529     } FCCU_tag;
14530   
14531   #define FCCU                           (*(volatile FCCU_tag *) 0xFFE6C000UL)
14532   
14533     /****************************************************************/
14534     /*                                                              */
14535     /* Module: SGENDIG  */
14536     /*                                                              */
14537     /****************************************************************/
14538     typedef union {                      /* SGENDIG_CTRL - SGENDIG Control Register */
14539       vuint32_t R;
14540       struct {
14541         vuint32_t LDOS:1;                /* Operation Status */
14542        vuint32_t:
14543         1;
14544         vuint32_t IOAMPL:4;              /* Define the AMPLitude value on I/O pad */
14545        vuint32_t:
14546         2;
14547         vuint32_t SEMASK:1;              /* Sine wave generator Error MASK interrupt register */
14548        vuint32_t:
14549         5;
14550         vuint32_t S0H1:1;                /* Operation Status: enter PD in Stop Mode */
14551         vuint32_t PDS:1;                 /* Operation Status: Power Down Mode */
14552         vuint32_t IOFREQ:16;             /* Define the FREQuency value on I/O pad */
14553       } B;
14554     } SGENDIG_CTRL_32B_tag;
14555   
14556     typedef union {                      /* SGENDIG_IRQE - SGENDIG Interrupt Request Enable  Register */
14557       vuint32_t R;
14558       struct {
14559        vuint32_t:
14560         8;
14561         vuint32_t SERR:1;                /* Sine wave generator Error bit */
14562        vuint32_t:
14563         3;
14564         vuint32_t FERR:1;                /* Sine wave generator Force Error bit */
14565        vuint32_t:
14566         19;
14567       } B;
14568     } SGENDIG_IRQE_32B_tag;
14569   
14570     typedef struct SGENDIG_struct_tag {
14571       /* SGENDIG_CTRL - SGENDIG Control Register */
14572       SGENDIG_CTRL_32B_tag CTRL;         /* offset: 0x0000 size: 32 bit */
14573   
14574       /* SGENDIG_IRQE - SGENDIG Interrupt Request Enable  Register */
14575       SGENDIG_IRQE_32B_tag IRQE;         /* offset: 0x0004 size: 32 bit */
14576       int8_t SGENDIG_reserved_0008[16376];
14577     } SGENDIG_tag;
14578   
14579   #define SGENDIG                        (*(volatile SGENDIG_tag *) 0xFFE78000UL)
14580   
14581     /****************************************************************/
14582     /*                                                              */
14583     /* Module: PFLASH2P_LCA  */
14584     /*                                                              */
14585     /****************************************************************/
14586     typedef union {                      /* PFLASH2P_LCA_PFCR0 - Platform Flash Configuration Register 0 */
14587       vuint32_t R;
14588       struct {
14589         vuint32_t B02_APC:5;             /* Bank0+2 Address Pipelining Control */
14590         vuint32_t B02_WWSC:5;            /* Bank0+2 Write Wait State Control */
14591         vuint32_t B02_RWSC:5;            /* Bank0+2 Read Wait State Control */
14592         vuint32_t B02_RWWC2:1;           /* Bank 0+2 Read While Write Control, bit 2 */
14593         vuint32_t B02_RWWC1:1;           /* Bank 0+2 Read While Write Control, bit 1 */
14594         vuint32_t B02_P1_BCFG:2;         /* Bank0+2 Port 1 Page Buffer Configuration */
14595         vuint32_t B02_P1_DPFE:1;         /* Bank0+2 Port 1 Data Prefetch Enable */
14596         vuint32_t B02_P1_IPFE:1;         /* Bank0+2 Port 1 Inst Prefetch Enable */
14597         vuint32_t B02_P1_PFLM:2;         /* Bank0+2 Port 1 Prefetch Limit */
14598         vuint32_t B02_P1_BFE:1;          /* Bank0+2 Port 1 Buffer Enable */
14599         vuint32_t B02_RWWC0:1;           /* Bank 0+2 Read While Write Control, bit 0 */
14600         vuint32_t B02_P0_BCFG:2;         /* Bank0+2 Port 0 Page Buffer Configuration */
14601         vuint32_t B02_P0_DPFE:1;         /* Bank0+2 Port 0 Data Prefetch Enable */
14602         vuint32_t B02_P0_IPFE:1;         /* Bank0+2 Port 0 Inst Prefetch Enable */
14603         vuint32_t B02_P0_PFLM:2;         /* Bank0+2 Port 0 Prefetch Limit */
14604         vuint32_t B02_P0_BFE:1;          /* Bank0+2 Port 0 Buffer Enable */
14605       } B;
14606     } PFLASH2P_LCA_PFCR0_32B_tag;
14607   
14608     typedef union {                      /* PFLASH2P_LCA_PFCR1 - Platform Flash Configuration Register 1 */
14609       vuint32_t R;
14610       struct {
14611         vuint32_t B1_APC:5;              /* Bank 1 Address Pipelining Control */
14612         vuint32_t B1_WWSC:5;             /* Bank 1 Write Wait State Control */
14613         vuint32_t B1_RWSC:5;             /* Bank 1 Read Wait State Control */
14614         vuint32_t B1_RWWC2:1;            /* Bank1 Read While Write Control, bit 2 */
14615         vuint32_t B1_RWWC1:1;            /* Bank1 Read While Write Control, bit 1 */
14616        vuint32_t:
14617         6;
14618         vuint32_t B1_P1_BFE:1;           /* Bank 1 Port 1 Buffer Enable */
14619         vuint32_t B1_RWWC0:1;            /* Bank1 Read While Write Control, bit 0 */
14620        vuint32_t:
14621         6;
14622         vuint32_t B1_P0_BFE:1;           /* Bank 1 Port 0 Buffer Enable */
14623       } B;
14624     } PFLASH2P_LCA_PFCR1_32B_tag;
14625   
14626     typedef union {                      /* PFLASH2P_LCA_PFAPR - Platform Flash Access Protection Register */
14627       vuint32_t R;
14628       struct {
14629        vuint32_t:
14630         6;
14631         vuint32_t ARBM:2;                /* Arbitration Mode */
14632         vuint32_t M7PFD:1;               /* Master x Prefetch Disable */
14633         vuint32_t M6PFD:1;               /* Master x Prefetch Disable */
14634         vuint32_t M5PFD:1;               /* Master x Prefetch Disable */
14635         vuint32_t M4PFD:1;               /* Master x Prefetch Disable */
14636         vuint32_t M3PFD:1;               /* Master x Prefetch Disable */
14637         vuint32_t M2PFD:1;               /* Master x Prefetch Disable */
14638         vuint32_t M1PFD:1;               /* Master x Prefetch Disable */
14639         vuint32_t M0PFD:1;               /* Master x Prefetch Disable */
14640         vuint32_t M7AP:2;                /* Master 7 Access Protection */
14641         vuint32_t M6AP:2;                /* Master 6 Access Protection */
14642         vuint32_t M5AP:2;                /* Master 5 Access Protection */
14643         vuint32_t M4AP:2;                /* Master 4 Access Protection */
14644         vuint32_t M3AP:2;                /* Master 3 Access Protection */
14645         vuint32_t M2AP:2;                /* Master 2 Access Protection */
14646         vuint32_t M1AP:2;                /* Master 1 Access Protection */
14647         vuint32_t M0AP:2;                /* Master 0 Access Protection */
14648       } B;
14649     } PFLASH2P_LCA_PFAPR_32B_tag;
14650   
14651     typedef struct PFLASH2P_LCA_struct_tag {
14652       int8_t PFLASH2P_LCA_reserved_0000[28];
14653   
14654       /* PFLASH2P_LCA_PFCR0 - Platform Flash Configuration Register 0 */
14655       PFLASH2P_LCA_PFCR0_32B_tag PFCR0;  /* offset: 0x001C size: 32 bit */
14656   
14657       /* PFLASH2P_LCA_PFCR1 - Platform Flash Configuration Register 1 */
14658       PFLASH2P_LCA_PFCR1_32B_tag PFCR1;  /* offset: 0x0020 size: 32 bit */
14659   
14660       /* PFLASH2P_LCA_PFAPR - Platform Flash Access Protection Register */
14661       PFLASH2P_LCA_PFAPR_32B_tag PFAPR;  /* offset: 0x0024 size: 32 bit */
14662       int8_t PFLASH2P_LCA_reserved_0028[16344];
14663     } PFLASH2P_LCA_tag;
14664   
14665   #define PFLASH2P_LCA                   (*(volatile PFLASH2P_LCA_tag *) 0xFFE88000UL)
14666   
14667     /****************************************************************/
14668     /*                                                              */
14669     /* Module: PBRIDGE  */
14670     /*                                                              */
14671     /****************************************************************/
14672     typedef union {                      /* MPROT - Master Privilege Registers */
14673       vuint32_t R;
14674       struct {
14675         vuint32_t MPROT0_MBW:1;          /* Master 0 Buffer Writes */
14676         vuint32_t MPROT0_MTR:1;          /* Master 0 Trusted for Reads */
14677         vuint32_t MPROT0_MTW:1;          /* Master 0 Trusted for Writes */
14678         vuint32_t MPROT0_MPL:1;          /* Master 0 Priviledge Level */
14679         vuint32_t MPROT1_MBW:1;          /* Master 1 Buffer Writes */
14680         vuint32_t MPROT1_MTR:1;          /* Master 1 Trusted for Reads */
14681         vuint32_t MPROT1_MTW:1;          /* Master 1 Trusted for Writes */
14682         vuint32_t MPROT1_MPL:1;          /* Master 1 Priviledge Level */
14683         vuint32_t MPROT2_MBW:1;          /* Master 2 Buffer Writes */
14684         vuint32_t MPROT2_MTR:1;          /* Master 2 Trusted for Reads */
14685         vuint32_t MPROT2_MTW:1;          /* Master 2 Trusted for Writes */
14686         vuint32_t MPROT2_MPL:1;          /* Master 2 Priviledge Level */
14687         vuint32_t MPROT3_MBW:1;          /* Master 3 Buffer Writes */
14688         vuint32_t MPROT3_MTR:1;          /* Master 3 Trusted for Reads */
14689         vuint32_t MPROT3_MTW:1;          /* Master 3 Trusted for Writes */
14690         vuint32_t MPROT3_MPL:1;          /* Master 3 Priviledge Level */
14691         vuint32_t MPROT4_MBW:1;          /* Master 4 Buffer Writes */
14692         vuint32_t MPROT4_MTR:1;          /* Master 4 Trusted for Reads */
14693         vuint32_t MPROT4_MTW:1;          /* Master 4 Trusted for Writes */
14694         vuint32_t MPROT4_MPL:1;          /* Master 4 Priviledge Level */
14695         vuint32_t MPROT5_MBW:1;          /* Master 5 Buffer Writes */
14696         vuint32_t MPROT5_MTR:1;          /* Master 5 Trusted for Reads */
14697         vuint32_t MPROT5_MTW:1;          /* Master 5 Trusted for Writes */
14698         vuint32_t MPROT5_MPL:1;          /* Master 5 Priviledge Level */
14699         vuint32_t MPROT6_MBW:1;          /* Master 6 Buffer Writes */
14700         vuint32_t MPROT6_MTR:1;          /* Master 6 Trusted for Reads */
14701         vuint32_t MPROT6_MTW:1;          /* Master 6 Trusted for Writes */
14702         vuint32_t MPROT6_MPL:1;          /* Master 6 Priviledge Level */
14703         vuint32_t MPROT7_MBW:1;          /* Master 7 Buffer Writes */
14704         vuint32_t MPROT7_MTR:1;          /* Master 7 Trusted for Reads */
14705         vuint32_t MPROT7_MTW:1;          /* Master 7 Trusted for Writes */
14706         vuint32_t MPROT7_MPL:1;          /* Master 7 Priviledge Level */
14707       } B;
14708     } PBRIDGE_MPROT0_7_32B_tag;
14709   
14710     typedef union {                      /* MPROT - Master Privilege Registers */
14711       vuint32_t R;
14712       struct {
14713         vuint32_t MPROT8_MBW:1;          /* Master 8 Buffer Writes */
14714         vuint32_t MPROT8_MTR:1;          /* Master 8 Trusted for Reads */
14715         vuint32_t MPROT8_MTW:1;          /* Master 8 Trusted for Writes */
14716         vuint32_t MPROT8_MPL:1;          /* Master 8 Priviledge Level */
14717         vuint32_t MPROT9_MBW:1;          /* Master 9 Buffer Writes */
14718         vuint32_t MPROT9_MTR:1;          /* Master 9 Trusted for Reads */
14719         vuint32_t MPROT9_MTW:1;          /* Master 9 Trusted for Writes */
14720         vuint32_t MPROT9_MPL:1;          /* Master 9 Priviledge Level */
14721         vuint32_t MPROT10_MBW:1;         /* Master 10 Buffer Writes */
14722         vuint32_t MPROT10_MTR:1;         /* Master 10 Trusted for Reads */
14723         vuint32_t MPROT10_MTW:1;         /* Master 10 Trusted for Writes */
14724         vuint32_t MPROT10_MPL:1;         /* Master 10 Priviledge Level */
14725         vuint32_t MPROT11_MBW:1;         /* Master 11 Buffer Writes */
14726         vuint32_t MPROT11_MTR:1;         /* Master 11 Trusted for Reads */
14727         vuint32_t MPROT11_MTW:1;         /* Master 11 Trusted for Writes */
14728         vuint32_t MPROT11_MPL:1;         /* Master 11 Priviledge Level */
14729         vuint32_t MPROT12_MBW:1;         /* Master 12 Buffer Writes */
14730         vuint32_t MPROT12_MTR:1;         /* Master 12 Trusted for Reads */
14731         vuint32_t MPROT12_MTW:1;         /* Master 12 Trusted for Writes */
14732         vuint32_t MPROT12_MPL:1;         /* Master 12 Priviledge Level */
14733         vuint32_t MPROT13_MBW:1;         /* Master 13 Buffer Writes */
14734         vuint32_t MPROT13_MTR:1;         /* Master 13 Trusted for Reads */
14735         vuint32_t MPROT13_MTW:1;         /* Master 13 Trusted for Writes */
14736         vuint32_t MPROT13_MPL:1;         /* Master 13 Priviledge Level */
14737         vuint32_t MPROT14_MBW:1;         /* Master 14 Buffer Writes */
14738         vuint32_t MPROT14_MTR:1;         /* Master 14 Trusted for Reads */
14739         vuint32_t MPROT14_MTW:1;         /* Master 14 Trusted for Writes */
14740         vuint32_t MPROT14_MPL:1;         /* Master 14 Priviledge Level */
14741         vuint32_t MPROT15_MBW:1;         /* Master 15 Buffer Writes */
14742         vuint32_t MPROT15_MTR:1;         /* Master 15 Trusted for Reads */
14743         vuint32_t MPROT15_MTW:1;         /* Master 15 Trusted for Writes */
14744         vuint32_t MPROT15_MPL:1;         /* Master 15 Priviledge Level */
14745       } B;
14746     } PBRIDGE_MPROT8_15_32B_tag;
14747   
14748     typedef union {                      /* PACR0_7 - Peripheral Access Control Registers */
14749       vuint32_t R;
14750       struct {
14751         vuint32_t PACR0_BW:1;            /* Buffer Writes */
14752         vuint32_t PACR0_SP:1;            /* Supervisor Protect */
14753         vuint32_t PACR0_WP:1;            /* Write Protect */
14754         vuint32_t PACR0_TP:1;            /* Trusted Protect */
14755         vuint32_t PACR1_BW:1;            /* Buffer Writes */
14756         vuint32_t PACR1_SP:1;            /* Supervisor Protect */
14757         vuint32_t PACR1_WP:1;            /* Write Protect */
14758         vuint32_t PACR1_TP:1;            /* Trusted Protect */
14759         vuint32_t PACR2_BW:1;            /* Buffer Writes */
14760         vuint32_t PACR2_SP:1;            /* Supervisor Protect */
14761         vuint32_t PACR2_WP:1;            /* Write Protect */
14762         vuint32_t PACR2_TP:1;            /* Trusted Protect */
14763         vuint32_t PACR3_BW:1;            /* Buffer Writes */
14764         vuint32_t PACR3_SP:1;            /* Supervisor Protect */
14765         vuint32_t PACR3_WP:1;            /* Write Protect */
14766         vuint32_t PACR3_TP:1;            /* Trusted Protect */
14767         vuint32_t PACR4_BW:1;            /* Buffer Writes */
14768         vuint32_t PACR4_SP:1;            /* Supervisor Protect */
14769         vuint32_t PACR4_WP:1;            /* Write Protect */
14770         vuint32_t PACR4_TP:1;            /* Trusted Protect */
14771         vuint32_t PACR5_BW:1;            /* Buffer Writes */
14772         vuint32_t PACR5_SP:1;            /* Supervisor Protect */
14773         vuint32_t PACR5_WP:1;            /* Write Protect */
14774         vuint32_t PACR5_TP:1;            /* Trusted Protect */
14775         vuint32_t PACR6_BW:1;            /* Buffer Writes */
14776         vuint32_t PACR6_SP:1;            /* Supervisor Protect */
14777         vuint32_t PACR6_WP:1;            /* Write Protect */
14778         vuint32_t PACR6_TP:1;            /* Trusted Protect */
14779         vuint32_t PACR7_BW:1;            /* Buffer Writes */
14780         vuint32_t PACR7_SP:1;            /* Supervisor Protect */
14781         vuint32_t PACR7_WP:1;            /* Write Protect */
14782         vuint32_t PACR7_TP:1;            /* Trusted Protect */
14783       } B;
14784     } PBRIDGE_PACR0_7_32B_tag;
14785   
14786     typedef union {                      /* PACR8_15 - Peripheral Access Control Registers */
14787       vuint32_t R;
14788       struct {
14789         vuint32_t PACR8_BW:1;            /* Buffer Writes */
14790         vuint32_t PACR8_SP:1;            /* Supervisor Protect */
14791         vuint32_t PACR8_WP:1;            /* Write Protect */
14792         vuint32_t PACR8_TP:1;            /* Trusted Protect */
14793         vuint32_t PACR9_BW:1;            /* Buffer Writes */
14794         vuint32_t PACR9_SP:1;            /* Supervisor Protect */
14795         vuint32_t PACR9_WP:1;            /* Write Protect */
14796         vuint32_t PACR9_TP:1;            /* Trusted Protect */
14797         vuint32_t PACR10_BW:1;           /* Buffer Writes */
14798         vuint32_t PACR10_SP:1;           /* Supervisor Protect */
14799         vuint32_t PACR10_WP:1;           /* Write Protect */
14800         vuint32_t PACR10_TP:1;           /* Trusted Protect */
14801         vuint32_t PACR11_BW:1;           /* Buffer Writes */
14802         vuint32_t PACR11_SP:1;           /* Supervisor Protect */
14803         vuint32_t PACR11_WP:1;           /* Write Protect */
14804         vuint32_t PACR11_TP:1;           /* Trusted Protect */
14805         vuint32_t PACR12_BW:1;           /* Buffer Writes */
14806         vuint32_t PACR12_SP:1;           /* Supervisor Protect */
14807         vuint32_t PACR12_WP:1;           /* Write Protect */
14808         vuint32_t PACR12_TP:1;           /* Trusted Protect */
14809         vuint32_t PACR13_BW:1;           /* Buffer Writes */
14810         vuint32_t PACR13_SP:1;           /* Supervisor Protect */
14811         vuint32_t PACR13_WP:1;           /* Write Protect */
14812         vuint32_t PACR13_TP:1;           /* Trusted Protect */
14813         vuint32_t PACR14_BW:1;           /* Buffer Writes */
14814         vuint32_t PACR14_SP:1;           /* Supervisor Protect */
14815         vuint32_t PACR14_WP:1;           /* Write Protect */
14816         vuint32_t PACR14_TP:1;           /* Trusted Protect */
14817         vuint32_t PACR15_BW:1;           /* Buffer Writes */
14818         vuint32_t PACR15_SP:1;           /* Supervisor Protect */
14819         vuint32_t PACR15_WP:1;           /* Write Protect */
14820         vuint32_t PACR15_TP:1;           /* Trusted Protect */
14821       } B;
14822     } PBRIDGE_PACR8_15_32B_tag;
14823   
14824     typedef union {                      /* PACR16_23 - Peripheral Access Control Registers */
14825       vuint32_t R;
14826       struct {
14827         vuint32_t PACR16_BW:1;           /* Buffer Writes */
14828         vuint32_t PACR16_SP:1;           /* Supervisor Protect */
14829         vuint32_t PACR16_WP:1;           /* Write Protect */
14830         vuint32_t PACR16_TP:1;           /* Trusted Protect */
14831         vuint32_t PACR17_BW:1;           /* Buffer Writes */
14832         vuint32_t PACR17_SP:1;           /* Supervisor Protect */
14833         vuint32_t PACR17_WP:1;           /* Write Protect */
14834         vuint32_t PACR17_TP:1;           /* Trusted Protect */
14835         vuint32_t PACR18_BW:1;           /* Buffer Writes */
14836         vuint32_t PACR18_SP:1;           /* Supervisor Protect */
14837         vuint32_t PACR18_WP:1;           /* Write Protect */
14838         vuint32_t PACR18_TP:1;           /* Trusted Protect */
14839         vuint32_t PACR19_BW:1;           /* Buffer Writes */
14840         vuint32_t PACR19_SP:1;           /* Supervisor Protect */
14841         vuint32_t PACR19_WP:1;           /* Write Protect */
14842         vuint32_t PACR19_TP:1;           /* Trusted Protect */
14843         vuint32_t PACR20_BW:1;           /* Buffer Writes */
14844         vuint32_t PACR20_SP:1;           /* Supervisor Protect */
14845         vuint32_t PACR20_WP:1;           /* Write Protect */
14846         vuint32_t PACR20_TP:1;           /* Trusted Protect */
14847         vuint32_t PACR21_BW:1;           /* Buffer Writes */
14848         vuint32_t PACR21_SP:1;           /* Supervisor Protect */
14849         vuint32_t PACR21_WP:1;           /* Write Protect */
14850         vuint32_t PACR21_TP:1;           /* Trusted Protect */
14851         vuint32_t PACR22_BW:1;           /* Buffer Writes */
14852         vuint32_t PACR22_SP:1;           /* Supervisor Protect */
14853         vuint32_t PACR22_WP:1;           /* Write Protect */
14854         vuint32_t PACR22_TP:1;           /* Trusted Protect */
14855         vuint32_t PACR23_BW:1;           /* Buffer Writes */
14856         vuint32_t PACR23_SP:1;           /* Supervisor Protect */
14857         vuint32_t PACR23_WP:1;           /* Write Protect */
14858         vuint32_t PACR23_TP:1;           /* Trusted Protect */
14859       } B;
14860     } PBRIDGE_PACR16_23_32B_tag;
14861   
14862     typedef union {                      /* PACR24_31 - Peripheral Access Control Registers */
14863       vuint32_t R;
14864       struct {
14865         vuint32_t PACR24_BW:1;           /* Buffer Writes */
14866         vuint32_t PACR24_SP:1;           /* Supervisor Protect */
14867         vuint32_t PACR24_WP:1;           /* Write Protect */
14868         vuint32_t PACR24_TP:1;           /* Trusted Protect */
14869         vuint32_t PACR25_BW:1;           /* Buffer Writes */
14870         vuint32_t PACR25_SP:1;           /* Supervisor Protect */
14871         vuint32_t PACR25_WP:1;           /* Write Protect */
14872         vuint32_t PACR25_TP:1;           /* Trusted Protect */
14873         vuint32_t PACR26_BW:1;           /* Buffer Writes */
14874         vuint32_t PACR26_SP:1;           /* Supervisor Protect */
14875         vuint32_t PACR26_WP:1;           /* Write Protect */
14876         vuint32_t PACR26_TP:1;           /* Trusted Protect */
14877         vuint32_t PACR27_BW:1;           /* Buffer Writes */
14878         vuint32_t PACR27_SP:1;           /* Supervisor Protect */
14879         vuint32_t PACR27_WP:1;           /* Write Protect */
14880         vuint32_t PACR27_TP:1;           /* Trusted Protect */
14881         vuint32_t PACR28_BW:1;           /* Buffer Writes */
14882         vuint32_t PACR28_SP:1;           /* Supervisor Protect */
14883         vuint32_t PACR28_WP:1;           /* Write Protect */
14884         vuint32_t PACR28_TP:1;           /* Trusted Protect */
14885         vuint32_t PACR29_BW:1;           /* Buffer Writes */
14886         vuint32_t PACR29_SP:1;           /* Supervisor Protect */
14887         vuint32_t PACR29_WP:1;           /* Write Protect */
14888         vuint32_t PACR29_TP:1;           /* Trusted Protect */
14889         vuint32_t PACR30_BW:1;           /* Buffer Writes */
14890         vuint32_t PACR30_SP:1;           /* Supervisor Protect */
14891         vuint32_t PACR30_WP:1;           /* Write Protect */
14892         vuint32_t PACR30_TP:1;           /* Trusted Protect */
14893         vuint32_t PACR31_BW:1;           /* Buffer Writes */
14894         vuint32_t PACR31_SP:1;           /* Supervisor Protect */
14895         vuint32_t PACR31_WP:1;           /* Write Protect */
14896         vuint32_t PACR31_TP:1;           /* Trusted Protect */
14897       } B;
14898     } PBRIDGE_PACR24_31_32B_tag;
14899   
14900     typedef union {                      /* OPACR0_7 - Off-Platform Peripheral Access Control Registers */
14901       vuint32_t R;
14902       struct {
14903         vuint32_t OPACR0_BW:1;           /* Buffer Writes */
14904         vuint32_t OPACR0_SP:1;           /* Supervisor Protect */
14905         vuint32_t OPACR0_WP:1;           /* Write Protect */
14906         vuint32_t OPACR0_TP:1;           /* Trusted Protect */
14907         vuint32_t OPACR1_BW:1;           /* Buffer Writes */
14908         vuint32_t OPACR1_SP:1;           /* Supervisor Protect */
14909         vuint32_t OPACR1_WP:1;           /* Write Protect */
14910         vuint32_t OPACR1_TP:1;           /* Trusted Protect */
14911         vuint32_t OPACR2_BW:1;           /* Buffer Writes */
14912         vuint32_t OPACR2_SP:1;           /* Supervisor Protect */
14913         vuint32_t OPACR2_WP:1;           /* Write Protect */
14914         vuint32_t OPACR2_TP:1;           /* Trusted Protect */
14915         vuint32_t OPACR3_BW:1;           /* Buffer Writes */
14916         vuint32_t OPACR3_SP:1;           /* Supervisor Protect */
14917         vuint32_t OPACR3_WP:1;           /* Write Protect */
14918         vuint32_t OPACR3_TP:1;           /* Trusted Protect */
14919         vuint32_t OPACR4_BW:1;           /* Buffer Writes */
14920         vuint32_t OPACR4_SP:1;           /* Supervisor Protect */
14921         vuint32_t OPACR4_WP:1;           /* Write Protect */
14922         vuint32_t OPACR4_TP:1;           /* Trusted Protect */
14923         vuint32_t OPACR5_BW:1;           /* Buffer Writes */
14924         vuint32_t OPACR5_SP:1;           /* Supervisor Protect */
14925         vuint32_t OPACR5_WP:1;           /* Write Protect */
14926         vuint32_t OPACR5_TP:1;           /* Trusted Protect */
14927         vuint32_t OPACR6_BW:1;           /* Buffer Writes */
14928         vuint32_t OPACR6_SP:1;           /* Supervisor Protect */
14929         vuint32_t OPACR6_WP:1;           /* Write Protect */
14930         vuint32_t OPACR6_TP:1;           /* Trusted Protect */
14931         vuint32_t OPACR7_BW:1;           /* Buffer Writes */
14932         vuint32_t OPACR7_SP:1;           /* Supervisor Protect */
14933         vuint32_t OPACR7_WP:1;           /* Write Protect */
14934         vuint32_t OPACR7_TP:1;           /* Trusted Protect */
14935       } B;
14936     } PBRIDGE_OPACR0_7_32B_tag;
14937   
14938     typedef union {                      /* OPACR8_15 - Off-Platform Peripheral Access Control Registers */
14939       vuint32_t R;
14940       struct {
14941         vuint32_t OPACR8_BW:1;           /* Buffer Writes */
14942         vuint32_t OPACR8_SP:1;           /* Supervisor Protect */
14943         vuint32_t OPACR8_WP:1;           /* Write Protect */
14944         vuint32_t OPACR8_TP:1;           /* Trusted Protect */
14945         vuint32_t OPACR9_BW:1;           /* Buffer Writes */
14946         vuint32_t OPACR9_SP:1;           /* Supervisor Protect */
14947         vuint32_t OPACR9_WP:1;           /* Write Protect */
14948         vuint32_t OPACR9_TP:1;           /* Trusted Protect */
14949         vuint32_t OPACR10_BW:1;          /* Buffer Writes */
14950         vuint32_t OPACR10_SP:1;          /* Supervisor Protect */
14951         vuint32_t OPACR10_WP:1;          /* Write Protect */
14952         vuint32_t OPACR10_TP:1;          /* Trusted Protect */
14953         vuint32_t OPACR11_BW:1;          /* Buffer Writes */
14954         vuint32_t OPACR11_SP:1;          /* Supervisor Protect */
14955         vuint32_t OPACR11_WP:1;          /* Write Protect */
14956         vuint32_t OPACR11_TP:1;          /* Trusted Protect */
14957         vuint32_t OPACR12_BW:1;          /* Buffer Writes */
14958         vuint32_t OPACR12_SP:1;          /* Supervisor Protect */
14959         vuint32_t OPACR12_WP:1;          /* Write Protect */
14960         vuint32_t OPACR12_TP:1;          /* Trusted Protect */
14961         vuint32_t OPACR13_BW:1;          /* Buffer Writes */
14962         vuint32_t OPACR13_SP:1;          /* Supervisor Protect */
14963         vuint32_t OPACR13_WP:1;          /* Write Protect */
14964         vuint32_t OPACR13_TP:1;          /* Trusted Protect */
14965         vuint32_t OPACR14_BW:1;          /* Buffer Writes */
14966         vuint32_t OPACR14_SP:1;          /* Supervisor Protect */
14967         vuint32_t OPACR14_WP:1;          /* Write Protect */
14968         vuint32_t OPACR14_TP:1;          /* Trusted Protect */
14969         vuint32_t OPACR15_BW:1;          /* Buffer Writes */
14970         vuint32_t OPACR15_SP:1;          /* Supervisor Protect */
14971         vuint32_t OPACR15_WP:1;          /* Write Protect */
14972         vuint32_t OPACR15_TP:1;          /* Trusted Protect */
14973       } B;
14974     } PBRIDGE_OPACR8_15_32B_tag;
14975   
14976     typedef union {                      /* OPACR16_23 - Off-Platform Peripheral Access Control Registers */
14977       vuint32_t R;
14978       struct {
14979         vuint32_t OPACR16_BW:1;          /* Buffer Writes */
14980         vuint32_t OPACR16_SP:1;          /* Supervisor Protect */
14981         vuint32_t OPACR16_WP:1;          /* Write Protect */
14982         vuint32_t OPACR16_TP:1;          /* Trusted Protect */
14983         vuint32_t OPACR17_BW:1;          /* Buffer Writes */
14984         vuint32_t OPACR17_SP:1;          /* Supervisor Protect */
14985         vuint32_t OPACR17_WP:1;          /* Write Protect */
14986         vuint32_t OPACR17_TP:1;          /* Trusted Protect */
14987         vuint32_t OPACR18_BW:1;          /* Buffer Writes */
14988         vuint32_t OPACR18_SP:1;          /* Supervisor Protect */
14989         vuint32_t OPACR18_WP:1;          /* Write Protect */
14990         vuint32_t OPACR18_TP:1;          /* Trusted Protect */
14991         vuint32_t OPACR19_BW:1;          /* Buffer Writes */
14992         vuint32_t OPACR19_SP:1;          /* Supervisor Protect */
14993         vuint32_t OPACR19_WP:1;          /* Write Protect */
14994         vuint32_t OPACR19_TP:1;          /* Trusted Protect */
14995         vuint32_t OPACR20_BW:1;          /* Buffer Writes */
14996         vuint32_t OPACR20_SP:1;          /* Supervisor Protect */
14997         vuint32_t OPACR20_WP:1;          /* Write Protect */
14998         vuint32_t OPACR20_TP:1;          /* Trusted Protect */
14999         vuint32_t OPACR21_BW:1;          /* Buffer Writes */
15000         vuint32_t OPACR21_SP:1;          /* Supervisor Protect */
15001         vuint32_t OPACR21_WP:1;          /* Write Protect */
15002         vuint32_t OPACR21_TP:1;          /* Trusted Protect */
15003         vuint32_t OPACR22_BW:1;          /* Buffer Writes */
15004         vuint32_t OPACR22_SP:1;          /* Supervisor Protect */
15005         vuint32_t OPACR22_WP:1;          /* Write Protect */
15006         vuint32_t OPACR22_TP:1;          /* Trusted Protect */
15007         vuint32_t OPACR23_BW:1;          /* Buffer Writes */
15008         vuint32_t OPACR23_SP:1;          /* Supervisor Protect */
15009         vuint32_t OPACR23_WP:1;          /* Write Protect */
15010         vuint32_t OPACR23_TP:1;          /* Trusted Protect */
15011       } B;
15012     } PBRIDGE_OPACR16_23_32B_tag;
15013   
15014     typedef union {                      /* OPACR24_31 - Off-Platform Peripheral Access Control Registers */
15015       vuint32_t R;
15016       struct {
15017         vuint32_t OPACR24_BW:1;          /* Buffer Writes */
15018         vuint32_t OPACR24_SP:1;          /* Supervisor Protect */
15019         vuint32_t OPACR24_WP:1;          /* Write Protect */
15020         vuint32_t OPACR24_TP:1;          /* Trusted Protect */
15021         vuint32_t OPACR25_BW:1;          /* Buffer Writes */
15022         vuint32_t OPACR25_SP:1;          /* Supervisor Protect */
15023         vuint32_t OPACR25_WP:1;          /* Write Protect */
15024         vuint32_t OPACR25_TP:1;          /* Trusted Protect */
15025         vuint32_t OPACR26_BW:1;          /* Buffer Writes */
15026         vuint32_t OPACR26_SP:1;          /* Supervisor Protect */
15027         vuint32_t OPACR26_WP:1;          /* Write Protect */
15028         vuint32_t OPACR26_TP:1;          /* Trusted Protect */
15029         vuint32_t OPACR27_BW:1;          /* Buffer Writes */
15030         vuint32_t OPACR27_SP:1;          /* Supervisor Protect */
15031         vuint32_t OPACR27_WP:1;          /* Write Protect */
15032         vuint32_t OPACR27_TP:1;          /* Trusted Protect */
15033         vuint32_t OPACR28_BW:1;          /* Buffer Writes */
15034         vuint32_t OPACR28_SP:1;          /* Supervisor Protect */
15035         vuint32_t OPACR28_WP:1;          /* Write Protect */
15036         vuint32_t OPACR28_TP:1;          /* Trusted Protect */
15037         vuint32_t OPACR29_BW:1;          /* Buffer Writes */
15038         vuint32_t OPACR29_SP:1;          /* Supervisor Protect */
15039         vuint32_t OPACR29_WP:1;          /* Write Protect */
15040         vuint32_t OPACR29_TP:1;          /* Trusted Protect */
15041         vuint32_t OPACR30_BW:1;          /* Buffer Writes */
15042         vuint32_t OPACR30_SP:1;          /* Supervisor Protect */
15043         vuint32_t OPACR30_WP:1;          /* Write Protect */
15044         vuint32_t OPACR30_TP:1;          /* Trusted Protect */
15045         vuint32_t OPACR31_BW:1;          /* Buffer Writes */
15046         vuint32_t OPACR31_SP:1;          /* Supervisor Protect */
15047         vuint32_t OPACR31_WP:1;          /* Write Protect */
15048         vuint32_t OPACR31_TP:1;          /* Trusted Protect */
15049       } B;
15050     } PBRIDGE_OPACR24_31_32B_tag;
15051   
15052     typedef union {                      /* OPACR32_39 - Off-Platform Peripheral Access Control Registers */
15053       vuint32_t R;
15054       struct {
15055         vuint32_t OPACR32_BW:1;          /* Buffer Writes */
15056         vuint32_t OPACR32_SP:1;          /* Supervisor Protect */
15057         vuint32_t OPACR32_WP:1;          /* Write Protect */
15058         vuint32_t OPACR32_TP:1;          /* Trusted Protect */
15059         vuint32_t OPACR33_BW:1;          /* Buffer Writes */
15060         vuint32_t OPACR33_SP:1;          /* Supervisor Protect */
15061         vuint32_t OPACR33_WP:1;          /* Write Protect */
15062         vuint32_t OPACR33_TP:1;          /* Trusted Protect */
15063         vuint32_t OPACR34_BW:1;          /* Buffer Writes */
15064         vuint32_t OPACR34_SP:1;          /* Supervisor Protect */
15065         vuint32_t OPACR34_WP:1;          /* Write Protect */
15066         vuint32_t OPACR34_TP:1;          /* Trusted Protect */
15067         vuint32_t OPACR35_BW:1;          /* Buffer Writes */
15068         vuint32_t OPACR35_SP:1;          /* Supervisor Protect */
15069         vuint32_t OPACR35_WP:1;          /* Write Protect */
15070         vuint32_t OPACR35_TP:1;          /* Trusted Protect */
15071         vuint32_t OPACR36_BW:1;          /* Buffer Writes */
15072         vuint32_t OPACR36_SP:1;          /* Supervisor Protect */
15073         vuint32_t OPACR36_WP:1;          /* Write Protect */
15074         vuint32_t OPACR36_TP:1;          /* Trusted Protect */
15075         vuint32_t OPACR37_BW:1;          /* Buffer Writes */
15076         vuint32_t OPACR37_SP:1;          /* Supervisor Protect */
15077         vuint32_t OPACR37_WP:1;          /* Write Protect */
15078         vuint32_t OPACR37_TP:1;          /* Trusted Protect */
15079         vuint32_t OPACR38_BW:1;          /* Buffer Writes */
15080         vuint32_t OPACR38_SP:1;          /* Supervisor Protect */
15081         vuint32_t OPACR38_WP:1;          /* Write Protect */
15082         vuint32_t OPACR38_TP:1;          /* Trusted Protect */
15083         vuint32_t OPACR39_BW:1;          /* Buffer Writes */
15084         vuint32_t OPACR39_SP:1;          /* Supervisor Protect */
15085         vuint32_t OPACR39_WP:1;          /* Write Protect */
15086         vuint32_t OPACR39_TP:1;          /* Trusted Protect */
15087       } B;
15088     } PBRIDGE_OPACR32_39_32B_tag;
15089   
15090     typedef union {                      /* OPACR40_47 - Off-Platform Peripheral Access Control Registers */
15091       vuint32_t R;
15092       struct {
15093         vuint32_t OPACR40_BW:1;          /* Buffer Writes */
15094         vuint32_t OPACR40_SP:1;          /* Supervisor Protect */
15095         vuint32_t OPACR40_WP:1;          /* Write Protect */
15096         vuint32_t OPACR40_TP:1;          /* Trusted Protect */
15097         vuint32_t OPACR41_BW:1;          /* Buffer Writes */
15098         vuint32_t OPACR41_SP:1;          /* Supervisor Protect */
15099         vuint32_t OPACR41_WP:1;          /* Write Protect */
15100         vuint32_t OPACR41_TP:1;          /* Trusted Protect */
15101         vuint32_t OPACR42_BW:1;          /* Buffer Writes */
15102         vuint32_t OPACR42_SP:1;          /* Supervisor Protect */
15103         vuint32_t OPACR42_WP:1;          /* Write Protect */
15104         vuint32_t OPACR42_TP:1;          /* Trusted Protect */
15105         vuint32_t OPACR43_BW:1;          /* Buffer Writes */
15106         vuint32_t OPACR43_SP:1;          /* Supervisor Protect */
15107         vuint32_t OPACR43_WP:1;          /* Write Protect */
15108         vuint32_t OPACR43_TP:1;          /* Trusted Protect */
15109         vuint32_t OPACR44_BW:1;          /* Buffer Writes */
15110         vuint32_t OPACR44_SP:1;          /* Supervisor Protect */
15111         vuint32_t OPACR44_WP:1;          /* Write Protect */
15112         vuint32_t OPACR44_TP:1;          /* Trusted Protect */
15113         vuint32_t OPACR45_BW:1;          /* Buffer Writes */
15114         vuint32_t OPACR45_SP:1;          /* Supervisor Protect */
15115         vuint32_t OPACR45_WP:1;          /* Write Protect */
15116         vuint32_t OPACR45_TP:1;          /* Trusted Protect */
15117         vuint32_t OPACR46_BW:1;          /* Buffer Writes */
15118         vuint32_t OPACR46_SP:1;          /* Supervisor Protect */
15119         vuint32_t OPACR46_WP:1;          /* Write Protect */
15120         vuint32_t OPACR46_TP:1;          /* Trusted Protect */
15121         vuint32_t OPACR47_BW:1;          /* Buffer Writes */
15122         vuint32_t OPACR47_SP:1;          /* Supervisor Protect */
15123         vuint32_t OPACR47_WP:1;          /* Write Protect */
15124         vuint32_t OPACR47_TP:1;          /* Trusted Protect */
15125       } B;
15126     } PBRIDGE_OPACR40_47_32B_tag;
15127   
15128     typedef union {                      /* OPACR48_55 - Off-Platform Peripheral Access Control Registers */
15129       vuint32_t R;
15130       struct {
15131         vuint32_t OPACR48_BW:1;          /* Buffer Writes */
15132         vuint32_t OPACR48_SP:1;          /* Supervisor Protect */
15133         vuint32_t OPACR48_WP:1;          /* Write Protect */
15134         vuint32_t OPACR48_TP:1;          /* Trusted Protect */
15135         vuint32_t OPACR49_BW:1;          /* Buffer Writes */
15136         vuint32_t OPACR49_SP:1;          /* Supervisor Protect */
15137         vuint32_t OPACR49_WP:1;          /* Write Protect */
15138         vuint32_t OPACR49_TP:1;          /* Trusted Protect */
15139         vuint32_t OPACR50_BW:1;          /* Buffer Writes */
15140         vuint32_t OPACR50_SP:1;          /* Supervisor Protect */
15141         vuint32_t OPACR50_WP:1;          /* Write Protect */
15142         vuint32_t OPACR50_TP:1;          /* Trusted Protect */
15143         vuint32_t OPACR51_BW:1;          /* Buffer Writes */
15144         vuint32_t OPACR51_SP:1;          /* Supervisor Protect */
15145         vuint32_t OPACR51_WP:1;          /* Write Protect */
15146         vuint32_t OPACR51_TP:1;          /* Trusted Protect */
15147         vuint32_t OPACR52_BW:1;          /* Buffer Writes */
15148         vuint32_t OPACR52_SP:1;          /* Supervisor Protect */
15149         vuint32_t OPACR52_WP:1;          /* Write Protect */
15150         vuint32_t OPACR52_TP:1;          /* Trusted Protect */
15151         vuint32_t OPACR53_BW:1;          /* Buffer Writes */
15152         vuint32_t OPACR53_SP:1;          /* Supervisor Protect */
15153         vuint32_t OPACR53_WP:1;          /* Write Protect */
15154         vuint32_t OPACR53_TP:1;          /* Trusted Protect */
15155         vuint32_t OPACR54_BW:1;          /* Buffer Writes */
15156         vuint32_t OPACR54_SP:1;          /* Supervisor Protect */
15157         vuint32_t OPACR54_WP:1;          /* Write Protect */
15158         vuint32_t OPACR54_TP:1;          /* Trusted Protect */
15159         vuint32_t OPACR55_BW:1;          /* Buffer Writes */
15160         vuint32_t OPACR55_SP:1;          /* Supervisor Protect */
15161         vuint32_t OPACR55_WP:1;          /* Write Protect */
15162         vuint32_t OPACR55_TP:1;          /* Trusted Protect */
15163       } B;
15164     } PBRIDGE_OPACR48_55_32B_tag;
15165   
15166     typedef union {                      /* OPACR56_63 - Off-Platform Peripheral Access Control Registers */
15167       vuint32_t R;
15168       struct {
15169         vuint32_t OPACR56_BW:1;          /* Buffer Writes */
15170         vuint32_t OPACR56_SP:1;          /* Supervisor Protect */
15171         vuint32_t OPACR56_WP:1;          /* Write Protect */
15172         vuint32_t OPACR56_TP:1;          /* Trusted Protect */
15173         vuint32_t OPACR57_BW:1;          /* Buffer Writes */
15174         vuint32_t OPACR57_SP:1;          /* Supervisor Protect */
15175         vuint32_t OPACR57_WP:1;          /* Write Protect */
15176         vuint32_t OPACR57_TP:1;          /* Trusted Protect */
15177         vuint32_t OPACR58_BW:1;          /* Buffer Writes */
15178         vuint32_t OPACR58_SP:1;          /* Supervisor Protect */
15179         vuint32_t OPACR58_WP:1;          /* Write Protect */
15180         vuint32_t OPACR58_TP:1;          /* Trusted Protect */
15181         vuint32_t OPACR59_BW:1;          /* Buffer Writes */
15182         vuint32_t OPACR59_SP:1;          /* Supervisor Protect */
15183         vuint32_t OPACR59_WP:1;          /* Write Protect */
15184         vuint32_t OPACR59_TP:1;          /* Trusted Protect */
15185         vuint32_t OPACR60_BW:1;          /* Buffer Writes */
15186         vuint32_t OPACR60_SP:1;          /* Supervisor Protect */
15187         vuint32_t OPACR60_WP:1;          /* Write Protect */
15188         vuint32_t OPACR60_TP:1;          /* Trusted Protect */
15189         vuint32_t OPACR61_BW:1;          /* Buffer Writes */
15190         vuint32_t OPACR61_SP:1;          /* Supervisor Protect */
15191         vuint32_t OPACR61_WP:1;          /* Write Protect */
15192         vuint32_t OPACR61_TP:1;          /* Trusted Protect */
15193         vuint32_t OPACR62_BW:1;          /* Buffer Writes */
15194         vuint32_t OPACR62_SP:1;          /* Supervisor Protect */
15195         vuint32_t OPACR62_WP:1;          /* Write Protect */
15196         vuint32_t OPACR62_TP:1;          /* Trusted Protect */
15197         vuint32_t OPACR63_BW:1;          /* Buffer Writes */
15198         vuint32_t OPACR63_SP:1;          /* Supervisor Protect */
15199         vuint32_t OPACR63_WP:1;          /* Write Protect */
15200         vuint32_t OPACR63_TP:1;          /* Trusted Protect */
15201       } B;
15202     } PBRIDGE_OPACR56_63_32B_tag;
15203   
15204     typedef union {                      /* OPACR64_71 - Off-Platform Peripheral Access Control Registers */
15205       vuint32_t R;
15206       struct {
15207         vuint32_t OPACR64_BW:1;          /* Buffer Writes */
15208         vuint32_t OPACR64_SP:1;          /* Supervisor Protect */
15209         vuint32_t OPACR64_WP:1;          /* Write Protect */
15210         vuint32_t OPACR64_TP:1;          /* Trusted Protect */
15211         vuint32_t OPACR65_BW:1;          /* Buffer Writes */
15212         vuint32_t OPACR65_SP:1;          /* Supervisor Protect */
15213         vuint32_t OPACR65_WP:1;          /* Write Protect */
15214         vuint32_t OPACR65_TP:1;          /* Trusted Protect */
15215         vuint32_t OPACR66_BW:1;          /* Buffer Writes */
15216         vuint32_t OPACR66_SP:1;          /* Supervisor Protect */
15217         vuint32_t OPACR66_WP:1;          /* Write Protect */
15218         vuint32_t OPACR66_TP:1;          /* Trusted Protect */
15219         vuint32_t OPACR67_BW:1;          /* Buffer Writes */
15220         vuint32_t OPACR67_SP:1;          /* Supervisor Protect */
15221         vuint32_t OPACR67_WP:1;          /* Write Protect */
15222         vuint32_t OPACR67_TP:1;          /* Trusted Protect */
15223         vuint32_t OPACR68_BW:1;          /* Buffer Writes */
15224         vuint32_t OPACR68_SP:1;          /* Supervisor Protect */
15225         vuint32_t OPACR68_WP:1;          /* Write Protect */
15226         vuint32_t OPACR68_TP:1;          /* Trusted Protect */
15227         vuint32_t OPACR69_BW:1;          /* Buffer Writes */
15228         vuint32_t OPACR69_SP:1;          /* Supervisor Protect */
15229         vuint32_t OPACR69_WP:1;          /* Write Protect */
15230         vuint32_t OPACR69_TP:1;          /* Trusted Protect */
15231         vuint32_t OPACR70_BW:1;          /* Buffer Writes */
15232         vuint32_t OPACR70_SP:1;          /* Supervisor Protect */
15233         vuint32_t OPACR70_WP:1;          /* Write Protect */
15234         vuint32_t OPACR70_TP:1;          /* Trusted Protect */
15235         vuint32_t OPACR71_BW:1;          /* Buffer Writes */
15236         vuint32_t OPACR71_SP:1;          /* Supervisor Protect */
15237         vuint32_t OPACR71_WP:1;          /* Write Protect */
15238         vuint32_t OPACR71_TP:1;          /* Trusted Protect */
15239       } B;
15240     } PBRIDGE_OPACR64_71_32B_tag;
15241   
15242     typedef union {                      /* OPACR72_79 - Off-Platform Peripheral Access Control Registers */
15243       vuint32_t R;
15244       struct {
15245         vuint32_t OPACR72_BW:1;          /* Buffer Writes */
15246         vuint32_t OPACR72_SP:1;          /* Supervisor Protect */
15247         vuint32_t OPACR72_WP:1;          /* Write Protect */
15248         vuint32_t OPACR72_TP:1;          /* Trusted Protect */
15249         vuint32_t OPACR73_BW:1;          /* Buffer Writes */
15250         vuint32_t OPACR73_SP:1;          /* Supervisor Protect */
15251         vuint32_t OPACR73_WP:1;          /* Write Protect */
15252         vuint32_t OPACR73_TP:1;          /* Trusted Protect */
15253         vuint32_t OPACR74_BW:1;          /* Buffer Writes */
15254         vuint32_t OPACR74_SP:1;          /* Supervisor Protect */
15255         vuint32_t OPACR74_WP:1;          /* Write Protect */
15256         vuint32_t OPACR74_TP:1;          /* Trusted Protect */
15257         vuint32_t OPACR75_BW:1;          /* Buffer Writes */
15258         vuint32_t OPACR75_SP:1;          /* Supervisor Protect */
15259         vuint32_t OPACR75_WP:1;          /* Write Protect */
15260         vuint32_t OPACR75_TP:1;          /* Trusted Protect */
15261         vuint32_t OPACR76_BW:1;          /* Buffer Writes */
15262         vuint32_t OPACR76_SP:1;          /* Supervisor Protect */
15263         vuint32_t OPACR76_WP:1;          /* Write Protect */
15264         vuint32_t OPACR76_TP:1;          /* Trusted Protect */
15265         vuint32_t OPACR77_BW:1;          /* Buffer Writes */
15266         vuint32_t OPACR77_SP:1;          /* Supervisor Protect */
15267         vuint32_t OPACR77_WP:1;          /* Write Protect */
15268         vuint32_t OPACR77_TP:1;          /* Trusted Protect */
15269         vuint32_t OPACR78_BW:1;          /* Buffer Writes */
15270         vuint32_t OPACR78_SP:1;          /* Supervisor Protect */
15271         vuint32_t OPACR78_WP:1;          /* Write Protect */
15272         vuint32_t OPACR78_TP:1;          /* Trusted Protect */
15273         vuint32_t OPACR79_BW:1;          /* Buffer Writes */
15274         vuint32_t OPACR79_SP:1;          /* Supervisor Protect */
15275         vuint32_t OPACR79_WP:1;          /* Write Protect */
15276         vuint32_t OPACR79_TP:1;          /* Trusted Protect */
15277       } B;
15278     } PBRIDGE_OPACR72_79_32B_tag;
15279   
15280     typedef union {                      /* OPACR80_87 - Off-Platform Peripheral Access Control Registers */
15281       vuint32_t R;
15282       struct {
15283         vuint32_t OPACR80_BW:1;          /* Buffer Writes */
15284         vuint32_t OPACR80_SP:1;          /* Supervisor Protect */
15285         vuint32_t OPACR80_WP:1;          /* Write Protect */
15286         vuint32_t OPACR80_TP:1;          /* Trusted Protect */
15287         vuint32_t OPACR81_BW:1;          /* Buffer Writes */
15288         vuint32_t OPACR81_SP:1;          /* Supervisor Protect */
15289         vuint32_t OPACR81_WP:1;          /* Write Protect */
15290         vuint32_t OPACR81_TP:1;          /* Trusted Protect */
15291         vuint32_t OPACR82_BW:1;          /* Buffer Writes */
15292         vuint32_t OPACR82_SP:1;          /* Supervisor Protect */
15293         vuint32_t OPACR82_WP:1;          /* Write Protect */
15294         vuint32_t OPACR82_TP:1;          /* Trusted Protect */
15295         vuint32_t OPACR83_BW:1;          /* Buffer Writes */
15296         vuint32_t OPACR83_SP:1;          /* Supervisor Protect */
15297         vuint32_t OPACR83_WP:1;          /* Write Protect */
15298         vuint32_t OPACR83_TP:1;          /* Trusted Protect */
15299         vuint32_t OPACR84_BW:1;          /* Buffer Writes */
15300         vuint32_t OPACR84_SP:1;          /* Supervisor Protect */
15301         vuint32_t OPACR84_WP:1;          /* Write Protect */
15302         vuint32_t OPACR84_TP:1;          /* Trusted Protect */
15303         vuint32_t OPACR85_BW:1;          /* Buffer Writes */
15304         vuint32_t OPACR85_SP:1;          /* Supervisor Protect */
15305         vuint32_t OPACR85_WP:1;          /* Write Protect */
15306         vuint32_t OPACR85_TP:1;          /* Trusted Protect */
15307         vuint32_t OPACR86_BW:1;          /* Buffer Writes */
15308         vuint32_t OPACR86_SP:1;          /* Supervisor Protect */
15309         vuint32_t OPACR86_WP:1;          /* Write Protect */
15310         vuint32_t OPACR86_TP:1;          /* Trusted Protect */
15311         vuint32_t OPACR87_BW:1;          /* Buffer Writes */
15312         vuint32_t OPACR87_SP:1;          /* Supervisor Protect */
15313         vuint32_t OPACR87_WP:1;          /* Write Protect */
15314         vuint32_t OPACR87_TP:1;          /* Trusted Protect */
15315       } B;
15316     } PBRIDGE_OPACR80_87_32B_tag;
15317   
15318     typedef union {                      /* OPACR88_95 - Off-Platform Peripheral Access Control Registers */
15319       vuint32_t R;
15320       struct {
15321         vuint32_t OPACR88_BW:1;          /* Buffer Writes */
15322         vuint32_t OPACR88_SP:1;          /* Supervisor Protect */
15323         vuint32_t OPACR88_WP:1;          /* Write Protect */
15324         vuint32_t OPACR88_TP:1;          /* Trusted Protect */
15325         vuint32_t OPACR89_BW:1;          /* Buffer Writes */
15326         vuint32_t OPACR89_SP:1;          /* Supervisor Protect */
15327         vuint32_t OPACR89_WP:1;          /* Write Protect */
15328         vuint32_t OPACR89_TP:1;          /* Trusted Protect */
15329         vuint32_t OPACR90_BW:1;          /* Buffer Writes */
15330         vuint32_t OPACR90_SP:1;          /* Supervisor Protect */
15331         vuint32_t OPACR90_WP:1;          /* Write Protect */
15332         vuint32_t OPACR90_TP:1;          /* Trusted Protect */
15333         vuint32_t OPACR91_BW:1;          /* Buffer Writes */
15334         vuint32_t OPACR91_SP:1;          /* Supervisor Protect */
15335         vuint32_t OPACR91_WP:1;          /* Write Protect */
15336         vuint32_t OPACR91_TP:1;          /* Trusted Protect */
15337         vuint32_t OPACR92_BW:1;          /* Buffer Writes */
15338         vuint32_t OPACR92_SP:1;          /* Supervisor Protect */
15339         vuint32_t OPACR92_WP:1;          /* Write Protect */
15340         vuint32_t OPACR92_TP:1;          /* Trusted Protect */
15341         vuint32_t OPACR93_BW:1;          /* Buffer Writes */
15342         vuint32_t OPACR93_SP:1;          /* Supervisor Protect */
15343         vuint32_t OPACR93_WP:1;          /* Write Protect */
15344         vuint32_t OPACR93_TP:1;          /* Trusted Protect */
15345         vuint32_t OPACR94_BW:1;          /* Buffer Writes */
15346         vuint32_t OPACR94_SP:1;          /* Supervisor Protect */
15347         vuint32_t OPACR94_WP:1;          /* Write Protect */
15348         vuint32_t OPACR94_TP:1;          /* Trusted Protect */
15349         vuint32_t OPACR95_BW:1;          /* Buffer Writes */
15350         vuint32_t OPACR95_SP:1;          /* Supervisor Protect */
15351         vuint32_t OPACR95_WP:1;          /* Write Protect */
15352         vuint32_t OPACR95_TP:1;          /* Trusted Protect */
15353       } B;
15354     } PBRIDGE_OPACR88_95_32B_tag;
15355   
15356     typedef struct PBRIDGE_struct_tag {
15357       /* MPROT - Master Privilege Registers */
15358       PBRIDGE_MPROT0_7_32B_tag MPROT0_7; /* offset: 0x0000 size: 32 bit */
15359   
15360       /* MPROT - Master Privilege Registers */
15361       PBRIDGE_MPROT8_15_32B_tag MPROT8_15;/* offset: 0x0004 size: 32 bit */
15362       int8_t PBRIDGE_reserved_0008[24];
15363   
15364       /* PACR0_7 - Peripheral Access Control Registers */
15365       PBRIDGE_PACR0_7_32B_tag PACR0_7;   /* offset: 0x0020 size: 32 bit */
15366   
15367       /* PACR8_15 - Peripheral Access Control Registers */
15368       PBRIDGE_PACR8_15_32B_tag PACR8_15; /* offset: 0x0024 size: 32 bit */
15369   
15370       /* PACR16_23 - Peripheral Access Control Registers */
15371       PBRIDGE_PACR16_23_32B_tag PACR16_23;/* offset: 0x0028 size: 32 bit */
15372   
15373       /* PACR24_31 - Peripheral Access Control Registers */
15374       PBRIDGE_PACR24_31_32B_tag PACR24_31;/* offset: 0x002C size: 32 bit */
15375       int8_t PBRIDGE_reserved_0030[16];
15376   
15377       /* OPACR0_7 - Off-Platform Peripheral Access Control Registers */
15378       PBRIDGE_OPACR0_7_32B_tag OPACR0_7; /* offset: 0x0040 size: 32 bit */
15379   
15380       /* OPACR8_15 - Off-Platform Peripheral Access Control Registers */
15381       PBRIDGE_OPACR8_15_32B_tag OPACR8_15;/* offset: 0x0044 size: 32 bit */
15382   
15383       /* OPACR16_23 - Off-Platform Peripheral Access Control Registers */
15384       PBRIDGE_OPACR16_23_32B_tag OPACR16_23;/* offset: 0x0048 size: 32 bit */
15385   
15386       /* OPACR24_31 - Off-Platform Peripheral Access Control Registers */
15387       PBRIDGE_OPACR24_31_32B_tag OPACR24_31;/* offset: 0x004C size: 32 bit */
15388   
15389       /* OPACR32_39 - Off-Platform Peripheral Access Control Registers */
15390       PBRIDGE_OPACR32_39_32B_tag OPACR32_39;/* offset: 0x0050 size: 32 bit */
15391   
15392       /* OPACR40_47 - Off-Platform Peripheral Access Control Registers */
15393       PBRIDGE_OPACR40_47_32B_tag OPACR40_47;/* offset: 0x0054 size: 32 bit */
15394   
15395       /* OPACR48_55 - Off-Platform Peripheral Access Control Registers */
15396       PBRIDGE_OPACR48_55_32B_tag OPACR48_55;/* offset: 0x0058 size: 32 bit */
15397   
15398       /* OPACR56_63 - Off-Platform Peripheral Access Control Registers */
15399       PBRIDGE_OPACR56_63_32B_tag OPACR56_63;/* offset: 0x005C size: 32 bit */
15400   
15401       /* OPACR64_71 - Off-Platform Peripheral Access Control Registers */
15402       PBRIDGE_OPACR64_71_32B_tag OPACR64_71;/* offset: 0x0060 size: 32 bit */
15403   
15404       /* OPACR72_79 - Off-Platform Peripheral Access Control Registers */
15405       PBRIDGE_OPACR72_79_32B_tag OPACR72_79;/* offset: 0x0064 size: 32 bit */
15406   
15407       /* OPACR80_87 - Off-Platform Peripheral Access Control Registers */
15408       PBRIDGE_OPACR80_87_32B_tag OPACR80_87;/* offset: 0x0068 size: 32 bit */
15409   
15410       /* OPACR88_95 - Off-Platform Peripheral Access Control Registers */
15411       PBRIDGE_OPACR88_95_32B_tag OPACR88_95;/* offset: 0x006C size: 32 bit */
15412       int8_t PBRIDGE_reserved_0070[16272];
15413     } PBRIDGE_tag;
15414   
15415   #define PBRIDGE                        (*(volatile PBRIDGE_tag *) 0xFFF00000UL)
15416   
15417     /****************************************************************/
15418     /*                                                              */
15419     /* Module: MAX  */
15420     /*                                                              */
15421     /****************************************************************/
15422   
15423     /* Register layout for all registers MPR ... */
15424     typedef union {                      /* Master Priority Register for slave port n */
15425       vuint32_t R;
15426       struct {
15427        vuint32_t:
15428         1;
15429         vuint32_t MSTR_7:3;              /* Master 7 Priority */
15430        vuint32_t:
15431         1;
15432         vuint32_t MSTR_6:3;              /* Master 6 Priority */
15433        vuint32_t:
15434         1;
15435         vuint32_t MSTR_5:3;              /* Master 5 Priority */
15436        vuint32_t:
15437         1;
15438         vuint32_t MSTR_4:3;              /* Master 4 Priority */
15439        vuint32_t:
15440         1;
15441         vuint32_t MSTR_3:3;              /* Master 3 Priority */
15442        vuint32_t:
15443         1;
15444         vuint32_t MSTR_2:3;              /* Master 2 Priority */
15445        vuint32_t:
15446         1;
15447         vuint32_t MSTR_1:3;              /* Master 1 Priority */
15448        vuint32_t:
15449         1;
15450         vuint32_t MSTR_0:3;              /* Master 0 Priority */
15451       } B;
15452     } MAX_MPR_32B_tag;
15453   
15454     /* Register layout for all registers AMPR matches MPR */
15455   
15456     /* Register layout for all registers SGPCR ... */
15457     typedef union {                      /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */
15458       vuint32_t R;
15459       struct {
15460         vuint32_t RO:1;                  /* Read Only */
15461         vuint32_t HLP:1;                 /* Halt Low Priority */
15462        vuint32_t:
15463         6;
15464         vuint32_t HPE7:1;                /* High Priority Enable */
15465         vuint32_t HPE6:1;                /* High Priority Enable */
15466         vuint32_t HPE5:1;                /* High Priority Enable */
15467         vuint32_t HPE4:1;                /* High Priority Enable */
15468         vuint32_t HPE3:1;                /* High Priority Enable */
15469         vuint32_t HPE2:1;                /* High Priority Enable */
15470         vuint32_t HPE1:1;                /* High Priority Enable */
15471         vuint32_t HPE0:1;                /* High Priority Enable */
15472        vuint32_t:
15473         6;
15474         vuint32_t ARB:2;                 /* Arbitration Mode */
15475        vuint32_t:
15476         2;
15477         vuint32_t PCTL:2;                /* Parking Control */
15478        vuint32_t:
15479         1;
15480         vuint32_t PARK:3;                /* Park */
15481       } B;
15482     } MAX_SGPCR_32B_tag;
15483   
15484     /* Register layout for all registers ASGPCR ... */
15485     typedef union {                      /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */
15486       vuint32_t R;
15487       struct {
15488        vuint32_t:
15489         1;
15490         vuint32_t HLP:1;                 /* Halt Low Priority */
15491        vuint32_t:
15492         6;
15493         vuint32_t HPE7:1;                /* High Priority Enable */
15494         vuint32_t HPE6:1;                /* High Priority Enable */
15495         vuint32_t HPE5:1;                /* High Priority Enable */
15496         vuint32_t HPE4:1;                /* High Priority Enable */
15497         vuint32_t HPE3:1;                /* High Priority Enable */
15498         vuint32_t HPE2:1;                /* High Priority Enable */
15499         vuint32_t HPE1:1;                /* High Priority Enable */
15500         vuint32_t HPE0:1;                /* High Priority Enable */
15501        vuint32_t:
15502         6;
15503         vuint32_t ARB:2;                 /* Arbitration Mode */
15504        vuint32_t:
15505         2;
15506         vuint32_t PCTL:2;                /* Parking Control */
15507        vuint32_t:
15508         1;
15509         vuint32_t PARK:3;                /* Park */
15510       } B;
15511     } MAX_ASGPCR_32B_tag;
15512   
15513     /* Register layout for all registers MGPCR ... */
15514     typedef union {                      /* MAX_MGPCRn - Master General Purpose Control Register n */
15515       vuint32_t R;
15516       struct {
15517        vuint32_t:
15518         29;
15519         vuint32_t AULB:3;                /* Arbitrate on Undefined Length Bursts */
15520       } B;
15521     } MAX_MGPCR_32B_tag;
15522   
15523     typedef struct MAX_SLAVE_PORT_struct_tag {
15524       /* Master Priority Register for slave port n */
15525       MAX_MPR_32B_tag MPR;               /* relative offset: 0x0000 */
15526   
15527       /* Alternate Master Priority Register for slave port n */
15528       MAX_MPR_32B_tag AMPR;              /* relative offset: 0x0004 */
15529       int8_t MAX_SLAVE_PORT_reserved_0008[8];
15530   
15531       /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */
15532       MAX_SGPCR_32B_tag SGPCR;           /* relative offset: 0x0010 */
15533   
15534       /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */
15535       MAX_ASGPCR_32B_tag ASGPCR;         /* relative offset: 0x0014 */
15536       int8_t MAX_SLAVE_PORT_reserved_0018[232];
15537     } MAX_SLAVE_PORT_tag;
15538   
15539     typedef struct MAX_MASTER_PORT_struct_tag {
15540       /* MAX_MGPCRn - Master General Purpose Control Register n */
15541       MAX_MGPCR_32B_tag MGPCR;           /* relative offset: 0x0000 */
15542       int8_t MAX_MASTER_PORT_reserved_0004[252];
15543     } MAX_MASTER_PORT_tag;
15544   
15545     typedef struct MAX_struct_tag {
15546       union {
15547         /*  Register set SLAVE_PORT */
15548         MAX_SLAVE_PORT_tag SLAVE_PORT[8];/* offset: 0x0000  (0x0100 x 8) */
15549         struct {
15550           /* Master Priority Register for slave port n */
15551           MAX_MPR_32B_tag MPR0;          /* offset: 0x0000 size: 32 bit */
15552   
15553           /* Alternate Master Priority Register for slave port n */
15554           MAX_MPR_32B_tag AMPR0;         /* offset: 0x0004 size: 32 bit */
15555           int8_t MAX_reserved_0008_I1[8];
15556   
15557           /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */
15558           MAX_SGPCR_32B_tag SGPCR0;      /* offset: 0x0010 size: 32 bit */
15559   
15560           /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */
15561           MAX_ASGPCR_32B_tag ASGPCR0;    /* offset: 0x0014 size: 32 bit */
15562           int8_t MAX_reserved_0018_I1[232];
15563   
15564           /* Master Priority Register for slave port n */
15565           MAX_MPR_32B_tag MPR1;          /* offset: 0x0100 size: 32 bit */
15566   
15567           /* Alternate Master Priority Register for slave port n */
15568           MAX_MPR_32B_tag AMPR1;         /* offset: 0x0104 size: 32 bit */
15569           int8_t MAX_reserved_0108_I1[8];
15570   
15571           /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */
15572           MAX_SGPCR_32B_tag SGPCR1;      /* offset: 0x0110 size: 32 bit */
15573   
15574           /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */
15575           MAX_ASGPCR_32B_tag ASGPCR1;    /* offset: 0x0114 size: 32 bit */
15576           int8_t MAX_reserved_0118_I1[232];
15577   
15578           /* Master Priority Register for slave port n */
15579           MAX_MPR_32B_tag MPR2;          /* offset: 0x0200 size: 32 bit */
15580   
15581           /* Alternate Master Priority Register for slave port n */
15582           MAX_MPR_32B_tag AMPR2;         /* offset: 0x0204 size: 32 bit */
15583           int8_t MAX_reserved_0208_I1[8];
15584   
15585           /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */
15586           MAX_SGPCR_32B_tag SGPCR2;      /* offset: 0x0210 size: 32 bit */
15587   
15588           /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */
15589           MAX_ASGPCR_32B_tag ASGPCR2;    /* offset: 0x0214 size: 32 bit */
15590           int8_t MAX_reserved_0218_I1[232];
15591   
15592           /* Master Priority Register for slave port n */
15593           MAX_MPR_32B_tag MPR3;          /* offset: 0x0300 size: 32 bit */
15594   
15595           /* Alternate Master Priority Register for slave port n */
15596           MAX_MPR_32B_tag AMPR3;         /* offset: 0x0304 size: 32 bit */
15597           int8_t MAX_reserved_0308_I1[8];
15598   
15599           /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */
15600           MAX_SGPCR_32B_tag SGPCR3;      /* offset: 0x0310 size: 32 bit */
15601   
15602           /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */
15603           MAX_ASGPCR_32B_tag ASGPCR3;    /* offset: 0x0314 size: 32 bit */
15604           int8_t MAX_reserved_0318_I1[232];
15605   
15606           /* Master Priority Register for slave port n */
15607           MAX_MPR_32B_tag MPR4;          /* offset: 0x0400 size: 32 bit */
15608   
15609           /* Alternate Master Priority Register for slave port n */
15610           MAX_MPR_32B_tag AMPR4;         /* offset: 0x0404 size: 32 bit */
15611           int8_t MAX_reserved_0408_I1[8];
15612   
15613           /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */
15614           MAX_SGPCR_32B_tag SGPCR4;      /* offset: 0x0410 size: 32 bit */
15615   
15616           /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */
15617           MAX_ASGPCR_32B_tag ASGPCR4;    /* offset: 0x0414 size: 32 bit */
15618           int8_t MAX_reserved_0418_I1[232];
15619   
15620           /* Master Priority Register for slave port n */
15621           MAX_MPR_32B_tag MPR5;          /* offset: 0x0500 size: 32 bit */
15622   
15623           /* Alternate Master Priority Register for slave port n */
15624           MAX_MPR_32B_tag AMPR5;         /* offset: 0x0504 size: 32 bit */
15625           int8_t MAX_reserved_0508_I1[8];
15626   
15627           /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */
15628           MAX_SGPCR_32B_tag SGPCR5;      /* offset: 0x0510 size: 32 bit */
15629   
15630           /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */
15631           MAX_ASGPCR_32B_tag ASGPCR5;    /* offset: 0x0514 size: 32 bit */
15632           int8_t MAX_reserved_0518_I1[232];
15633   
15634           /* Master Priority Register for slave port n */
15635           MAX_MPR_32B_tag MPR6;          /* offset: 0x0600 size: 32 bit */
15636   
15637           /* Alternate Master Priority Register for slave port n */
15638           MAX_MPR_32B_tag AMPR6;         /* offset: 0x0604 size: 32 bit */
15639           int8_t MAX_reserved_0608_I1[8];
15640   
15641           /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */
15642           MAX_SGPCR_32B_tag SGPCR6;      /* offset: 0x0610 size: 32 bit */
15643   
15644           /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */
15645           MAX_ASGPCR_32B_tag ASGPCR6;    /* offset: 0x0614 size: 32 bit */
15646           int8_t MAX_reserved_0618_I1[232];
15647   
15648           /* Master Priority Register for slave port n */
15649           MAX_MPR_32B_tag MPR7;          /* offset: 0x0700 size: 32 bit */
15650   
15651           /* Alternate Master Priority Register for slave port n */
15652           MAX_MPR_32B_tag AMPR7;         /* offset: 0x0704 size: 32 bit */
15653           int8_t MAX_reserved_0708_I1[8];
15654   
15655           /* MAX_SGPCRn - MAX General Purpose Control Register for Slave Port n */
15656           MAX_SGPCR_32B_tag SGPCR7;      /* offset: 0x0710 size: 32 bit */
15657   
15658           /* MAX_ASGPCRn - MAX Alternate General Purpose Control Register n */
15659           MAX_ASGPCR_32B_tag ASGPCR7;    /* offset: 0x0714 size: 32 bit */
15660           int8_t MAX_reserved_0718_E1[232];
15661         };
15662       };
15663   
15664       union {
15665         /*  Register set MASTER_PORT */
15666         MAX_MASTER_PORT_tag MASTER_PORT[8];/* offset: 0x0800  (0x0100 x 8) */
15667         struct {
15668           /* MAX_MGPCRn - Master General Purpose Control Register n */
15669           MAX_MGPCR_32B_tag MGPCR0;      /* offset: 0x0800 size: 32 bit */
15670           int8_t MAX_reserved_0804_I1[252];
15671           MAX_MGPCR_32B_tag MGPCR1;      /* offset: 0x0900 size: 32 bit */
15672           int8_t MAX_reserved_0904_I1[252];
15673           MAX_MGPCR_32B_tag MGPCR2;      /* offset: 0x0A00 size: 32 bit */
15674           int8_t MAX_reserved_0A04_I1[252];
15675           MAX_MGPCR_32B_tag MGPCR3;      /* offset: 0x0B00 size: 32 bit */
15676           int8_t MAX_reserved_0B04_I1[252];
15677           MAX_MGPCR_32B_tag MGPCR4;      /* offset: 0x0C00 size: 32 bit */
15678           int8_t MAX_reserved_0C04_I1[252];
15679           MAX_MGPCR_32B_tag MGPCR5;      /* offset: 0x0D00 size: 32 bit */
15680           int8_t MAX_reserved_0D04_I1[252];
15681           MAX_MGPCR_32B_tag MGPCR6;      /* offset: 0x0E00 size: 32 bit */
15682           int8_t MAX_reserved_0E04_I1[252];
15683           MAX_MGPCR_32B_tag MGPCR7;      /* offset: 0x0F00 size: 32 bit */
15684           int8_t MAX_reserved_0F04_E1[252];
15685         };
15686       };
15687   
15688       int8_t MAX_reserved_1000[12288];
15689     } MAX_tag;
15690   
15691   #define MAX                            (*(volatile MAX_tag *) 0xFFF04000UL)
15692   
15693     /****************************************************************/
15694     /*                                                              */
15695     /* Module: MPU  */
15696     /*                                                              */
15697     /****************************************************************/
15698     typedef union {                      /* MPU_CESR - MPU Control/Error Status Register */
15699       vuint32_t R;
15700       struct {
15701         vuint32_t SPERR:8;               /* Slave Port n Error */
15702        vuint32_t:
15703         4;
15704         vuint32_t HRL:4;                 /* Hardware Revision Level */
15705         vuint32_t NSP:4;                 /* Number of Slave Ports */
15706         vuint32_t NRGD:4;                /* Number of Region Descriptors */
15707        vuint32_t:
15708         7;
15709         vuint32_t VLD:1;                 /* Valid bit */
15710       } B;
15711     } MPU_CESR_32B_tag;
15712   
15713     /* Register layout for all registers EAR ... */
15714     typedef union {                      /* MPU_EARn - MPU Error Address Register, Slave Port n */
15715       vuint32_t R;
15716       struct {
15717         vuint32_t EADDR:32;              /* Error Address */
15718       } B;
15719     } MPU_EAR_32B_tag;
15720   
15721     /* Register layout for all registers EDR ... */
15722     typedef union {                      /* MPU_EDRn - MPU Error Detail Register, Slave Port n */
15723       vuint32_t R;
15724       struct {
15725         vuint32_t EACD:16;               /* Error Access Control Detail */
15726         vuint32_t EPID:8;                /* Error Process Identification */
15727         vuint32_t EMN:4;                 /* Error Master Number */
15728         vuint32_t EATTR:3;               /* Error Attributes */
15729         vuint32_t ERW:1;                 /* Error Read/Write */
15730       } B;
15731     } MPU_EDR_32B_tag;
15732   
15733     /* Register layout for all registers RGD_WORD0 ... */
15734     typedef union {                      /* MPU_RGDn_Word0 - MPU Region Descriptor */
15735       vuint32_t R;
15736       struct {
15737         vuint32_t SRTADDR:27;            /* Start Address */
15738        vuint32_t:
15739         5;
15740       } B;
15741     } MPU_RGD_WORD0_32B_tag;
15742   
15743     /* Register layout for all registers RGD_WORD1 ... */
15744     typedef union {                      /* MPU_RGDn_Word1 - MPU Region Descriptor */
15745       vuint32_t R;
15746       struct {
15747         vuint32_t ENDADDR:27;            /* End Address */
15748        vuint32_t:
15749         5;
15750       } B;
15751     } MPU_RGD_WORD1_32B_tag;
15752   
15753     /* Register layout for all registers RGD_WORD2 ... */
15754     typedef union {                      /* MPU_RGDn_Word2 - MPU Region Descriptor */
15755       vuint32_t R;
15756       struct {
15757         vuint32_t M7RE:1;                /* Bus Master 7 Read Enable */
15758         vuint32_t M7WE:1;                /* Bus Master 7 Write Enable */
15759         vuint32_t M6RE:1;                /* Bus Master 6 Read Enable */
15760         vuint32_t M6WE:1;                /* Bus Master 7 Write Enable */
15761         vuint32_t M5RE:1;                /* Bus Master 5 Read Enable */
15762         vuint32_t M5WE:1;                /* Bus Master 5 Write Enable */
15763         vuint32_t M4RE:1;                /* Bus Master 4 Read Enable */
15764         vuint32_t M4WE:1;                /* Bus Master 4 Write Enable */
15765         vuint32_t M3PE:1;                /* Bus Master 3 Process Identifier Enable */
15766         vuint32_t M3SM:2;                /* Bus Master 3 Supervisor Mode Access Control */
15767         vuint32_t M3UM:3;                /* Bus Master 3 User Mode Access Control */
15768         vuint32_t M2PE:1;                /* Bus Master 2 Process Identifier Enable */
15769         vuint32_t M2SM:2;                /* Bus Master 2 Supervisor Mode Access Control */
15770         vuint32_t M2UM:3;                /* Bus Master 2 User Mode Access Control */
15771         vuint32_t M1PE:1;                /* Bus Master 1 Process Identifier Enable */
15772         vuint32_t M1SM:2;                /* Bus Master 1 Supervisor Mode Access Control */
15773         vuint32_t M1UM:3;                /* Bus Master 1 User Mode Access Control */
15774         vuint32_t M0PE:1;                /* Bus Master 0 Process Identifier Enable */
15775         vuint32_t M0SM:2;                /* Bus Master 0 Supervisor Mode Access Control */
15776         vuint32_t M0UM:3;                /* Bus Master 0 User Mode Access Control */
15777       } B;
15778     } MPU_RGD_WORD2_32B_tag;
15779   
15780     /* Register layout for all registers RGD_WORD3 ... */
15781     typedef union {                      /* MPU_RGDn_Word3 - MPU Region Descriptor */
15782       vuint32_t R;
15783       struct {
15784         vuint32_t PID:8;                 /* Process Identifier */
15785         vuint32_t PIDMASK:8;             /* Process Identifier Mask */
15786        vuint32_t:
15787         15;
15788         vuint32_t VLD:1;                 /* Valid */
15789       } B;
15790     } MPU_RGD_WORD3_32B_tag;
15791   
15792     /* Register layout for all registers RGDAAC ... */
15793     typedef union {                      /* MPU_RGDAACn -  MPU Region Descriptor Alternate Access Control */
15794       vuint32_t R;
15795       struct {
15796         vuint32_t M7RE:1;                /* Bus Master 7 Read Enable */
15797         vuint32_t M7WE:1;                /* Bus Master 7 Write Enable */
15798         vuint32_t M6RE:1;                /* Bus Master 6 Read Enable */
15799         vuint32_t M6WE:1;                /* Bus Master 7 Write Enable */
15800         vuint32_t M5RE:1;                /* Bus Master 5 Read Enable */
15801         vuint32_t M5WE:1;                /* Bus Master 5 Write Enable */
15802         vuint32_t M4RE:1;                /* Bus Master 4 Read Enable */
15803         vuint32_t M4WE:1;                /* Bus Master 4 Write Enable */
15804         vuint32_t M3PE:1;                /* Bus Master 3 Process Identifier Enable */
15805         vuint32_t M3SM:2;                /* Bus Master 3 Supervisor Mode Access Control */
15806         vuint32_t M3UM:3;                /* Bus Master 3 User Mode Access Control */
15807         vuint32_t M2PE:1;                /* Bus Master 2 Process Identifier Enable */
15808         vuint32_t M2SM:2;                /* Bus Master 2 Supervisor Mode Access Control */
15809         vuint32_t M2UM:3;                /* Bus Master 2 User Mode Access Control */
15810         vuint32_t M1PE:1;                /* Bus Master 1 Process Identifier Enable */
15811         vuint32_t M1SM:2;                /* Bus Master 1 Supervisor Mode Access Control */
15812         vuint32_t M1UM:3;                /* Bus Master 1 User Mode Access Control */
15813         vuint32_t M0PE:1;                /* Bus Master 0 Process Identifier Enable */
15814         vuint32_t M0SM:2;                /* Bus Master 0 Supervisor Mode Access Control */
15815         vuint32_t M0UM:3;                /* Bus Master 0 User Mode Access Control */
15816       } B;
15817     } MPU_RGDAAC_32B_tag;
15818   
15819     typedef struct MPU_SLAVE_PORT_struct_tag {
15820       /* MPU_EARn - MPU Error Address Register, Slave Port n */
15821       MPU_EAR_32B_tag EAR;               /* relative offset: 0x0000 */
15822   
15823       /* MPU_EDRn - MPU Error Detail Register, Slave Port n */
15824       MPU_EDR_32B_tag EDR;               /* relative offset: 0x0004 */
15825     } MPU_SLAVE_PORT_tag;
15826   
15827     typedef struct MPU_REGION_struct_tag {
15828       /* MPU_RGDn_Word0 - MPU Region Descriptor */
15829       MPU_RGD_WORD0_32B_tag RGD_WORD0;   /* relative offset: 0x0000 */
15830   
15831       /* MPU_RGDn_Word1 - MPU Region Descriptor */
15832       MPU_RGD_WORD1_32B_tag RGD_WORD1;   /* relative offset: 0x0004 */
15833   
15834       /* MPU_RGDn_Word2 - MPU Region Descriptor */
15835       MPU_RGD_WORD2_32B_tag RGD_WORD2;   /* relative offset: 0x0008 */
15836   
15837       /* MPU_RGDn_Word3 - MPU Region Descriptor */
15838       MPU_RGD_WORD3_32B_tag RGD_WORD3;   /* relative offset: 0x000C */
15839     } MPU_REGION_tag;
15840   
15841     typedef struct MPU_struct_tag {
15842       /* MPU_CESR - MPU Control/Error Status Register */
15843       MPU_CESR_32B_tag CESR;             /* offset: 0x0000 size: 32 bit */
15844       int8_t MPU_reserved_0004[12];
15845       union {
15846         /*  Register set SLAVE_PORT */
15847         MPU_SLAVE_PORT_tag SLAVE_PORT[4];/* offset: 0x0010  (0x0008 x 4) */
15848         struct {
15849           /* MPU_EARn - MPU Error Address Register, Slave Port n */
15850           MPU_EAR_32B_tag EAR0;          /* offset: 0x0010 size: 32 bit */
15851   
15852           /* MPU_EDRn - MPU Error Detail Register, Slave Port n */
15853           MPU_EDR_32B_tag EDR0;          /* offset: 0x0014 size: 32 bit */
15854   
15855           /* MPU_EARn - MPU Error Address Register, Slave Port n */
15856           MPU_EAR_32B_tag EAR1;          /* offset: 0x0018 size: 32 bit */
15857   
15858           /* MPU_EDRn - MPU Error Detail Register, Slave Port n */
15859           MPU_EDR_32B_tag EDR1;          /* offset: 0x001C size: 32 bit */
15860   
15861           /* MPU_EARn - MPU Error Address Register, Slave Port n */
15862           MPU_EAR_32B_tag EAR2;          /* offset: 0x0020 size: 32 bit */
15863   
15864           /* MPU_EDRn - MPU Error Detail Register, Slave Port n */
15865           MPU_EDR_32B_tag EDR2;          /* offset: 0x0024 size: 32 bit */
15866   
15867           /* MPU_EARn - MPU Error Address Register, Slave Port n */
15868           MPU_EAR_32B_tag EAR3;          /* offset: 0x0028 size: 32 bit */
15869   
15870           /* MPU_EDRn - MPU Error Detail Register, Slave Port n */
15871           MPU_EDR_32B_tag EDR3;          /* offset: 0x002C size: 32 bit */
15872         };
15873       };
15874   
15875       int8_t MPU_reserved_0030[976];
15876       union {
15877         /*  Register set REGION */
15878         MPU_REGION_tag REGION[16];       /* offset: 0x0400  (0x0010 x 16) */
15879         struct {
15880           /* MPU_RGDn_Word0 - MPU Region Descriptor */
15881           MPU_RGD_WORD0_32B_tag RGD0_WORD0;/* offset: 0x0400 size: 32 bit */
15882   
15883           /* MPU_RGDn_Word1 - MPU Region Descriptor */
15884           MPU_RGD_WORD1_32B_tag RGD0_WORD1;/* offset: 0x0404 size: 32 bit */
15885   
15886           /* MPU_RGDn_Word2 - MPU Region Descriptor */
15887           MPU_RGD_WORD2_32B_tag RGD0_WORD2;/* offset: 0x0408 size: 32 bit */
15888   
15889           /* MPU_RGDn_Word3 - MPU Region Descriptor */
15890           MPU_RGD_WORD3_32B_tag RGD0_WORD3;/* offset: 0x040C size: 32 bit */
15891   
15892           /* MPU_RGDn_Word0 - MPU Region Descriptor */
15893           MPU_RGD_WORD0_32B_tag RGD1_WORD0;/* offset: 0x0410 size: 32 bit */
15894   
15895           /* MPU_RGDn_Word1 - MPU Region Descriptor */
15896           MPU_RGD_WORD1_32B_tag RGD1_WORD1;/* offset: 0x0414 size: 32 bit */
15897   
15898           /* MPU_RGDn_Word2 - MPU Region Descriptor */
15899           MPU_RGD_WORD2_32B_tag RGD1_WORD2;/* offset: 0x0418 size: 32 bit */
15900   
15901           /* MPU_RGDn_Word3 - MPU Region Descriptor */
15902           MPU_RGD_WORD3_32B_tag RGD1_WORD3;/* offset: 0x041C size: 32 bit */
15903   
15904           /* MPU_RGDn_Word0 - MPU Region Descriptor */
15905           MPU_RGD_WORD0_32B_tag RGD2_WORD0;/* offset: 0x0420 size: 32 bit */
15906   
15907           /* MPU_RGDn_Word1 - MPU Region Descriptor */
15908           MPU_RGD_WORD1_32B_tag RGD2_WORD1;/* offset: 0x0424 size: 32 bit */
15909   
15910           /* MPU_RGDn_Word2 - MPU Region Descriptor */
15911           MPU_RGD_WORD2_32B_tag RGD2_WORD2;/* offset: 0x0428 size: 32 bit */
15912   
15913           /* MPU_RGDn_Word3 - MPU Region Descriptor */
15914           MPU_RGD_WORD3_32B_tag RGD2_WORD3;/* offset: 0x042C size: 32 bit */
15915   
15916           /* MPU_RGDn_Word0 - MPU Region Descriptor */
15917           MPU_RGD_WORD0_32B_tag RGD3_WORD0;/* offset: 0x0430 size: 32 bit */
15918   
15919           /* MPU_RGDn_Word1 - MPU Region Descriptor */
15920           MPU_RGD_WORD1_32B_tag RGD3_WORD1;/* offset: 0x0434 size: 32 bit */
15921   
15922           /* MPU_RGDn_Word2 - MPU Region Descriptor */
15923           MPU_RGD_WORD2_32B_tag RGD3_WORD2;/* offset: 0x0438 size: 32 bit */
15924   
15925           /* MPU_RGDn_Word3 - MPU Region Descriptor */
15926           MPU_RGD_WORD3_32B_tag RGD3_WORD3;/* offset: 0x043C size: 32 bit */
15927   
15928           /* MPU_RGDn_Word0 - MPU Region Descriptor */
15929           MPU_RGD_WORD0_32B_tag RGD4_WORD0;/* offset: 0x0440 size: 32 bit */
15930   
15931           /* MPU_RGDn_Word1 - MPU Region Descriptor */
15932           MPU_RGD_WORD1_32B_tag RGD4_WORD1;/* offset: 0x0444 size: 32 bit */
15933   
15934           /* MPU_RGDn_Word2 - MPU Region Descriptor */
15935           MPU_RGD_WORD2_32B_tag RGD4_WORD2;/* offset: 0x0448 size: 32 bit */
15936   
15937           /* MPU_RGDn_Word3 - MPU Region Descriptor */
15938           MPU_RGD_WORD3_32B_tag RGD4_WORD3;/* offset: 0x044C size: 32 bit */
15939   
15940           /* MPU_RGDn_Word0 - MPU Region Descriptor */
15941           MPU_RGD_WORD0_32B_tag RGD5_WORD0;/* offset: 0x0450 size: 32 bit */
15942   
15943           /* MPU_RGDn_Word1 - MPU Region Descriptor */
15944           MPU_RGD_WORD1_32B_tag RGD5_WORD1;/* offset: 0x0454 size: 32 bit */
15945   
15946           /* MPU_RGDn_Word2 - MPU Region Descriptor */
15947           MPU_RGD_WORD2_32B_tag RGD5_WORD2;/* offset: 0x0458 size: 32 bit */
15948   
15949           /* MPU_RGDn_Word3 - MPU Region Descriptor */
15950           MPU_RGD_WORD3_32B_tag RGD5_WORD3;/* offset: 0x045C size: 32 bit */
15951   
15952           /* MPU_RGDn_Word0 - MPU Region Descriptor */
15953           MPU_RGD_WORD0_32B_tag RGD6_WORD0;/* offset: 0x0460 size: 32 bit */
15954   
15955           /* MPU_RGDn_Word1 - MPU Region Descriptor */
15956           MPU_RGD_WORD1_32B_tag RGD6_WORD1;/* offset: 0x0464 size: 32 bit */
15957   
15958           /* MPU_RGDn_Word2 - MPU Region Descriptor */
15959           MPU_RGD_WORD2_32B_tag RGD6_WORD2;/* offset: 0x0468 size: 32 bit */
15960   
15961           /* MPU_RGDn_Word3 - MPU Region Descriptor */
15962           MPU_RGD_WORD3_32B_tag RGD6_WORD3;/* offset: 0x046C size: 32 bit */
15963   
15964           /* MPU_RGDn_Word0 - MPU Region Descriptor */
15965           MPU_RGD_WORD0_32B_tag RGD7_WORD0;/* offset: 0x0470 size: 32 bit */
15966   
15967           /* MPU_RGDn_Word1 - MPU Region Descriptor */
15968           MPU_RGD_WORD1_32B_tag RGD7_WORD1;/* offset: 0x0474 size: 32 bit */
15969   
15970           /* MPU_RGDn_Word2 - MPU Region Descriptor */
15971           MPU_RGD_WORD2_32B_tag RGD7_WORD2;/* offset: 0x0478 size: 32 bit */
15972   
15973           /* MPU_RGDn_Word3 - MPU Region Descriptor */
15974           MPU_RGD_WORD3_32B_tag RGD7_WORD3;/* offset: 0x047C size: 32 bit */
15975   
15976           /* MPU_RGDn_Word0 - MPU Region Descriptor */
15977           MPU_RGD_WORD0_32B_tag RGD8_WORD0;/* offset: 0x0480 size: 32 bit */
15978   
15979           /* MPU_RGDn_Word1 - MPU Region Descriptor */
15980           MPU_RGD_WORD1_32B_tag RGD8_WORD1;/* offset: 0x0484 size: 32 bit */
15981   
15982           /* MPU_RGDn_Word2 - MPU Region Descriptor */
15983           MPU_RGD_WORD2_32B_tag RGD8_WORD2;/* offset: 0x0488 size: 32 bit */
15984   
15985           /* MPU_RGDn_Word3 - MPU Region Descriptor */
15986           MPU_RGD_WORD3_32B_tag RGD8_WORD3;/* offset: 0x048C size: 32 bit */
15987   
15988           /* MPU_RGDn_Word0 - MPU Region Descriptor */
15989           MPU_RGD_WORD0_32B_tag RGD9_WORD0;/* offset: 0x0490 size: 32 bit */
15990   
15991           /* MPU_RGDn_Word1 - MPU Region Descriptor */
15992           MPU_RGD_WORD1_32B_tag RGD9_WORD1;/* offset: 0x0494 size: 32 bit */
15993   
15994           /* MPU_RGDn_Word2 - MPU Region Descriptor */
15995           MPU_RGD_WORD2_32B_tag RGD9_WORD2;/* offset: 0x0498 size: 32 bit */
15996   
15997           /* MPU_RGDn_Word3 - MPU Region Descriptor */
15998           MPU_RGD_WORD3_32B_tag RGD9_WORD3;/* offset: 0x049C size: 32 bit */
15999   
16000           /* MPU_RGDn_Word0 - MPU Region Descriptor */
16001           MPU_RGD_WORD0_32B_tag RGD10_WORD0;/* offset: 0x04A0 size: 32 bit */
16002   
16003           /* MPU_RGDn_Word1 - MPU Region Descriptor */
16004           MPU_RGD_WORD1_32B_tag RGD10_WORD1;/* offset: 0x04A4 size: 32 bit */
16005   
16006           /* MPU_RGDn_Word2 - MPU Region Descriptor */
16007           MPU_RGD_WORD2_32B_tag RGD10_WORD2;/* offset: 0x04A8 size: 32 bit */
16008   
16009           /* MPU_RGDn_Word3 - MPU Region Descriptor */
16010           MPU_RGD_WORD3_32B_tag RGD10_WORD3;/* offset: 0x04AC size: 32 bit */
16011   
16012           /* MPU_RGDn_Word0 - MPU Region Descriptor */
16013           MPU_RGD_WORD0_32B_tag RGD11_WORD0;/* offset: 0x04B0 size: 32 bit */
16014   
16015           /* MPU_RGDn_Word1 - MPU Region Descriptor */
16016           MPU_RGD_WORD1_32B_tag RGD11_WORD1;/* offset: 0x04B4 size: 32 bit */
16017   
16018           /* MPU_RGDn_Word2 - MPU Region Descriptor */
16019           MPU_RGD_WORD2_32B_tag RGD11_WORD2;/* offset: 0x04B8 size: 32 bit */
16020   
16021           /* MPU_RGDn_Word3 - MPU Region Descriptor */
16022           MPU_RGD_WORD3_32B_tag RGD11_WORD3;/* offset: 0x04BC size: 32 bit */
16023   
16024           /* MPU_RGDn_Word0 - MPU Region Descriptor */
16025           MPU_RGD_WORD0_32B_tag RGD12_WORD0;/* offset: 0x04C0 size: 32 bit */
16026   
16027           /* MPU_RGDn_Word1 - MPU Region Descriptor */
16028           MPU_RGD_WORD1_32B_tag RGD12_WORD1;/* offset: 0x04C4 size: 32 bit */
16029   
16030           /* MPU_RGDn_Word2 - MPU Region Descriptor */
16031           MPU_RGD_WORD2_32B_tag RGD12_WORD2;/* offset: 0x04C8 size: 32 bit */
16032   
16033           /* MPU_RGDn_Word3 - MPU Region Descriptor */
16034           MPU_RGD_WORD3_32B_tag RGD12_WORD3;/* offset: 0x04CC size: 32 bit */
16035   
16036           /* MPU_RGDn_Word0 - MPU Region Descriptor */
16037           MPU_RGD_WORD0_32B_tag RGD13_WORD0;/* offset: 0x04D0 size: 32 bit */
16038   
16039           /* MPU_RGDn_Word1 - MPU Region Descriptor */
16040           MPU_RGD_WORD1_32B_tag RGD13_WORD1;/* offset: 0x04D4 size: 32 bit */
16041   
16042           /* MPU_RGDn_Word2 - MPU Region Descriptor */
16043           MPU_RGD_WORD2_32B_tag RGD13_WORD2;/* offset: 0x04D8 size: 32 bit */
16044   
16045           /* MPU_RGDn_Word3 - MPU Region Descriptor */
16046           MPU_RGD_WORD3_32B_tag RGD13_WORD3;/* offset: 0x04DC size: 32 bit */
16047   
16048           /* MPU_RGDn_Word0 - MPU Region Descriptor */
16049           MPU_RGD_WORD0_32B_tag RGD14_WORD0;/* offset: 0x04E0 size: 32 bit */
16050   
16051           /* MPU_RGDn_Word1 - MPU Region Descriptor */
16052           MPU_RGD_WORD1_32B_tag RGD14_WORD1;/* offset: 0x04E4 size: 32 bit */
16053   
16054           /* MPU_RGDn_Word2 - MPU Region Descriptor */
16055           MPU_RGD_WORD2_32B_tag RGD14_WORD2;/* offset: 0x04E8 size: 32 bit */
16056   
16057           /* MPU_RGDn_Word3 - MPU Region Descriptor */
16058           MPU_RGD_WORD3_32B_tag RGD14_WORD3;/* offset: 0x04EC size: 32 bit */
16059   
16060           /* MPU_RGDn_Word0 - MPU Region Descriptor */
16061           MPU_RGD_WORD0_32B_tag RGD15_WORD0;/* offset: 0x04F0 size: 32 bit */
16062   
16063           /* MPU_RGDn_Word1 - MPU Region Descriptor */
16064           MPU_RGD_WORD1_32B_tag RGD15_WORD1;/* offset: 0x04F4 size: 32 bit */
16065   
16066           /* MPU_RGDn_Word2 - MPU Region Descriptor */
16067           MPU_RGD_WORD2_32B_tag RGD15_WORD2;/* offset: 0x04F8 size: 32 bit */
16068   
16069           /* MPU_RGDn_Word3 - MPU Region Descriptor */
16070           MPU_RGD_WORD3_32B_tag RGD15_WORD3;/* offset: 0x04FC size: 32 bit */
16071         };
16072       };
16073   
16074       int8_t MPU_reserved_0500[768];
16075       union {
16076         /* MPU_RGDAACn -  MPU Region Descriptor Alternate Access Control */
16077         MPU_RGDAAC_32B_tag RGDAAC[16];   /* offset: 0x0800  (0x0004 x 16) */
16078         struct {
16079           /* MPU_RGDAACn -  MPU Region Descriptor Alternate Access Control */
16080           MPU_RGDAAC_32B_tag RGDAAC0;    /* offset: 0x0800 size: 32 bit */
16081           MPU_RGDAAC_32B_tag RGDAAC1;    /* offset: 0x0804 size: 32 bit */
16082           MPU_RGDAAC_32B_tag RGDAAC2;    /* offset: 0x0808 size: 32 bit */
16083           MPU_RGDAAC_32B_tag RGDAAC3;    /* offset: 0x080C size: 32 bit */
16084           MPU_RGDAAC_32B_tag RGDAAC4;    /* offset: 0x0810 size: 32 bit */
16085           MPU_RGDAAC_32B_tag RGDAAC5;    /* offset: 0x0814 size: 32 bit */
16086           MPU_RGDAAC_32B_tag RGDAAC6;    /* offset: 0x0818 size: 32 bit */
16087           MPU_RGDAAC_32B_tag RGDAAC7;    /* offset: 0x081C size: 32 bit */
16088           MPU_RGDAAC_32B_tag RGDAAC8;    /* offset: 0x0820 size: 32 bit */
16089           MPU_RGDAAC_32B_tag RGDAAC9;    /* offset: 0x0824 size: 32 bit */
16090           MPU_RGDAAC_32B_tag RGDAAC10;   /* offset: 0x0828 size: 32 bit */
16091           MPU_RGDAAC_32B_tag RGDAAC11;   /* offset: 0x082C size: 32 bit */
16092           MPU_RGDAAC_32B_tag RGDAAC12;   /* offset: 0x0830 size: 32 bit */
16093           MPU_RGDAAC_32B_tag RGDAAC13;   /* offset: 0x0834 size: 32 bit */
16094           MPU_RGDAAC_32B_tag RGDAAC14;   /* offset: 0x0838 size: 32 bit */
16095           MPU_RGDAAC_32B_tag RGDAAC15;   /* offset: 0x083C size: 32 bit */
16096         };
16097       };
16098   
16099       int8_t MPU_reserved_0840[14272];
16100     } MPU_tag;
16101   
16102   #define MPU                            (*(volatile MPU_tag *) 0xFFF10000UL)
16103   
16104     /****************************************************************/
16105     /*                                                              */
16106     /* Module: SEMA4  */
16107     /*                                                              */
16108     /****************************************************************/
16109   
16110     /* Register layout for all registers GATE ... */
16111     typedef union {                      /* SEMA4_GATEn - Semephores Gate Register */
16112       vuint8_t R;
16113       struct {
16114        vuint8_t:
16115         6;
16116         vuint8_t GTFSM:2;                /* Gate Finite State machine */
16117       } B;
16118     } SEMA4_GATE_8B_tag;
16119   
16120     typedef union {                      /* SEMA4_CP0INE - Semaphores Processor IRQ Notification Enable */
16121       vuint16_t R;
16122       struct {
16123         vuint16_t INE:16;                /* Interrupt Request Notification Enable */
16124       } B;
16125     } SEMA4_CP0INE_16B_tag;
16126   
16127     typedef union {                      /* SEMA4_CP1INE - Semaphores Processor IRQ Notification Enable */
16128       vuint16_t R;
16129       struct {
16130         vuint16_t INE:16;                /* Interrupt Request Notification Enable */
16131       } B;
16132     } SEMA4_CP1INE_16B_tag;
16133   
16134     typedef union {                      /* SEMA4_CP0NTF - Semaphores Processor IRQ Notification */
16135       vuint16_t R;
16136       struct {
16137         vuint16_t GN:16;                 /* Gate 0 Notification */
16138       } B;
16139     } SEMA4_CP0NTF_16B_tag;
16140   
16141     typedef union {                      /* SEMA4_CP1NTF - Semaphores Processor IRQ Notification */
16142       vuint16_t R;
16143       struct {
16144         vuint16_t GN:16;                 /* Gate 1 Notification */
16145       } B;
16146     } SEMA4_CP1NTF_16B_tag;
16147   
16148     typedef union {                      /* SEMA4_RSTGT -  Semaphores Reset Gate */
16149       vuint16_t R;
16150       struct {
16151        vuint16_t:
16152         2;
16153         vuint16_t RSTGSM:2;              /* Reset Gate Finite State Machine */
16154         vuint16_t RSTGDP:7;              /* Reset Gate Data Pattern */
16155         vuint16_t RSTGMS:3;              /* Reset Gate Bus Master */
16156         vuint16_t RSTGTN:8;              /* Reset Gate Number */
16157       } B;
16158     } SEMA4_RSTGT_16B_tag;
16159   
16160     typedef union {                      /* SEMA4_RSTNTF - Semaphores Reset Reset IRQ Notification */
16161       vuint16_t R;
16162       struct {
16163        vuint16_t:
16164         2;
16165         vuint16_t RSTNSM:2;              /* Reset Gate Finite State Machine */
16166         vuint16_t RSTNDP:7;              /* Reset Gate Data Pattern */
16167         vuint16_t RSTNMS:3;              /* Reset Gate Bus Master */
16168         vuint16_t RSTNTN:8;              /* Reset Gate Number */
16169       } B;
16170     } SEMA4_RSTNTF_16B_tag;
16171   
16172     typedef struct SEMA4_struct_tag {
16173       union {
16174         /* SEMA4_GATEn - Semephores Gate Register */
16175         SEMA4_GATE_8B_tag GATE[16];      /* offset: 0x0000  (0x0001 x 16) */
16176         struct {
16177           /* SEMA4_GATEn - Semephores Gate Register */
16178           SEMA4_GATE_8B_tag GATE0;       /* offset: 0x0000 size: 8 bit */
16179           SEMA4_GATE_8B_tag GATE1;       /* offset: 0x0001 size: 8 bit */
16180           SEMA4_GATE_8B_tag GATE2;       /* offset: 0x0002 size: 8 bit */
16181           SEMA4_GATE_8B_tag GATE3;       /* offset: 0x0003 size: 8 bit */
16182           SEMA4_GATE_8B_tag GATE4;       /* offset: 0x0004 size: 8 bit */
16183           SEMA4_GATE_8B_tag GATE5;       /* offset: 0x0005 size: 8 bit */
16184           SEMA4_GATE_8B_tag GATE6;       /* offset: 0x0006 size: 8 bit */
16185           SEMA4_GATE_8B_tag GATE7;       /* offset: 0x0007 size: 8 bit */
16186           SEMA4_GATE_8B_tag GATE8;       /* offset: 0x0008 size: 8 bit */
16187           SEMA4_GATE_8B_tag GATE9;       /* offset: 0x0009 size: 8 bit */
16188           SEMA4_GATE_8B_tag GATE10;      /* offset: 0x000A size: 8 bit */
16189           SEMA4_GATE_8B_tag GATE11;      /* offset: 0x000B size: 8 bit */
16190           SEMA4_GATE_8B_tag GATE12;      /* offset: 0x000C size: 8 bit */
16191           SEMA4_GATE_8B_tag GATE13;      /* offset: 0x000D size: 8 bit */
16192           SEMA4_GATE_8B_tag GATE14;      /* offset: 0x000E size: 8 bit */
16193           SEMA4_GATE_8B_tag GATE15;      /* offset: 0x000F size: 8 bit */
16194         };
16195       };
16196   
16197       int8_t SEMA4_reserved_0010[48];
16198   
16199       /* SEMA4_CP0INE - Semaphores Processor IRQ Notification Enable */
16200       SEMA4_CP0INE_16B_tag CP0INE;       /* offset: 0x0040 size: 16 bit */
16201       int8_t SEMA4_reserved_0042[6];
16202   
16203       /* SEMA4_CP1INE - Semaphores Processor IRQ Notification Enable */
16204       SEMA4_CP1INE_16B_tag CP1INE;       /* offset: 0x0048 size: 16 bit */
16205       int8_t SEMA4_reserved_004A[54];
16206   
16207       /* SEMA4_CP0NTF - Semaphores Processor IRQ Notification */
16208       SEMA4_CP0NTF_16B_tag CP0NTF;       /* offset: 0x0080 size: 16 bit */
16209       int8_t SEMA4_reserved_0082[6];
16210   
16211       /* SEMA4_CP1NTF - Semaphores Processor IRQ Notification */
16212       SEMA4_CP1NTF_16B_tag CP1NTF;       /* offset: 0x0088 size: 16 bit */
16213       int8_t SEMA4_reserved_008A[118];
16214   
16215       /* SEMA4_RSTGT -  Semaphores Reset Gate */
16216       SEMA4_RSTGT_16B_tag RSTGT;         /* offset: 0x0100 size: 16 bit */
16217       int8_t SEMA4_reserved_0102[2];
16218   
16219       /* SEMA4_RSTNTF - Semaphores Reset Reset IRQ Notification */
16220       SEMA4_RSTNTF_16B_tag RSTNTF;       /* offset: 0x0104 size: 16 bit */
16221       int8_t SEMA4_reserved_0106[16122];
16222     } SEMA4_tag;
16223   
16224   #define SEMA4                          (*(volatile SEMA4_tag *) 0xFFF24000UL)
16225   
16226     /****************************************************************/
16227     /*                                                              */
16228     /* Module: SWT  */
16229     /*                                                              */
16230     /****************************************************************/
16231     typedef union {                      /* SWT_CR - Control Register */
16232       vuint32_t R;
16233       struct {
16234         vuint32_t MAP0:1;                /* Master Access Protection for Master 0 */
16235         vuint32_t MAP1:1;                /* Master Access Protection for Master 1 */
16236         vuint32_t MAP2:1;                /* Master Access Protection for Master 2 */
16237         vuint32_t MAP3:1;                /* Master Access Protection for Master 3 */
16238         vuint32_t MAP4:1;                /* Master Access Protection for Master 4 */
16239         vuint32_t MAP5:1;                /* Master Access Protection for Master 5 */
16240         vuint32_t MAP6:1;                /* Master Access Protection for Master 6 */
16241         vuint32_t MAP7:1;                /* Master Access Protection for Master 7 */
16242        vuint32_t:
16243         14;
16244         vuint32_t KEY:1;                 /* Keyed Service Mode */
16245         vuint32_t RIA:1;                 /* Reset on Invalid Access */
16246         vuint32_t WND:1;                 /* Window Mode */
16247         vuint32_t ITR:1;                 /* Interrupt Then Reset */
16248         vuint32_t HLK:1;                 /* Hard Lock */
16249         vuint32_t SLK:1;                 /* Soft Lock */
16250        vuint32_t:
16251         1;
16252         vuint32_t STP:1;                 /* Stop Mode Control */
16253         vuint32_t FRZ:1;                 /* Debug Mode Control */
16254         vuint32_t WEN:1;                 /* Watchdog Enabled */
16255       } B;
16256     } SWT_CR_32B_tag;
16257   
16258     typedef union {                      /* SWT_IR - SWT Interrupt Register */
16259       vuint32_t R;
16260       struct {
16261        vuint32_t:
16262         31;
16263         vuint32_t TIF:1;                 /* Time Out Interrupt Flag */
16264       } B;
16265     } SWT_IR_32B_tag;
16266   
16267     typedef union {                      /* SWT_TO - SWT Time-Out Register */
16268       vuint32_t R;
16269       struct {
16270         vuint32_t WTO:32;                /* Watchdog Time Out Period */
16271       } B;
16272     } SWT_TO_32B_tag;
16273   
16274     typedef union {                      /* SWT_WN - SWT Window Register */
16275       vuint32_t R;
16276       struct {
16277         vuint32_t WST:32;                /* Watchdog Time Out Period */
16278       } B;
16279     } SWT_WN_32B_tag;
16280   
16281     typedef union {                      /* SWT_SR - SWT Service Register */
16282       vuint32_t R;
16283       struct {
16284        vuint32_t:
16285         16;
16286         vuint32_t WSC:16;                /* Watchdog Service Code */
16287       } B;
16288     } SWT_SR_32B_tag;
16289   
16290     typedef union {                      /* SWT_CO - SWT Counter Output Register */
16291       vuint32_t R;
16292       struct {
16293         vuint32_t CNT:32;                /* Watchdog Count */
16294       } B;
16295     } SWT_CO_32B_tag;
16296   
16297     typedef union {                      /* SWT_SK - SWT Service Key Register */
16298       vuint32_t R;
16299       struct {
16300        vuint32_t:
16301         16;
16302         vuint32_t SERVICEKEY:16;         /* Service Key */
16303       } B;
16304     } SWT_SK_32B_tag;
16305   
16306     typedef struct SWT_struct_tag {
16307       /* SWT_CR - Control Register */
16308       SWT_CR_32B_tag CR;                 /* offset: 0x0000 size: 32 bit */
16309   
16310       /* SWT_IR - SWT Interrupt Register */
16311       SWT_IR_32B_tag IR;                 /* offset: 0x0004 size: 32 bit */
16312   
16313       /* SWT_TO - SWT Time-Out Register */
16314       SWT_TO_32B_tag TO;                 /* offset: 0x0008 size: 32 bit */
16315   
16316       /* SWT_WN - SWT Window Register */
16317       SWT_WN_32B_tag WN;                 /* offset: 0x000C size: 32 bit */
16318   
16319       /* SWT_SR - SWT Service Register */
16320       SWT_SR_32B_tag SR;                 /* offset: 0x0010 size: 32 bit */
16321   
16322       /* SWT_CO - SWT Counter Output Register */
16323       SWT_CO_32B_tag CO;                 /* offset: 0x0014 size: 32 bit */
16324   
16325       /* SWT_SK - SWT Service Key Register */
16326       SWT_SK_32B_tag SK;                 /* offset: 0x0018 size: 32 bit */
16327       int8_t SWT_reserved_001C[16356];
16328     } SWT_tag;
16329   
16330   #define SWT                            (*(volatile SWT_tag *) 0xFFF38000UL)
16331   
16332     /****************************************************************/
16333     /*                                                              */
16334     /* Module: STM  */
16335     /*                                                              */
16336     /****************************************************************/
16337     typedef union {                      /* STM_CR - Control Register */
16338       vuint32_t R;
16339       struct {
16340        vuint32_t:
16341         16;
16342         vuint32_t CPS:8;                 /* Counter Prescaler */
16343        vuint32_t:
16344         6;
16345         vuint32_t FRZ:1;                 /* Freeze Control */
16346         vuint32_t TEN:1;                 /* Timer Counter Enabled */
16347       } B;
16348     } STM_CR_32B_tag;
16349   
16350     typedef union {                      /* STM_CNT - STM Count Register */
16351       vuint32_t R;
16352     } STM_CNT_32B_tag;
16353   
16354     /* Register layout for all registers CCR ... */
16355     typedef union {                      /* STM_CCRn - STM Channel Control Register */
16356       vuint32_t R;
16357       struct {
16358        vuint32_t:
16359         31;
16360         vuint32_t CEN:1;                 /* Channel Enable */
16361       } B;
16362     } STM_CCR_32B_tag;
16363   
16364     /* Register layout for all registers CIR ... */
16365     typedef union {                      /* STM_CIRn - STM Channel Interrupt Register */
16366       vuint32_t R;
16367       struct {
16368        vuint32_t:
16369         31;
16370         vuint32_t CIF:1;                 /* Channel Interrupt Flag */
16371       } B;
16372     } STM_CIR_32B_tag;
16373   
16374     /* Register layout for all registers CMP ... */
16375     typedef union {                      /* STM_CMPn - STM Channel Compare Register */
16376       vuint32_t R;
16377     } STM_CMP_32B_tag;
16378   
16379     typedef struct STM_CHANNEL_struct_tag {
16380       /* STM_CCRn - STM Channel Control Register */
16381       STM_CCR_32B_tag CCR;               /* relative offset: 0x0000 */
16382   
16383       /* STM_CIRn - STM Channel Interrupt Register */
16384       STM_CIR_32B_tag CIR;               /* relative offset: 0x0004 */
16385   
16386       /* STM_CMPn - STM Channel Compare Register */
16387       STM_CMP_32B_tag CMP;               /* relative offset: 0x0008 */
16388       int8_t STM_CHANNEL_reserved_000C[4];
16389     } STM_CHANNEL_tag;
16390   
16391     typedef struct STM_struct_tag {
16392       union {
16393         /* STM_CR - Control Register */
16394         STM_CR_32B_tag CR;               /* offset: 0x0000 size: 32 bit */
16395         STM_CR_32B_tag CR0;              /* deprecated - please avoid */
16396       };
16397   
16398       union {
16399         /* STM_CNT - STM Count Register */
16400         STM_CNT_32B_tag CNT;             /* offset: 0x0004 size: 32 bit */
16401         STM_CNT_32B_tag CNT0;            /* deprecated - please avoid */
16402       };
16403   
16404       int8_t STM_reserved_0008[8];
16405       union {
16406         /*  Register set CHANNEL */
16407         STM_CHANNEL_tag CHANNEL[4];      /* offset: 0x0010  (0x0010 x 4) */
16408         struct {
16409           /* STM_CCRn - STM Channel Control Register */
16410           STM_CCR_32B_tag CCR0;          /* offset: 0x0010 size: 32 bit */
16411   
16412           /* STM_CIRn - STM Channel Interrupt Register */
16413           STM_CIR_32B_tag CIR0;          /* offset: 0x0014 size: 32 bit */
16414   
16415           /* STM_CMPn - STM Channel Compare Register */
16416           STM_CMP_32B_tag CMP0;          /* offset: 0x0018 size: 32 bit */
16417           int8_t STM_reserved_001C_I1[4];
16418   
16419           /* STM_CCRn - STM Channel Control Register */
16420           STM_CCR_32B_tag CCR1;          /* offset: 0x0020 size: 32 bit */
16421   
16422           /* STM_CIRn - STM Channel Interrupt Register */
16423           STM_CIR_32B_tag CIR1;          /* offset: 0x0024 size: 32 bit */
16424   
16425           /* STM_CMPn - STM Channel Compare Register */
16426           STM_CMP_32B_tag CMP1;          /* offset: 0x0028 size: 32 bit */
16427           int8_t STM_reserved_002C_I1[4];
16428   
16429           /* STM_CCRn - STM Channel Control Register */
16430           STM_CCR_32B_tag CCR2;          /* offset: 0x0030 size: 32 bit */
16431   
16432           /* STM_CIRn - STM Channel Interrupt Register */
16433           STM_CIR_32B_tag CIR2;          /* offset: 0x0034 size: 32 bit */
16434   
16435           /* STM_CMPn - STM Channel Compare Register */
16436           STM_CMP_32B_tag CMP2;          /* offset: 0x0038 size: 32 bit */
16437           int8_t STM_reserved_003C_I1[4];
16438   
16439           /* STM_CCRn - STM Channel Control Register */
16440           STM_CCR_32B_tag CCR3;          /* offset: 0x0040 size: 32 bit */
16441   
16442           /* STM_CIRn - STM Channel Interrupt Register */
16443           STM_CIR_32B_tag CIR3;          /* offset: 0x0044 size: 32 bit */
16444   
16445           /* STM_CMPn - STM Channel Compare Register */
16446           STM_CMP_32B_tag CMP3;          /* offset: 0x0048 size: 32 bit */
16447           int8_t STM_reserved_004C_E1[4];
16448         };
16449       };
16450   
16451       int8_t STM_reserved_0050[16304];
16452     } STM_tag;
16453   
16454   #define STM                            (*(volatile STM_tag *) 0xFFF3C000UL)
16455   
16456     /****************************************************************/
16457     /*                                                              */
16458     /* Module: SPP_MCM  */
16459     /*                                                              */
16460     /****************************************************************/
16461     typedef union {                      /* SPP_MCM_PCT - Processor Core Type */
16462       vuint16_t R;
16463       struct {
16464         vuint16_t PCTYPE:16;             /* Processor Core Type */
16465       } B;
16466     } SPP_MCM_PCT_16B_tag;
16467   
16468     typedef union {                      /* SPP_MCM_PLREV - SOC-Defined Platform Revision */
16469       vuint16_t R;
16470       struct {
16471         vuint16_t PLREVISION:16;         /* Platform Revision */
16472       } B;
16473     } SPP_MCM_PLREV_16B_tag;
16474   
16475     typedef union {                      /* SPP_MCM_IOPMC - IPS On-Platform Module Configuration */
16476       vuint32_t R;
16477       struct {
16478         vuint32_t PMC:32;                /* IPS Module Configuration */
16479       } B;
16480     } SPP_MCM_IOPMC_32B_tag;
16481   
16482     typedef union {                      /* SPP_MCM_MRSR - Miscellaneous Reset Status Register */
16483       vuint8_t R;
16484       struct {
16485         vuint8_t POR:1;                  /* Power on Reset */
16486   
16487   #ifndef USE_FIELD_ALIASES_SPP_MCM
16488   
16489         vuint8_t OFPLR:1;                /* Off-Platform Reset */
16490   
16491   #else
16492   
16493         vuint8_t DIR:1;                  /* deprecated name - please avoid */
16494   
16495   #endif
16496   
16497        vuint8_t:
16498         6;
16499       } B;
16500     } SPP_MCM_MRSR_8B_tag;
16501   
16502     typedef union {                      /* SPP_MCM_MWCR - Miscellaneous Wakeup Control Register */
16503       vuint8_t R;
16504       struct {
16505         vuint8_t ENBWCR:1;               /* Enable WCR */
16506        vuint8_t:
16507         3;
16508         vuint8_t PRILVL:4;               /* Interrupt Priority Level */
16509       } B;
16510     } SPP_MCM_MWCR_8B_tag;
16511   
16512     typedef union {                      /* SPP_MCM_MIR - Miscellaneous Interrupt Register */
16513       vuint8_t R;
16514       struct {
16515         vuint8_t FB0AI:1;                /* Flash Bank 0 Abort Interrupt */
16516         vuint8_t FB0SI:1;                /* Flash Bank 0 Stall Interrupt */
16517         vuint8_t FB1AI:1;                /* Flash Bank 1 Abort Interrupt */
16518         vuint8_t FB1SI:1;                /* Flash Bank 1 Stall Interrupt */
16519         vuint8_t FB2AI:1;                /* Flash Bank 2 Abort Interrupt */
16520         vuint8_t FB2SI:1;                /* Flash Bank 2 Stall Interrupt */
16521        vuint8_t:
16522         2;
16523       } B;
16524     } SPP_MCM_MIR_8B_tag;
16525   
16526     typedef union {                      /* SPP_MCM_MUDCR - Miscellaneous User Defined Control Register */
16527       vuint32_t R;
16528       struct {
16529         vuint32_t MUSERDCR:32;           /* User Defined Control Register */
16530       } B;
16531     } SPP_MCM_MUDCR_32B_tag;
16532   
16533     typedef union {                      /* SPP_MCM_ECR - ECC Configuration Register */
16534       vuint8_t R;
16535       struct {
16536        vuint8_t:
16537         2;
16538   
16539   #ifndef USE_FIELD_ALIASES_SPP_MCM
16540   
16541         vuint8_t EPR1BR:1;               /* Enable Platform RAM 1-bit Reporting */
16542   
16543   #else
16544   
16545         vuint8_t ER1BR:1;                /* deprecated name - please avoid */
16546   
16547   #endif
16548   
16549   #ifndef USE_FIELD_ALIASES_SPP_MCM
16550   
16551         vuint8_t EPF1BR:1;               /* Enable Platform FLASH 1-bit Reporting */
16552   
16553   #else
16554   
16555         vuint8_t EF1BR:1;                /* deprecated name - please avoid */
16556   
16557   #endif
16558   
16559        vuint8_t:
16560         2;
16561   
16562   #ifndef USE_FIELD_ALIASES_SPP_MCM
16563   
16564         vuint8_t EPRNCR:1;               /* Enable Platform RAM Non-Correctable Reporting */
16565   
16566   #else
16567   
16568         vuint8_t ERNCR:1;                /* deprecated name - please avoid */
16569   
16570   #endif
16571   
16572   #ifndef USE_FIELD_ALIASES_SPP_MCM
16573   
16574         vuint8_t EPFNCR:1;               /* Enable Platform FLASH Non-Correctable Reporting */
16575   
16576   #else
16577   
16578         vuint8_t EFNCR:1;                /* deprecated name - please avoid */
16579   
16580   #endif
16581   
16582       } B;
16583     } SPP_MCM_ECR_8B_tag;
16584   
16585     typedef union {                      /* SPP_MCM_ESR - ECC Status Register */
16586       vuint8_t R;
16587       struct {
16588        vuint8_t:
16589         2;
16590   
16591   #ifndef USE_FIELD_ALIASES_SPP_MCM
16592   
16593         vuint8_t PR1BC:1;                /* Platform RAM 1-bit Correction */
16594   
16595   #else
16596   
16597         vuint8_t R1BC:1;                 /* deprecated name - please avoid */
16598   
16599   #endif
16600   
16601   #ifndef USE_FIELD_ALIASES_SPP_MCM
16602   
16603         vuint8_t PF1BC:1;                /* Platform FLASH 1-bit Correction */
16604   
16605   #else
16606   
16607         vuint8_t F1BC:1;                 /* deprecated name - please avoid */
16608   
16609   #endif
16610   
16611        vuint8_t:
16612         2;
16613   
16614   #ifndef USE_FIELD_ALIASES_SPP_MCM
16615   
16616         vuint8_t PRNCE:1;                /* Platform RAM Non-Correctable Error */
16617   
16618   #else
16619   
16620         vuint8_t RNCE:1;                 /* deprecated name - please avoid */
16621   
16622   #endif
16623   
16624   #ifndef USE_FIELD_ALIASES_SPP_MCM
16625   
16626         vuint8_t PFNCE:1;                /* Platform FLASH Non-Correctable Error */
16627   
16628   #else
16629   
16630         vuint8_t FNCE:1;                 /* deprecated name - please avoid */
16631   
16632   #endif
16633   
16634       } B;
16635     } SPP_MCM_ESR_8B_tag;
16636   
16637     typedef union {                      /* SPP_MCM_EEGR - ECC Error Generation Register */
16638       vuint16_t R;
16639       struct {
16640         vuint16_t FRCAP:1;               /* Force Platform RAM Error Injection Access Protection */
16641        vuint16_t:
16642         1;
16643         vuint16_t FRC1BI:1;              /* Force Platform RAM Continuous 1-Bit Data Inversions */
16644         vuint16_t FR11BI:1;              /* Force Platform RAM One 1-Bit Data Inversion */
16645        vuint16_t:
16646         2;
16647         vuint16_t FRCNCI:1;              /* Force Platform RAM Continuous Noncorrectable Data Inversions */
16648         vuint16_t FR1NCI:1;              /* Force Platform RAM One Noncorrectable Data Inversions */
16649        vuint16_t:
16650         1;
16651         vuint16_t ERRBIT:7;              /* Error Bit Position */
16652       } B;
16653     } SPP_MCM_EEGR_16B_tag;
16654   
16655     typedef union {                      /* SPP_MCM_PFEAR - Platform Flash ECC Error Address Register */
16656       vuint32_t R;
16657     } SPP_MCM_PFEAR_32B_tag;
16658   
16659     typedef union {                      /* SPP_MCM_PFEMR - Platform Flash ECC Master Number Register */
16660       vuint8_t R;
16661     } SPP_MCM_PFEMR_8B_tag;
16662   
16663     typedef union {                      /* SPP_MCM_PFEAT - Platform Flash ECC Attributes Register */
16664       vuint8_t R;
16665       struct {
16666   
16667   #ifndef USE_FIELD_ALIASES_SPP_MCM
16668   
16669         vuint8_t F_WRITE:1;              /* AMBA-AHBH Write */
16670   
16671   #else
16672   
16673         vuint8_t WRITE:1;                /* deprecated name - please avoid */
16674   
16675   #endif
16676   
16677   #ifndef USE_FIELD_ALIASES_SPP_MCM
16678   
16679         vuint8_t F_SIZE:3;               /* AMBA-AHBH Size */
16680   
16681   #else
16682   
16683         vuint8_t SIZE:3;                 /* deprecated name - please avoid */
16684   
16685   #endif
16686   
16687   #ifndef USE_FIELD_ALIASES_SPP_MCM
16688   
16689         vuint8_t F_PROTECT:4;            /* AMBA-AHBH PROT */
16690   
16691   #else
16692   
16693         vuint8_t PROTECTION:4;           /* deprecated name - please avoid */
16694   
16695   #endif
16696   
16697       } B;
16698     } SPP_MCM_PFEAT_8B_tag;
16699   
16700     typedef union {                      /* SPP_MCM_PFEDRH - Platform Flash ECC Data Register High Word */
16701       vuint32_t R;
16702     } SPP_MCM_PFEDRH_32B_tag;
16703   
16704     typedef union {                      /* SPP_MCM_PFEDR - Platform Flash ECC Data Register */
16705       vuint32_t R;
16706     } SPP_MCM_PFEDR_32B_tag;
16707   
16708     typedef union {                      /* SPP_MCM_PREAR - Platform RAM ECC Address Register */
16709       vuint32_t R;
16710     } SPP_MCM_PREAR_32B_tag;
16711   
16712     typedef union {                      /* SPP_MCM_PRESR - Platform RAM ECC Syndrome Register */
16713       vuint8_t R;
16714     } SPP_MCM_PRESR_8B_tag;
16715   
16716     typedef union {                      /* SPP_MCM_PREMR - Platform RAM ECC Master Number Register */
16717       vuint8_t R;
16718       struct {
16719        vuint8_t:
16720         4;
16721   
16722   #ifndef USE_FIELD_ALIASES_SPP_MCM
16723   
16724         vuint8_t PR_EMR:4;               /* Platform RAM ECC Master Number */
16725   
16726   #else
16727   
16728         vuint8_t REMR:4;                 /* deprecated name - please avoid */
16729   
16730   #endif
16731   
16732       } B;
16733     } SPP_MCM_PREMR_8B_tag;
16734   
16735     typedef union {                      /* SPP_MCM_PREAT - Platform RAM ECC Attributes Register */
16736       vuint8_t R;
16737       struct {
16738   
16739   #ifndef USE_FIELD_ALIASES_SPP_MCM
16740   
16741         vuint8_t R_WRITE:1;              /* AMBA-AHBH Write */
16742   
16743   #else
16744   
16745         vuint8_t WRITE:1;                /* deprecated name - please avoid */
16746   
16747   #endif
16748   
16749   #ifndef USE_FIELD_ALIASES_SPP_MCM
16750   
16751         vuint8_t R_SIZE:3;               /* AMBA-AHBH Size */
16752   
16753   #else
16754   
16755         vuint8_t SIZE:3;                 /* deprecated name - please avoid */
16756   
16757   #endif
16758   
16759   #ifndef USE_FIELD_ALIASES_SPP_MCM
16760   
16761         vuint8_t R_PROTECT:4;            /* AMBA-AHBH PROT */
16762   
16763   #else
16764   
16765         vuint8_t PROTECTION:4;           /* deprecated name - please avoid */
16766   
16767   #endif
16768   
16769       } B;
16770     } SPP_MCM_PREAT_8B_tag;
16771   
16772     typedef union {                      /* SPP_MCM_PREDR - Platform RAM ECC Data Register High Word */
16773       vuint32_t R;
16774     } SPP_MCM_PREDRH_32B_tag;
16775   
16776     typedef union {                      /* SPP_MCM_PREDR - Platform RAM ECC Data Register */
16777       vuint32_t R;
16778     } SPP_MCM_PREDR_32B_tag;
16779   
16780     typedef struct SPP_MCM_struct_tag {
16781       /* SPP_MCM_PCT - Processor Core Type */
16782       SPP_MCM_PCT_16B_tag PCT;           /* offset: 0x0000 size: 16 bit */
16783       union {
16784         /* SPP_MCM_PLREV - SOC-Defined Platform Revision */
16785         SPP_MCM_PLREV_16B_tag PLREV;     /* offset: 0x0002 size: 16 bit */
16786         SPP_MCM_PLREV_16B_tag REV;       /* deprecated - please avoid */
16787       };
16788   
16789       int8_t SPP_MCM_reserved_0004[4];
16790       union {
16791         /* SPP_MCM_IOPMC - IPS On-Platform Module Configuration */
16792         SPP_MCM_IOPMC_32B_tag IOPMC;     /* offset: 0x0008 size: 32 bit */
16793         SPP_MCM_IOPMC_32B_tag MC;        /* deprecated - please avoid */
16794       };
16795   
16796       int8_t SPP_MCM_reserved_000C[3];
16797   
16798       /* SPP_MCM_MRSR - Miscellaneous Reset Status Register */
16799       SPP_MCM_MRSR_8B_tag MRSR;          /* offset: 0x000F size: 8 bit */
16800       int8_t SPP_MCM_reserved_0010[3];
16801   
16802       /* SPP_MCM_MWCR - Miscellaneous Wakeup Control Register */
16803       SPP_MCM_MWCR_8B_tag MWCR;          /* offset: 0x0013 size: 8 bit */
16804       int8_t SPP_MCM_reserved_0014[11];
16805   
16806       /* SPP_MCM_MIR - Miscellaneous Interrupt Register */
16807       SPP_MCM_MIR_8B_tag MIR;            /* offset: 0x001F size: 8 bit */
16808       int8_t SPP_MCM_reserved_0020[4];
16809   
16810       /* SPP_MCM_MUDCR - Miscellaneous User Defined Control Register */
16811       SPP_MCM_MUDCR_32B_tag MUDCR;       /* offset: 0x0024 size: 32 bit */
16812       int8_t SPP_MCM_reserved_0028[27];
16813   
16814       /* SPP_MCM_ECR - ECC Configuration Register */
16815       SPP_MCM_ECR_8B_tag ECR;            /* offset: 0x0043 size: 8 bit */
16816       int8_t SPP_MCM_reserved_0044[3];
16817   
16818       /* SPP_MCM_ESR - ECC Status Register */
16819       SPP_MCM_ESR_8B_tag ESR;            /* offset: 0x0047 size: 8 bit */
16820       int8_t SPP_MCM_reserved_0048[2];
16821   
16822       /* SPP_MCM_EEGR - ECC Error Generation Register */
16823       SPP_MCM_EEGR_16B_tag EEGR;         /* offset: 0x004A size: 16 bit */
16824       int8_t SPP_MCM_reserved_004C[4];
16825       union {
16826         /* SPP_MCM_PFEAR - Platform Flash ECC Error Address Register */
16827         SPP_MCM_PFEAR_32B_tag PFEAR;     /* offset: 0x0050 size: 32 bit */
16828         SPP_MCM_PFEAR_32B_tag FEAR;      /* deprecated - please avoid */
16829       };
16830   
16831       int8_t SPP_MCM_reserved_0054[2];
16832       union {
16833         /* SPP_MCM_PFEMR - Platform Flash ECC Master Number Register */
16834         SPP_MCM_PFEMR_8B_tag PFEMR;      /* offset: 0x0056 size: 8 bit */
16835         SPP_MCM_PFEMR_8B_tag FEMR;       /* deprecated - please avoid */
16836       };
16837   
16838       union {
16839         /* SPP_MCM_PFEAT - Platform Flash ECC Attributes Register */
16840         SPP_MCM_PFEAT_8B_tag PFEAT;      /* offset: 0x0057 size: 8 bit */
16841         SPP_MCM_PFEAT_8B_tag FEAT;       /* deprecated - please avoid */
16842       };
16843   
16844       /* SPP_MCM_PFEDRH - Platform Flash ECC Data Register High Word */
16845       SPP_MCM_PFEDRH_32B_tag PFEDRH;     /* offset: 0x0058 size: 32 bit */
16846       union {
16847         /* SPP_MCM_PFEDR - Platform Flash ECC Data Register */
16848         SPP_MCM_PFEDR_32B_tag PFEDR;     /* offset: 0x005C size: 32 bit */
16849         SPP_MCM_PFEDR_32B_tag FEDR;      /* deprecated - please avoid */
16850       };
16851   
16852       union {
16853         /* SPP_MCM_PREAR - Platform RAM ECC Address Register */
16854         SPP_MCM_PREAR_32B_tag PREAR;     /* offset: 0x0060 size: 32 bit */
16855         SPP_MCM_PREAR_32B_tag REAR;      /* deprecated - please avoid */
16856       };
16857   
16858       int8_t SPP_MCM_reserved_0064;
16859       union {
16860         /* SPP_MCM_PRESR - Platform RAM ECC Syndrome Register */
16861         SPP_MCM_PRESR_8B_tag PRESR;      /* offset: 0x0065 size: 8 bit */
16862         SPP_MCM_PRESR_8B_tag RESR;       /* deprecated - please avoid */
16863       };
16864   
16865       union {
16866         /* SPP_MCM_PREMR - Platform RAM ECC Master Number Register */
16867         SPP_MCM_PREMR_8B_tag PREMR;      /* offset: 0x0066 size: 8 bit */
16868         SPP_MCM_PREMR_8B_tag REMR;       /* deprecated - please avoid */
16869       };
16870   
16871       union {
16872         /* SPP_MCM_PREAT - Platform RAM ECC Attributes Register */
16873         SPP_MCM_PREAT_8B_tag PREAT;      /* offset: 0x0067 size: 8 bit */
16874         SPP_MCM_PREAT_8B_tag REAT;       /* deprecated - please avoid */
16875       };
16876   
16877       /* SPP_MCM_PREDR - Platform RAM ECC Data Register High Word */
16878       SPP_MCM_PREDRH_32B_tag PREDRH;     /* offset: 0x0068 size: 32 bit */
16879       union {
16880         /* SPP_MCM_PREDR - Platform RAM ECC Data Register */
16881         SPP_MCM_PREDR_32B_tag PREDR;     /* offset: 0x006C size: 32 bit */
16882         SPP_MCM_PREDR_32B_tag REDR;      /* deprecated - please avoid */
16883       };
16884   
16885       int8_t SPP_MCM_reserved_0070[16272];
16886     } SPP_MCM_tag;
16887   
16888   #define SPP_MCM                        (*(volatile SPP_MCM_tag *) 0xFFF40000UL)
16889   
16890     /****************************************************************/
16891     /*                                                              */
16892     /* Module: SPP_DMA2  */
16893     /*                                                              */
16894     /****************************************************************/
16895     typedef union {                      /* SPP_DMA2_DMACR - DMA Control Register */
16896       vuint32_t R;
16897       struct {
16898        vuint32_t:
16899         14;
16900         vuint32_t CX:1;                  /* Cancel Transfer */
16901         vuint32_t ECX:1;                 /* Error Cancel Transfer */
16902         vuint32_t GRP3PRI:2;             /* Channel Group 3 Priority */
16903         vuint32_t GRP2PRI:2;             /* Channel Group 2 Priority */
16904         vuint32_t GRP1PRI:2;             /* Channel Group 1 Priority */
16905         vuint32_t GRP0PRI:2;             /* Channel Group 0 Priority */
16906         vuint32_t EMLM:1;                /* Enable Minor Loop Mapping */
16907         vuint32_t CLM:1;                 /* Continuous Link Mode */
16908         vuint32_t HALT:1;                /* Halt DMA Operations */
16909         vuint32_t HOE:1;                 /* Halt on Error */
16910         vuint32_t ERGA:1;                /* Enable Round Robin Group Arbitration */
16911         vuint32_t ERCA:1;                /* Enable Round Robin Channel Arbitration */
16912         vuint32_t EDBG:1;                /* Enable Debug */
16913         vuint32_t EBW:1;                 /* Enable Buffered Writes */
16914       } B;
16915     } SPP_DMA2_DMACR_32B_tag;
16916   
16917     typedef union {                      /* SPP_DMA2_DMAES - DMA Error Status Register */
16918       vuint32_t R;
16919       struct {
16920         vuint32_t VLD:1;                 /* Logical OR of DMAERRH and DMAERRL status bits */
16921        vuint32_t:
16922         14;
16923         vuint32_t ECX:1;                 /* Transfer Cancelled */
16924         vuint32_t GPE:1;                 /* Group Priority Error */
16925         vuint32_t CPE:1;                 /* Channel Priority Error */
16926         vuint32_t ERRCHN:6;              /* Error Channel Number or Cancelled Channel Number */
16927         vuint32_t SAE:1;                 /* Source Address Error */
16928         vuint32_t SOE:1;                 /* Source Offset Error */
16929         vuint32_t DAE:1;                 /* Destination Address Error */
16930         vuint32_t DOE:1;                 /* Destination Offset Error */
16931         vuint32_t NCE:1;                 /* Nbytes/Citer Configuration Error */
16932         vuint32_t SGE:1;                 /* Scatter/Gather Configuration Error */
16933         vuint32_t SBE:1;                 /* Source Bus Error */
16934         vuint32_t DBE:1;                 /* Destination Bus Error */
16935       } B;
16936     } SPP_DMA2_DMAES_32B_tag;
16937   
16938     typedef union {                      /* SPP_DMA2_DMAERQH - DMA Enable Request Register */
16939       vuint32_t R;
16940       struct {
16941         vuint32_t ERQ:32;                /* DMA Enable Request */
16942       } B;
16943     } SPP_DMA2_DMAERQH_32B_tag;
16944   
16945     typedef union {                      /* SPP_DMA2_DMAERQL - DMA Enable Request Register */
16946       vuint32_t R;
16947       struct {
16948         vuint32_t ERQ:32;                /* DMA Enable Request */
16949       } B;
16950     } SPP_DMA2_DMAERQL_32B_tag;
16951   
16952     typedef union {                      /* SPP_DMA2_DMAEEIH - DMA Enable Error Interrupt Register */
16953       vuint32_t R;
16954       struct {
16955         vuint32_t EEI:32;                /* DMA Enable Error Interrupt */
16956       } B;
16957     } SPP_DMA2_DMAEEIH_32B_tag;
16958   
16959     typedef union {                      /* SPP_DMA2_DMAEEIL - DMA Enable Error Interrupt Register */
16960       vuint32_t R;
16961       struct {
16962         vuint32_t EEI:32;                /* DMA Enable Error Interrupt */
16963       } B;
16964     } SPP_DMA2_DMAEEIL_32B_tag;
16965   
16966     typedef union {                      /* SPP_DMA2_DMASERQ - DMA Set Enable Request Register */
16967       vuint8_t R;
16968       struct {
16969        vuint8_t:
16970         1;
16971         vuint8_t SERQ:7;                 /* Set Enable Request */
16972       } B;
16973     } SPP_DMA2_DMASERQ_8B_tag;
16974   
16975     typedef union {                      /* SPP_DMA2_DMACERQ - DMA Clear Enable Request Register */
16976       vuint8_t R;
16977       struct {
16978        vuint8_t:
16979         1;
16980         vuint8_t CERQ:7;                 /* Clear Enable Request */
16981       } B;
16982     } SPP_DMA2_DMACERQ_8B_tag;
16983   
16984     typedef union {                      /* SPP_DMA2_DMASEEI - DMA Set Enable Error Interrupt Register */
16985       vuint8_t R;
16986       struct {
16987        vuint8_t:
16988         1;
16989         vuint8_t SEEI:7;                 /* Set Enable Error Interrupt */
16990       } B;
16991     } SPP_DMA2_DMASEEI_8B_tag;
16992   
16993     typedef union {                      /* SPP_DMA2_DMACEEI - DMA Clear Enable Error Interrupt Register */
16994       vuint8_t R;
16995       struct {
16996        vuint8_t:
16997         1;
16998         vuint8_t CEEI:7;                 /* Clear Enable Error Interrupt */
16999       } B;
17000     } SPP_DMA2_DMACEEI_8B_tag;
17001   
17002     typedef union {                      /* SPP_DMA2_DMACINT - DMA Clear Interrupt Request */
17003       vuint8_t R;
17004       struct {
17005        vuint8_t:
17006         1;
17007         vuint8_t CINT:7;                 /* Clear Interrupt Request */
17008       } B;
17009     } SPP_DMA2_DMACINT_8B_tag;
17010   
17011     typedef union {                      /* SPP_DMA2_DMACERR - DMA Clear Error */
17012       vuint8_t R;
17013       struct {
17014        vuint8_t:
17015         1;
17016   
17017   #ifndef USE_FIELD_ALIASES_SPP_DMA2
17018   
17019         vuint8_t CERR:7;                 /* Clear Error Indicator */
17020   
17021   #else
17022   
17023         vuint8_t CER:7;                  /* deprecated name - please avoid */
17024   
17025   #endif
17026   
17027       } B;
17028     } SPP_DMA2_DMACERR_8B_tag;
17029   
17030     typedef union {                      /* SPP_DMA2_DMASSRT - DMA Set START Bit */
17031       vuint8_t R;
17032       struct {
17033        vuint8_t:
17034         1;
17035   
17036   #ifndef USE_FIELD_ALIASES_SPP_DMA2
17037   
17038         vuint8_t SSRT:7;                 /* Set START Bit */
17039   
17040   #else
17041   
17042         vuint8_t SSB:7;                  /* deprecated name - please avoid */
17043   
17044   #endif
17045   
17046       } B;
17047     } SPP_DMA2_DMASSRT_8B_tag;
17048   
17049     typedef union {                      /* SPP_DMA2_DMACDNE - DMA Clear DONE Status */
17050       vuint8_t R;
17051       struct {
17052        vuint8_t:
17053         1;
17054   
17055   #ifndef USE_FIELD_ALIASES_SPP_DMA2
17056   
17057         vuint8_t CDNE:7;                 /* Clear DONE Status Bit */
17058   
17059   #else
17060   
17061         vuint8_t CDSB:7;                 /* deprecated name - please avoid */
17062   
17063   #endif
17064   
17065       } B;
17066     } SPP_DMA2_DMACDNE_8B_tag;
17067   
17068     typedef union {                      /* SPP_DMA2_DMAINTH - DMA Interrupt Request Register */
17069       vuint32_t R;
17070       struct {
17071         vuint32_t INT:32;                /* DMA Interrupt Request */
17072       } B;
17073     } SPP_DMA2_DMAINTH_32B_tag;
17074   
17075     typedef union {                      /* SPP_DMA2_DMAINTL - DMA Interrupt Request Register */
17076       vuint32_t R;
17077       struct {
17078         vuint32_t INT:32;                /* DMA Interrupt Request */
17079       } B;
17080     } SPP_DMA2_DMAINTL_32B_tag;
17081   
17082     typedef union {                      /* SPP_DMA2_DMAERRH - DMA Error Register */
17083       vuint32_t R;
17084       struct {
17085         vuint32_t ERR:32;                /* DMA Error n */
17086       } B;
17087     } SPP_DMA2_DMAERRH_32B_tag;
17088   
17089     typedef union {                      /* SPP_DMA2_DMAERRL - DMA Error Register */
17090       vuint32_t R;
17091       struct {
17092         vuint32_t ERR:32;                /* DMA Error n */
17093       } B;
17094     } SPP_DMA2_DMAERRL_32B_tag;
17095   
17096     typedef union {                      /* SPP_DMA2_DMAHRSH - DMA Hardware Request Status Register */
17097       vuint32_t R;
17098       struct {
17099         vuint32_t HRS:32;                /* DMA Hardware Request Status */
17100       } B;
17101     } SPP_DMA2_DMAHRSH_32B_tag;
17102   
17103     typedef union {                      /* SPP_DMA2_DMAHRSL - DMA Hardware Request Status Register */
17104       vuint32_t R;
17105       struct {
17106         vuint32_t HRS:32;                /* DMA Hardware Request Status */
17107       } B;
17108     } SPP_DMA2_DMAHRSL_32B_tag;
17109   
17110     typedef union {                      /* SPP_DMA2_DMAGPOR - DMA General Purpose Output Register */
17111       vuint32_t R;
17112       struct {
17113         vuint32_t GPOR:32;               /* DMA General Purpose Output */
17114       } B;
17115     } SPP_DMA2_DMAGPOR_32B_tag;
17116   
17117     /* Register layout for all registers DCHPRI ... */
17118     typedef union {                      /* SPP_DMA2_DCHPRIn - DMA Channel n Priority */
17119       vuint8_t R;
17120       struct {
17121         vuint8_t ECP:1;                  /* Enable Channel Preemption */
17122         vuint8_t DPA:1;                  /* Disable Preempt Ability */
17123         vuint8_t GRPPRI:2;               /* Channel n Current Group Priority */
17124         vuint8_t CHPRI:4;                /* Channel n Arbitration Priority */
17125       } B;
17126     } SPP_DMA2_DCHPRI_8B_tag;
17127   
17128     /* Register layout for all registers TCDWORD0_ ... */
17129     typedef union {                      /* SPP_DMA2_TCDn Word0 - Source Address */
17130       vuint32_t R;
17131       struct {
17132         vuint32_t SADDR:32;              /* Source Address */
17133       } B;
17134     } SPP_DMA2_TCDWORD0__32B_tag;
17135   
17136     /* Register layout for all registers TCDWORD4_ ... */
17137     typedef union {                      /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
17138       vuint32_t R;
17139       struct {
17140         vuint32_t SMOD:5;                /* Source Address Modulo */
17141         vuint32_t SSIZE:3;               /* Source Data Transfer Size */
17142         vuint32_t DMOD:5;                /* Destination Address Module */
17143         vuint32_t DSIZE:3;               /* Destination Data Transfer Size */
17144         vuint32_t SOFF:16;               /* Source Address Signed Offset */
17145       } B;
17146     } SPP_DMA2_TCDWORD4__32B_tag;
17147   
17148     /* Register layout for all registers TCDWORD8_ ... */
17149     typedef union {                      /* SPP_DMA2_TCDn Word2 - nbytes */
17150       vuint32_t R;
17151       struct {
17152         vuint32_t SMLOE:1;               /* Source Minor Loop Offset Enable */
17153         vuint32_t DMLOE:1;               /* Destination Minor Loop Offset Enable */
17154         vuint32_t MLOFF:20;              /* Minor Loop Offset */
17155         vuint32_t NBYTES:10;             /* Inner Minor byte transfer Count */
17156       } B;
17157     } SPP_DMA2_TCDWORD8__32B_tag;
17158   
17159     /* Register layout for all registers TCDWORD12_ ... */
17160     typedef union {                      /* SPP_DMA2_TCDn Word3 - slast */
17161       vuint32_t R;
17162       struct {
17163         vuint32_t SLAST:32;              /* Last Source Address Adjustment */
17164       } B;
17165     } SPP_DMA2_TCDWORD12__32B_tag;
17166   
17167     /* Register layout for all registers TCDWORD16_ ... */
17168     typedef union {                      /* SPP_DMA2_TCDn Word4 - daddr */
17169       vuint32_t R;
17170       struct {
17171         vuint32_t DADDR:32;              /* Destination Address */
17172       } B;
17173     } SPP_DMA2_TCDWORD16__32B_tag;
17174   
17175     /* Register layout for all registers TCDWORD20_ ... */
17176     typedef union {                      /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
17177       vuint32_t R;
17178       struct {
17179         vuint32_t CITER_E_LINK:1;        /* Enable Channel to channel linking on minor loop complete */
17180         vuint32_t CITER_LINKCH:6;        /* Link Channel Number */
17181         vuint32_t CITER:9;               /* Current Major Iteration Count */
17182         vuint32_t DOFF:16;               /* Destination Address Signed Offset */
17183       } B;
17184     } SPP_DMA2_TCDWORD20__32B_tag;
17185   
17186     /* Register layout for all registers TCDWORD24_ ... */
17187     typedef union {                      /* SPP_DMA2_TCDn Word6 -  dlast_sga */
17188       vuint32_t R;
17189       struct {
17190         vuint32_t DLAST_SGA:32;          /* Last destination address adjustment */
17191       } B;
17192     } SPP_DMA2_TCDWORD24__32B_tag;
17193   
17194     /* Register layout for all registers TCDWORD28_ ... */
17195     typedef union {                      /* SPP_DMA2_TCDn Word7 -  biter, etc. */
17196       vuint32_t R;
17197       struct {
17198         vuint32_t BITER_E_LINK:1;        /* beginning ("major") iteration count */
17199         vuint32_t BITER:15;              /* Enable Channel to Channel linking on minor loop complete */
17200         vuint32_t BWC:2;                 /* Bandwidth Control */
17201         vuint32_t MAJOR_LINKCH:6;        /* Link Channel Number */
17202         vuint32_t DONE:1;                /* channel done */
17203         vuint32_t ACTIVE:1;              /* Channel Active */
17204         vuint32_t MAJOR_E_LINK:1;        /* Enable Channel to Channel Linking on major loop complete */
17205         vuint32_t E_SG:1;                /* Enable Scatter/Gather Processing */
17206         vuint32_t D_REQ:1;               /* Disable Request */
17207         vuint32_t INT_HALF:1;            /* Enable an Interrupt when Major Counter is half complete */
17208         vuint32_t INT_MAJ:1;             /* Enable an Interrupt when Major Iteration count completes */
17209         vuint32_t START:1;               /* Channel Start */
17210       } B;
17211     } SPP_DMA2_TCDWORD28__32B_tag;
17212   
17213     /* Register layout for generated register(s) CPR... */
17214     typedef union {                      /*  */
17215       vuint8_t R;
17216     } SPP_DMA2_CPR_8B_tag;
17217   
17218     typedef struct SPP_DMA2_CHANNEL_struct_tag {
17219       /* SPP_DMA2_TCDn Word0 - Source Address */
17220       SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_;/* relative offset: 0x0000 */
17221   
17222       /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
17223       SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_;/* relative offset: 0x0004 */
17224   
17225       /* SPP_DMA2_TCDn Word2 - nbytes */
17226       SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_;/* relative offset: 0x0008 */
17227   
17228       /* SPP_DMA2_TCDn Word3 - slast */
17229       SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_;/* relative offset: 0x000C */
17230   
17231       /* SPP_DMA2_TCDn Word4 - daddr */
17232       SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_;/* relative offset: 0x0010 */
17233   
17234       /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
17235       SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_;/* relative offset: 0x0014 */
17236   
17237       /* SPP_DMA2_TCDn Word6 -  dlast_sga */
17238       SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_;/* relative offset: 0x0018 */
17239   
17240       /* SPP_DMA2_TCDn Word7 -  biter, etc. */
17241       SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_;/* relative offset: 0x001C */
17242     } SPP_DMA2_CHANNEL_tag;
17243   
17244     typedef struct SPP_DMA2_struct_tag {
17245       union {
17246         /* SPP_DMA2_DMACR - DMA Control Register */
17247         SPP_DMA2_DMACR_32B_tag DMACR;    /* offset: 0x0000 size: 32 bit */
17248         SPP_DMA2_DMACR_32B_tag CR;       /* deprecated - please avoid */
17249       };
17250   
17251       union {
17252         /* SPP_DMA2_DMAES - DMA Error Status Register */
17253         SPP_DMA2_DMAES_32B_tag DMAES;    /* offset: 0x0004 size: 32 bit */
17254         SPP_DMA2_DMAES_32B_tag ESR;      /* deprecated - please avoid */
17255       };
17256   
17257       /* SPP_DMA2_DMAERQH - DMA Enable Request Register */
17258       SPP_DMA2_DMAERQH_32B_tag DMAERQH;  /* offset: 0x0008 size: 32 bit */
17259   
17260       /* SPP_DMA2_DMAERQL - DMA Enable Request Register */
17261       SPP_DMA2_DMAERQL_32B_tag DMAERQL;  /* offset: 0x000C size: 32 bit */
17262   
17263       /* SPP_DMA2_DMAEEIH - DMA Enable Error Interrupt Register */
17264       SPP_DMA2_DMAEEIH_32B_tag DMAEEIH;  /* offset: 0x0010 size: 32 bit */
17265   
17266       /* SPP_DMA2_DMAEEIL - DMA Enable Error Interrupt Register */
17267       SPP_DMA2_DMAEEIL_32B_tag DMAEEIL;  /* offset: 0x0014 size: 32 bit */
17268       union {
17269         /* SPP_DMA2_DMASERQ - DMA Set Enable Request Register */
17270         SPP_DMA2_DMASERQ_8B_tag DMASERQ; /* offset: 0x0018 size: 8 bit */
17271         SPP_DMA2_DMASERQ_8B_tag SERQR;   /* deprecated - please avoid */
17272       };
17273   
17274       union {
17275         /* SPP_DMA2_DMACERQ - DMA Clear Enable Request Register */
17276         SPP_DMA2_DMACERQ_8B_tag DMACERQ; /* offset: 0x0019 size: 8 bit */
17277         SPP_DMA2_DMACERQ_8B_tag CERQR;   /* deprecated - please avoid */
17278       };
17279   
17280       union {
17281         /* SPP_DMA2_DMASEEI - DMA Set Enable Error Interrupt Register */
17282         SPP_DMA2_DMASEEI_8B_tag DMASEEI; /* offset: 0x001A size: 8 bit */
17283         SPP_DMA2_DMASEEI_8B_tag SEEIR;   /* deprecated - please avoid */
17284       };
17285   
17286       union {
17287         /* SPP_DMA2_DMACEEI - DMA Clear Enable Error Interrupt Register */
17288         SPP_DMA2_DMACEEI_8B_tag DMACEEI; /* offset: 0x001B size: 8 bit */
17289         SPP_DMA2_DMACEEI_8B_tag CEEIR;   /* deprecated - please avoid */
17290       };
17291   
17292       union {
17293         /* SPP_DMA2_DMACINT - DMA Clear Interrupt Request */
17294         SPP_DMA2_DMACINT_8B_tag DMACINT; /* offset: 0x001C size: 8 bit */
17295         SPP_DMA2_DMACINT_8B_tag CIRQR;   /* deprecated - please avoid */
17296       };
17297   
17298       union {
17299         /* SPP_DMA2_DMACERR - DMA Clear Error */
17300         SPP_DMA2_DMACERR_8B_tag DMACERR; /* offset: 0x001D size: 8 bit */
17301         SPP_DMA2_DMACERR_8B_tag CERR;    /* deprecated - please avoid */
17302       };
17303   
17304       union {
17305         /* SPP_DMA2_DMASSRT - DMA Set START Bit */
17306         SPP_DMA2_DMASSRT_8B_tag DMASSRT; /* offset: 0x001E size: 8 bit */
17307         SPP_DMA2_DMASSRT_8B_tag SSBR;    /* deprecated - please avoid */
17308       };
17309   
17310       union {
17311         /* SPP_DMA2_DMACDNE - DMA Clear DONE Status */
17312         SPP_DMA2_DMACDNE_8B_tag DMACDNE; /* offset: 0x001F size: 8 bit */
17313         SPP_DMA2_DMACDNE_8B_tag CDSBR;   /* deprecated - please avoid */
17314       };
17315   
17316       /* SPP_DMA2_DMAINTH - DMA Interrupt Request Register */
17317       SPP_DMA2_DMAINTH_32B_tag DMAINTH;  /* offset: 0x0020 size: 32 bit */
17318   
17319       /* SPP_DMA2_DMAINTL - DMA Interrupt Request Register */
17320       SPP_DMA2_DMAINTL_32B_tag DMAINTL;  /* offset: 0x0024 size: 32 bit */
17321   
17322       /* SPP_DMA2_DMAERRH - DMA Error Register */
17323       SPP_DMA2_DMAERRH_32B_tag DMAERRH;  /* offset: 0x0028 size: 32 bit */
17324   
17325       /* SPP_DMA2_DMAERRL - DMA Error Register */
17326       SPP_DMA2_DMAERRL_32B_tag DMAERRL;  /* offset: 0x002C size: 32 bit */
17327   
17328       /* SPP_DMA2_DMAHRSH - DMA Hardware Request Status Register */
17329       SPP_DMA2_DMAHRSH_32B_tag DMAHRSH;  /* offset: 0x0030 size: 32 bit */
17330   
17331       /* SPP_DMA2_DMAHRSL - DMA Hardware Request Status Register */
17332       SPP_DMA2_DMAHRSL_32B_tag DMAHRSL;  /* offset: 0x0034 size: 32 bit */
17333   
17334       /* SPP_DMA2_DMAGPOR - DMA General Purpose Output Register */
17335       SPP_DMA2_DMAGPOR_32B_tag DMAGPOR;  /* offset: 0x0038 size: 32 bit */
17336       int8_t SPP_DMA2_reserved_003C[196];
17337       union {
17338         struct {
17339           SPP_DMA2_CPR_8B_tag CPR[16];   /* offset: 0x0100  (0x0001 x 16) */
17340           int8_t SPP_DMA2_reserved_0110_E0[48];
17341         };
17342   
17343         /* SPP_DMA2_DCHPRIn - DMA Channel n Priority */
17344         SPP_DMA2_DCHPRI_8B_tag DCHPRI[64];/* offset: 0x0100  (0x0001 x 64) */
17345         struct {
17346           /* SPP_DMA2_DCHPRIn - DMA Channel n Priority */
17347           SPP_DMA2_DCHPRI_8B_tag DCHPRI0;/* offset: 0x0100 size: 8 bit */
17348           SPP_DMA2_DCHPRI_8B_tag DCHPRI1;/* offset: 0x0101 size: 8 bit */
17349           SPP_DMA2_DCHPRI_8B_tag DCHPRI2;/* offset: 0x0102 size: 8 bit */
17350           SPP_DMA2_DCHPRI_8B_tag DCHPRI3;/* offset: 0x0103 size: 8 bit */
17351           SPP_DMA2_DCHPRI_8B_tag DCHPRI4;/* offset: 0x0104 size: 8 bit */
17352           SPP_DMA2_DCHPRI_8B_tag DCHPRI5;/* offset: 0x0105 size: 8 bit */
17353           SPP_DMA2_DCHPRI_8B_tag DCHPRI6;/* offset: 0x0106 size: 8 bit */
17354           SPP_DMA2_DCHPRI_8B_tag DCHPRI7;/* offset: 0x0107 size: 8 bit */
17355           SPP_DMA2_DCHPRI_8B_tag DCHPRI8;/* offset: 0x0108 size: 8 bit */
17356           SPP_DMA2_DCHPRI_8B_tag DCHPRI9;/* offset: 0x0109 size: 8 bit */
17357           SPP_DMA2_DCHPRI_8B_tag DCHPRI10;/* offset: 0x010A size: 8 bit */
17358           SPP_DMA2_DCHPRI_8B_tag DCHPRI11;/* offset: 0x010B size: 8 bit */
17359           SPP_DMA2_DCHPRI_8B_tag DCHPRI12;/* offset: 0x010C size: 8 bit */
17360           SPP_DMA2_DCHPRI_8B_tag DCHPRI13;/* offset: 0x010D size: 8 bit */
17361           SPP_DMA2_DCHPRI_8B_tag DCHPRI14;/* offset: 0x010E size: 8 bit */
17362           SPP_DMA2_DCHPRI_8B_tag DCHPRI15;/* offset: 0x010F size: 8 bit */
17363           SPP_DMA2_DCHPRI_8B_tag DCHPRI16;/* offset: 0x0110 size: 8 bit */
17364           SPP_DMA2_DCHPRI_8B_tag DCHPRI17;/* offset: 0x0111 size: 8 bit */
17365           SPP_DMA2_DCHPRI_8B_tag DCHPRI18;/* offset: 0x0112 size: 8 bit */
17366           SPP_DMA2_DCHPRI_8B_tag DCHPRI19;/* offset: 0x0113 size: 8 bit */
17367           SPP_DMA2_DCHPRI_8B_tag DCHPRI20;/* offset: 0x0114 size: 8 bit */
17368           SPP_DMA2_DCHPRI_8B_tag DCHPRI21;/* offset: 0x0115 size: 8 bit */
17369           SPP_DMA2_DCHPRI_8B_tag DCHPRI22;/* offset: 0x0116 size: 8 bit */
17370           SPP_DMA2_DCHPRI_8B_tag DCHPRI23;/* offset: 0x0117 size: 8 bit */
17371           SPP_DMA2_DCHPRI_8B_tag DCHPRI24;/* offset: 0x0118 size: 8 bit */
17372           SPP_DMA2_DCHPRI_8B_tag DCHPRI25;/* offset: 0x0119 size: 8 bit */
17373           SPP_DMA2_DCHPRI_8B_tag DCHPRI26;/* offset: 0x011A size: 8 bit */
17374           SPP_DMA2_DCHPRI_8B_tag DCHPRI27;/* offset: 0x011B size: 8 bit */
17375           SPP_DMA2_DCHPRI_8B_tag DCHPRI28;/* offset: 0x011C size: 8 bit */
17376           SPP_DMA2_DCHPRI_8B_tag DCHPRI29;/* offset: 0x011D size: 8 bit */
17377           SPP_DMA2_DCHPRI_8B_tag DCHPRI30;/* offset: 0x011E size: 8 bit */
17378           SPP_DMA2_DCHPRI_8B_tag DCHPRI31;/* offset: 0x011F size: 8 bit */
17379           SPP_DMA2_DCHPRI_8B_tag DCHPRI32;/* offset: 0x0120 size: 8 bit */
17380           SPP_DMA2_DCHPRI_8B_tag DCHPRI33;/* offset: 0x0121 size: 8 bit */
17381           SPP_DMA2_DCHPRI_8B_tag DCHPRI34;/* offset: 0x0122 size: 8 bit */
17382           SPP_DMA2_DCHPRI_8B_tag DCHPRI35;/* offset: 0x0123 size: 8 bit */
17383           SPP_DMA2_DCHPRI_8B_tag DCHPRI36;/* offset: 0x0124 size: 8 bit */
17384           SPP_DMA2_DCHPRI_8B_tag DCHPRI37;/* offset: 0x0125 size: 8 bit */
17385           SPP_DMA2_DCHPRI_8B_tag DCHPRI38;/* offset: 0x0126 size: 8 bit */
17386           SPP_DMA2_DCHPRI_8B_tag DCHPRI39;/* offset: 0x0127 size: 8 bit */
17387           SPP_DMA2_DCHPRI_8B_tag DCHPRI40;/* offset: 0x0128 size: 8 bit */
17388           SPP_DMA2_DCHPRI_8B_tag DCHPRI41;/* offset: 0x0129 size: 8 bit */
17389           SPP_DMA2_DCHPRI_8B_tag DCHPRI42;/* offset: 0x012A size: 8 bit */
17390           SPP_DMA2_DCHPRI_8B_tag DCHPRI43;/* offset: 0x012B size: 8 bit */
17391           SPP_DMA2_DCHPRI_8B_tag DCHPRI44;/* offset: 0x012C size: 8 bit */
17392           SPP_DMA2_DCHPRI_8B_tag DCHPRI45;/* offset: 0x012D size: 8 bit */
17393           SPP_DMA2_DCHPRI_8B_tag DCHPRI46;/* offset: 0x012E size: 8 bit */
17394           SPP_DMA2_DCHPRI_8B_tag DCHPRI47;/* offset: 0x012F size: 8 bit */
17395           SPP_DMA2_DCHPRI_8B_tag DCHPRI48;/* offset: 0x0130 size: 8 bit */
17396           SPP_DMA2_DCHPRI_8B_tag DCHPRI49;/* offset: 0x0131 size: 8 bit */
17397           SPP_DMA2_DCHPRI_8B_tag DCHPRI50;/* offset: 0x0132 size: 8 bit */
17398           SPP_DMA2_DCHPRI_8B_tag DCHPRI51;/* offset: 0x0133 size: 8 bit */
17399           SPP_DMA2_DCHPRI_8B_tag DCHPRI52;/* offset: 0x0134 size: 8 bit */
17400           SPP_DMA2_DCHPRI_8B_tag DCHPRI53;/* offset: 0x0135 size: 8 bit */
17401           SPP_DMA2_DCHPRI_8B_tag DCHPRI54;/* offset: 0x0136 size: 8 bit */
17402           SPP_DMA2_DCHPRI_8B_tag DCHPRI55;/* offset: 0x0137 size: 8 bit */
17403           SPP_DMA2_DCHPRI_8B_tag DCHPRI56;/* offset: 0x0138 size: 8 bit */
17404           SPP_DMA2_DCHPRI_8B_tag DCHPRI57;/* offset: 0x0139 size: 8 bit */
17405           SPP_DMA2_DCHPRI_8B_tag DCHPRI58;/* offset: 0x013A size: 8 bit */
17406           SPP_DMA2_DCHPRI_8B_tag DCHPRI59;/* offset: 0x013B size: 8 bit */
17407           SPP_DMA2_DCHPRI_8B_tag DCHPRI60;/* offset: 0x013C size: 8 bit */
17408           SPP_DMA2_DCHPRI_8B_tag DCHPRI61;/* offset: 0x013D size: 8 bit */
17409           SPP_DMA2_DCHPRI_8B_tag DCHPRI62;/* offset: 0x013E size: 8 bit */
17410           SPP_DMA2_DCHPRI_8B_tag DCHPRI63;/* offset: 0x013F size: 8 bit */
17411         };
17412       };
17413   
17414       int8_t SPP_DMA2_reserved_0140[3776];
17415       union {
17416         /*  Register set CHANNEL */
17417         SPP_DMA2_CHANNEL_tag CHANNEL[64];/* offset: 0x1000  (0x0020 x 64) */
17418         struct {
17419           /* SPP_DMA2_TCDn Word0 - Source Address */
17420           SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_0;/* offset: 0x1000 size: 32 bit */
17421   
17422           /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
17423           SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_0;/* offset: 0x1004 size: 32 bit */
17424   
17425           /* SPP_DMA2_TCDn Word2 - nbytes */
17426           SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_0;/* offset: 0x1008 size: 32 bit */
17427   
17428           /* SPP_DMA2_TCDn Word3 - slast */
17429           SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_0;/* offset: 0x100C size: 32 bit */
17430   
17431           /* SPP_DMA2_TCDn Word4 - daddr */
17432           SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_0;/* offset: 0x1010 size: 32 bit */
17433   
17434           /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
17435           SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_0;/* offset: 0x1014 size: 32 bit */
17436   
17437           /* SPP_DMA2_TCDn Word6 -  dlast_sga */
17438           SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_0;/* offset: 0x1018 size: 32 bit */
17439   
17440           /* SPP_DMA2_TCDn Word7 -  biter, etc. */
17441           SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_0;/* offset: 0x101C size: 32 bit */
17442   
17443           /* SPP_DMA2_TCDn Word0 - Source Address */
17444           SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_1;/* offset: 0x1020 size: 32 bit */
17445   
17446           /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
17447           SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_1;/* offset: 0x1024 size: 32 bit */
17448   
17449           /* SPP_DMA2_TCDn Word2 - nbytes */
17450           SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_1;/* offset: 0x1028 size: 32 bit */
17451   
17452           /* SPP_DMA2_TCDn Word3 - slast */
17453           SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_1;/* offset: 0x102C size: 32 bit */
17454   
17455           /* SPP_DMA2_TCDn Word4 - daddr */
17456           SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_1;/* offset: 0x1030 size: 32 bit */
17457   
17458           /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
17459           SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_1;/* offset: 0x1034 size: 32 bit */
17460   
17461           /* SPP_DMA2_TCDn Word6 -  dlast_sga */
17462           SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_1;/* offset: 0x1038 size: 32 bit */
17463   
17464           /* SPP_DMA2_TCDn Word7 -  biter, etc. */
17465           SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_1;/* offset: 0x103C size: 32 bit */
17466   
17467           /* SPP_DMA2_TCDn Word0 - Source Address */
17468           SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_2;/* offset: 0x1040 size: 32 bit */
17469   
17470           /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
17471           SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_2;/* offset: 0x1044 size: 32 bit */
17472   
17473           /* SPP_DMA2_TCDn Word2 - nbytes */
17474           SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_2;/* offset: 0x1048 size: 32 bit */
17475   
17476           /* SPP_DMA2_TCDn Word3 - slast */
17477           SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_2;/* offset: 0x104C size: 32 bit */
17478   
17479           /* SPP_DMA2_TCDn Word4 - daddr */
17480           SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_2;/* offset: 0x1050 size: 32 bit */
17481   
17482           /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
17483           SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_2;/* offset: 0x1054 size: 32 bit */
17484   
17485           /* SPP_DMA2_TCDn Word6 -  dlast_sga */
17486           SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_2;/* offset: 0x1058 size: 32 bit */
17487   
17488           /* SPP_DMA2_TCDn Word7 -  biter, etc. */
17489           SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_2;/* offset: 0x105C size: 32 bit */
17490   
17491           /* SPP_DMA2_TCDn Word0 - Source Address */
17492           SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_3;/* offset: 0x1060 size: 32 bit */
17493   
17494           /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
17495           SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_3;/* offset: 0x1064 size: 32 bit */
17496   
17497           /* SPP_DMA2_TCDn Word2 - nbytes */
17498           SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_3;/* offset: 0x1068 size: 32 bit */
17499   
17500           /* SPP_DMA2_TCDn Word3 - slast */
17501           SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_3;/* offset: 0x106C size: 32 bit */
17502   
17503           /* SPP_DMA2_TCDn Word4 - daddr */
17504           SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_3;/* offset: 0x1070 size: 32 bit */
17505   
17506           /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
17507           SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_3;/* offset: 0x1074 size: 32 bit */
17508   
17509           /* SPP_DMA2_TCDn Word6 -  dlast_sga */
17510           SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_3;/* offset: 0x1078 size: 32 bit */
17511   
17512           /* SPP_DMA2_TCDn Word7 -  biter, etc. */
17513           SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_3;/* offset: 0x107C size: 32 bit */
17514   
17515           /* SPP_DMA2_TCDn Word0 - Source Address */
17516           SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_4;/* offset: 0x1080 size: 32 bit */
17517   
17518           /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
17519           SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_4;/* offset: 0x1084 size: 32 bit */
17520   
17521           /* SPP_DMA2_TCDn Word2 - nbytes */
17522           SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_4;/* offset: 0x1088 size: 32 bit */
17523   
17524           /* SPP_DMA2_TCDn Word3 - slast */
17525           SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_4;/* offset: 0x108C size: 32 bit */
17526   
17527           /* SPP_DMA2_TCDn Word4 - daddr */
17528           SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_4;/* offset: 0x1090 size: 32 bit */
17529   
17530           /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
17531           SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_4;/* offset: 0x1094 size: 32 bit */
17532   
17533           /* SPP_DMA2_TCDn Word6 -  dlast_sga */
17534           SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_4;/* offset: 0x1098 size: 32 bit */
17535   
17536           /* SPP_DMA2_TCDn Word7 -  biter, etc. */
17537           SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_4;/* offset: 0x109C size: 32 bit */
17538   
17539           /* SPP_DMA2_TCDn Word0 - Source Address */
17540           SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_5;/* offset: 0x10A0 size: 32 bit */
17541   
17542           /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
17543           SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_5;/* offset: 0x10A4 size: 32 bit */
17544   
17545           /* SPP_DMA2_TCDn Word2 - nbytes */
17546           SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_5;/* offset: 0x10A8 size: 32 bit */
17547   
17548           /* SPP_DMA2_TCDn Word3 - slast */
17549           SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_5;/* offset: 0x10AC size: 32 bit */
17550   
17551           /* SPP_DMA2_TCDn Word4 - daddr */
17552           SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_5;/* offset: 0x10B0 size: 32 bit */
17553   
17554           /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
17555           SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_5;/* offset: 0x10B4 size: 32 bit */
17556   
17557           /* SPP_DMA2_TCDn Word6 -  dlast_sga */
17558           SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_5;/* offset: 0x10B8 size: 32 bit */
17559   
17560           /* SPP_DMA2_TCDn Word7 -  biter, etc. */
17561           SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_5;/* offset: 0x10BC size: 32 bit */
17562   
17563           /* SPP_DMA2_TCDn Word0 - Source Address */
17564           SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_6;/* offset: 0x10C0 size: 32 bit */
17565   
17566           /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
17567           SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_6;/* offset: 0x10C4 size: 32 bit */
17568   
17569           /* SPP_DMA2_TCDn Word2 - nbytes */
17570           SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_6;/* offset: 0x10C8 size: 32 bit */
17571   
17572           /* SPP_DMA2_TCDn Word3 - slast */
17573           SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_6;/* offset: 0x10CC size: 32 bit */
17574   
17575           /* SPP_DMA2_TCDn Word4 - daddr */
17576           SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_6;/* offset: 0x10D0 size: 32 bit */
17577   
17578           /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
17579           SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_6;/* offset: 0x10D4 size: 32 bit */
17580   
17581           /* SPP_DMA2_TCDn Word6 -  dlast_sga */
17582           SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_6;/* offset: 0x10D8 size: 32 bit */
17583   
17584           /* SPP_DMA2_TCDn Word7 -  biter, etc. */
17585           SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_6;/* offset: 0x10DC size: 32 bit */
17586   
17587           /* SPP_DMA2_TCDn Word0 - Source Address */
17588           SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_7;/* offset: 0x10E0 size: 32 bit */
17589   
17590           /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
17591           SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_7;/* offset: 0x10E4 size: 32 bit */
17592   
17593           /* SPP_DMA2_TCDn Word2 - nbytes */
17594           SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_7;/* offset: 0x10E8 size: 32 bit */
17595   
17596           /* SPP_DMA2_TCDn Word3 - slast */
17597           SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_7;/* offset: 0x10EC size: 32 bit */
17598   
17599           /* SPP_DMA2_TCDn Word4 - daddr */
17600           SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_7;/* offset: 0x10F0 size: 32 bit */
17601   
17602           /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
17603           SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_7;/* offset: 0x10F4 size: 32 bit */
17604   
17605           /* SPP_DMA2_TCDn Word6 -  dlast_sga */
17606           SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_7;/* offset: 0x10F8 size: 32 bit */
17607   
17608           /* SPP_DMA2_TCDn Word7 -  biter, etc. */
17609           SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_7;/* offset: 0x10FC size: 32 bit */
17610   
17611           /* SPP_DMA2_TCDn Word0 - Source Address */
17612           SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_8;/* offset: 0x1100 size: 32 bit */
17613   
17614           /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
17615           SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_8;/* offset: 0x1104 size: 32 bit */
17616   
17617           /* SPP_DMA2_TCDn Word2 - nbytes */
17618           SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_8;/* offset: 0x1108 size: 32 bit */
17619   
17620           /* SPP_DMA2_TCDn Word3 - slast */
17621           SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_8;/* offset: 0x110C size: 32 bit */
17622   
17623           /* SPP_DMA2_TCDn Word4 - daddr */
17624           SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_8;/* offset: 0x1110 size: 32 bit */
17625   
17626           /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
17627           SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_8;/* offset: 0x1114 size: 32 bit */
17628   
17629           /* SPP_DMA2_TCDn Word6 -  dlast_sga */
17630           SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_8;/* offset: 0x1118 size: 32 bit */
17631   
17632           /* SPP_DMA2_TCDn Word7 -  biter, etc. */
17633           SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_8;/* offset: 0x111C size: 32 bit */
17634   
17635           /* SPP_DMA2_TCDn Word0 - Source Address */
17636           SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_9;/* offset: 0x1120 size: 32 bit */
17637   
17638           /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
17639           SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_9;/* offset: 0x1124 size: 32 bit */
17640   
17641           /* SPP_DMA2_TCDn Word2 - nbytes */
17642           SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_9;/* offset: 0x1128 size: 32 bit */
17643   
17644           /* SPP_DMA2_TCDn Word3 - slast */
17645           SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_9;/* offset: 0x112C size: 32 bit */
17646   
17647           /* SPP_DMA2_TCDn Word4 - daddr */
17648           SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_9;/* offset: 0x1130 size: 32 bit */
17649   
17650           /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
17651           SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_9;/* offset: 0x1134 size: 32 bit */
17652   
17653           /* SPP_DMA2_TCDn Word6 -  dlast_sga */
17654           SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_9;/* offset: 0x1138 size: 32 bit */
17655   
17656           /* SPP_DMA2_TCDn Word7 -  biter, etc. */
17657           SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_9;/* offset: 0x113C size: 32 bit */
17658   
17659           /* SPP_DMA2_TCDn Word0 - Source Address */
17660           SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_10;/* offset: 0x1140 size: 32 bit */
17661   
17662           /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
17663           SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_10;/* offset: 0x1144 size: 32 bit */
17664   
17665           /* SPP_DMA2_TCDn Word2 - nbytes */
17666           SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_10;/* offset: 0x1148 size: 32 bit */
17667   
17668           /* SPP_DMA2_TCDn Word3 - slast */
17669           SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_10;/* offset: 0x114C size: 32 bit */
17670   
17671           /* SPP_DMA2_TCDn Word4 - daddr */
17672           SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_10;/* offset: 0x1150 size: 32 bit */
17673   
17674           /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
17675           SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_10;/* offset: 0x1154 size: 32 bit */
17676   
17677           /* SPP_DMA2_TCDn Word6 -  dlast_sga */
17678           SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_10;/* offset: 0x1158 size: 32 bit */
17679   
17680           /* SPP_DMA2_TCDn Word7 -  biter, etc. */
17681           SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_10;/* offset: 0x115C size: 32 bit */
17682   
17683           /* SPP_DMA2_TCDn Word0 - Source Address */
17684           SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_11;/* offset: 0x1160 size: 32 bit */
17685   
17686           /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
17687           SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_11;/* offset: 0x1164 size: 32 bit */
17688   
17689           /* SPP_DMA2_TCDn Word2 - nbytes */
17690           SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_11;/* offset: 0x1168 size: 32 bit */
17691   
17692           /* SPP_DMA2_TCDn Word3 - slast */
17693           SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_11;/* offset: 0x116C size: 32 bit */
17694   
17695           /* SPP_DMA2_TCDn Word4 - daddr */
17696           SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_11;/* offset: 0x1170 size: 32 bit */
17697   
17698           /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
17699           SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_11;/* offset: 0x1174 size: 32 bit */
17700   
17701           /* SPP_DMA2_TCDn Word6 -  dlast_sga */
17702           SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_11;/* offset: 0x1178 size: 32 bit */
17703   
17704           /* SPP_DMA2_TCDn Word7 -  biter, etc. */
17705           SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_11;/* offset: 0x117C size: 32 bit */
17706   
17707           /* SPP_DMA2_TCDn Word0 - Source Address */
17708           SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_12;/* offset: 0x1180 size: 32 bit */
17709   
17710           /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
17711           SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_12;/* offset: 0x1184 size: 32 bit */
17712   
17713           /* SPP_DMA2_TCDn Word2 - nbytes */
17714           SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_12;/* offset: 0x1188 size: 32 bit */
17715   
17716           /* SPP_DMA2_TCDn Word3 - slast */
17717           SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_12;/* offset: 0x118C size: 32 bit */
17718   
17719           /* SPP_DMA2_TCDn Word4 - daddr */
17720           SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_12;/* offset: 0x1190 size: 32 bit */
17721   
17722           /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
17723           SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_12;/* offset: 0x1194 size: 32 bit */
17724   
17725           /* SPP_DMA2_TCDn Word6 -  dlast_sga */
17726           SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_12;/* offset: 0x1198 size: 32 bit */
17727   
17728           /* SPP_DMA2_TCDn Word7 -  biter, etc. */
17729           SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_12;/* offset: 0x119C size: 32 bit */
17730   
17731           /* SPP_DMA2_TCDn Word0 - Source Address */
17732           SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_13;/* offset: 0x11A0 size: 32 bit */
17733   
17734           /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
17735           SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_13;/* offset: 0x11A4 size: 32 bit */
17736   
17737           /* SPP_DMA2_TCDn Word2 - nbytes */
17738           SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_13;/* offset: 0x11A8 size: 32 bit */
17739   
17740           /* SPP_DMA2_TCDn Word3 - slast */
17741           SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_13;/* offset: 0x11AC size: 32 bit */
17742   
17743           /* SPP_DMA2_TCDn Word4 - daddr */
17744           SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_13;/* offset: 0x11B0 size: 32 bit */
17745   
17746           /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
17747           SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_13;/* offset: 0x11B4 size: 32 bit */
17748   
17749           /* SPP_DMA2_TCDn Word6 -  dlast_sga */
17750           SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_13;/* offset: 0x11B8 size: 32 bit */
17751   
17752           /* SPP_DMA2_TCDn Word7 -  biter, etc. */
17753           SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_13;/* offset: 0x11BC size: 32 bit */
17754   
17755           /* SPP_DMA2_TCDn Word0 - Source Address */
17756           SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_14;/* offset: 0x11C0 size: 32 bit */
17757   
17758           /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
17759           SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_14;/* offset: 0x11C4 size: 32 bit */
17760   
17761           /* SPP_DMA2_TCDn Word2 - nbytes */
17762           SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_14;/* offset: 0x11C8 size: 32 bit */
17763   
17764           /* SPP_DMA2_TCDn Word3 - slast */
17765           SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_14;/* offset: 0x11CC size: 32 bit */
17766   
17767           /* SPP_DMA2_TCDn Word4 - daddr */
17768           SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_14;/* offset: 0x11D0 size: 32 bit */
17769   
17770           /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
17771           SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_14;/* offset: 0x11D4 size: 32 bit */
17772   
17773           /* SPP_DMA2_TCDn Word6 -  dlast_sga */
17774           SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_14;/* offset: 0x11D8 size: 32 bit */
17775   
17776           /* SPP_DMA2_TCDn Word7 -  biter, etc. */
17777           SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_14;/* offset: 0x11DC size: 32 bit */
17778   
17779           /* SPP_DMA2_TCDn Word0 - Source Address */
17780           SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_15;/* offset: 0x11E0 size: 32 bit */
17781   
17782           /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
17783           SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_15;/* offset: 0x11E4 size: 32 bit */
17784   
17785           /* SPP_DMA2_TCDn Word2 - nbytes */
17786           SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_15;/* offset: 0x11E8 size: 32 bit */
17787   
17788           /* SPP_DMA2_TCDn Word3 - slast */
17789           SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_15;/* offset: 0x11EC size: 32 bit */
17790   
17791           /* SPP_DMA2_TCDn Word4 - daddr */
17792           SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_15;/* offset: 0x11F0 size: 32 bit */
17793   
17794           /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
17795           SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_15;/* offset: 0x11F4 size: 32 bit */
17796   
17797           /* SPP_DMA2_TCDn Word6 -  dlast_sga */
17798           SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_15;/* offset: 0x11F8 size: 32 bit */
17799   
17800           /* SPP_DMA2_TCDn Word7 -  biter, etc. */
17801           SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_15;/* offset: 0x11FC size: 32 bit */
17802   
17803           /* SPP_DMA2_TCDn Word0 - Source Address */
17804           SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_16;/* offset: 0x1200 size: 32 bit */
17805   
17806           /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
17807           SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_16;/* offset: 0x1204 size: 32 bit */
17808   
17809           /* SPP_DMA2_TCDn Word2 - nbytes */
17810           SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_16;/* offset: 0x1208 size: 32 bit */
17811   
17812           /* SPP_DMA2_TCDn Word3 - slast */
17813           SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_16;/* offset: 0x120C size: 32 bit */
17814   
17815           /* SPP_DMA2_TCDn Word4 - daddr */
17816           SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_16;/* offset: 0x1210 size: 32 bit */
17817   
17818           /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
17819           SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_16;/* offset: 0x1214 size: 32 bit */
17820   
17821           /* SPP_DMA2_TCDn Word6 -  dlast_sga */
17822           SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_16;/* offset: 0x1218 size: 32 bit */
17823   
17824           /* SPP_DMA2_TCDn Word7 -  biter, etc. */
17825           SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_16;/* offset: 0x121C size: 32 bit */
17826   
17827           /* SPP_DMA2_TCDn Word0 - Source Address */
17828           SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_17;/* offset: 0x1220 size: 32 bit */
17829   
17830           /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
17831           SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_17;/* offset: 0x1224 size: 32 bit */
17832   
17833           /* SPP_DMA2_TCDn Word2 - nbytes */
17834           SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_17;/* offset: 0x1228 size: 32 bit */
17835   
17836           /* SPP_DMA2_TCDn Word3 - slast */
17837           SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_17;/* offset: 0x122C size: 32 bit */
17838   
17839           /* SPP_DMA2_TCDn Word4 - daddr */
17840           SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_17;/* offset: 0x1230 size: 32 bit */
17841   
17842           /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
17843           SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_17;/* offset: 0x1234 size: 32 bit */
17844   
17845           /* SPP_DMA2_TCDn Word6 -  dlast_sga */
17846           SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_17;/* offset: 0x1238 size: 32 bit */
17847   
17848           /* SPP_DMA2_TCDn Word7 -  biter, etc. */
17849           SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_17;/* offset: 0x123C size: 32 bit */
17850   
17851           /* SPP_DMA2_TCDn Word0 - Source Address */
17852           SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_18;/* offset: 0x1240 size: 32 bit */
17853   
17854           /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
17855           SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_18;/* offset: 0x1244 size: 32 bit */
17856   
17857           /* SPP_DMA2_TCDn Word2 - nbytes */
17858           SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_18;/* offset: 0x1248 size: 32 bit */
17859   
17860           /* SPP_DMA2_TCDn Word3 - slast */
17861           SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_18;/* offset: 0x124C size: 32 bit */
17862   
17863           /* SPP_DMA2_TCDn Word4 - daddr */
17864           SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_18;/* offset: 0x1250 size: 32 bit */
17865   
17866           /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
17867           SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_18;/* offset: 0x1254 size: 32 bit */
17868   
17869           /* SPP_DMA2_TCDn Word6 -  dlast_sga */
17870           SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_18;/* offset: 0x1258 size: 32 bit */
17871   
17872           /* SPP_DMA2_TCDn Word7 -  biter, etc. */
17873           SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_18;/* offset: 0x125C size: 32 bit */
17874   
17875           /* SPP_DMA2_TCDn Word0 - Source Address */
17876           SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_19;/* offset: 0x1260 size: 32 bit */
17877   
17878           /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
17879           SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_19;/* offset: 0x1264 size: 32 bit */
17880   
17881           /* SPP_DMA2_TCDn Word2 - nbytes */
17882           SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_19;/* offset: 0x1268 size: 32 bit */
17883   
17884           /* SPP_DMA2_TCDn Word3 - slast */
17885           SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_19;/* offset: 0x126C size: 32 bit */
17886   
17887           /* SPP_DMA2_TCDn Word4 - daddr */
17888           SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_19;/* offset: 0x1270 size: 32 bit */
17889   
17890           /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
17891           SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_19;/* offset: 0x1274 size: 32 bit */
17892   
17893           /* SPP_DMA2_TCDn Word6 -  dlast_sga */
17894           SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_19;/* offset: 0x1278 size: 32 bit */
17895   
17896           /* SPP_DMA2_TCDn Word7 -  biter, etc. */
17897           SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_19;/* offset: 0x127C size: 32 bit */
17898   
17899           /* SPP_DMA2_TCDn Word0 - Source Address */
17900           SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_20;/* offset: 0x1280 size: 32 bit */
17901   
17902           /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
17903           SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_20;/* offset: 0x1284 size: 32 bit */
17904   
17905           /* SPP_DMA2_TCDn Word2 - nbytes */
17906           SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_20;/* offset: 0x1288 size: 32 bit */
17907   
17908           /* SPP_DMA2_TCDn Word3 - slast */
17909           SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_20;/* offset: 0x128C size: 32 bit */
17910   
17911           /* SPP_DMA2_TCDn Word4 - daddr */
17912           SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_20;/* offset: 0x1290 size: 32 bit */
17913   
17914           /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
17915           SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_20;/* offset: 0x1294 size: 32 bit */
17916   
17917           /* SPP_DMA2_TCDn Word6 -  dlast_sga */
17918           SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_20;/* offset: 0x1298 size: 32 bit */
17919   
17920           /* SPP_DMA2_TCDn Word7 -  biter, etc. */
17921           SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_20;/* offset: 0x129C size: 32 bit */
17922   
17923           /* SPP_DMA2_TCDn Word0 - Source Address */
17924           SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_21;/* offset: 0x12A0 size: 32 bit */
17925   
17926           /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
17927           SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_21;/* offset: 0x12A4 size: 32 bit */
17928   
17929           /* SPP_DMA2_TCDn Word2 - nbytes */
17930           SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_21;/* offset: 0x12A8 size: 32 bit */
17931   
17932           /* SPP_DMA2_TCDn Word3 - slast */
17933           SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_21;/* offset: 0x12AC size: 32 bit */
17934   
17935           /* SPP_DMA2_TCDn Word4 - daddr */
17936           SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_21;/* offset: 0x12B0 size: 32 bit */
17937   
17938           /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
17939           SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_21;/* offset: 0x12B4 size: 32 bit */
17940   
17941           /* SPP_DMA2_TCDn Word6 -  dlast_sga */
17942           SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_21;/* offset: 0x12B8 size: 32 bit */
17943   
17944           /* SPP_DMA2_TCDn Word7 -  biter, etc. */
17945           SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_21;/* offset: 0x12BC size: 32 bit */
17946   
17947           /* SPP_DMA2_TCDn Word0 - Source Address */
17948           SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_22;/* offset: 0x12C0 size: 32 bit */
17949   
17950           /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
17951           SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_22;/* offset: 0x12C4 size: 32 bit */
17952   
17953           /* SPP_DMA2_TCDn Word2 - nbytes */
17954           SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_22;/* offset: 0x12C8 size: 32 bit */
17955   
17956           /* SPP_DMA2_TCDn Word3 - slast */
17957           SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_22;/* offset: 0x12CC size: 32 bit */
17958   
17959           /* SPP_DMA2_TCDn Word4 - daddr */
17960           SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_22;/* offset: 0x12D0 size: 32 bit */
17961   
17962           /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
17963           SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_22;/* offset: 0x12D4 size: 32 bit */
17964   
17965           /* SPP_DMA2_TCDn Word6 -  dlast_sga */
17966           SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_22;/* offset: 0x12D8 size: 32 bit */
17967   
17968           /* SPP_DMA2_TCDn Word7 -  biter, etc. */
17969           SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_22;/* offset: 0x12DC size: 32 bit */
17970   
17971           /* SPP_DMA2_TCDn Word0 - Source Address */
17972           SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_23;/* offset: 0x12E0 size: 32 bit */
17973   
17974           /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
17975           SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_23;/* offset: 0x12E4 size: 32 bit */
17976   
17977           /* SPP_DMA2_TCDn Word2 - nbytes */
17978           SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_23;/* offset: 0x12E8 size: 32 bit */
17979   
17980           /* SPP_DMA2_TCDn Word3 - slast */
17981           SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_23;/* offset: 0x12EC size: 32 bit */
17982   
17983           /* SPP_DMA2_TCDn Word4 - daddr */
17984           SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_23;/* offset: 0x12F0 size: 32 bit */
17985   
17986           /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
17987           SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_23;/* offset: 0x12F4 size: 32 bit */
17988   
17989           /* SPP_DMA2_TCDn Word6 -  dlast_sga */
17990           SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_23;/* offset: 0x12F8 size: 32 bit */
17991   
17992           /* SPP_DMA2_TCDn Word7 -  biter, etc. */
17993           SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_23;/* offset: 0x12FC size: 32 bit */
17994   
17995           /* SPP_DMA2_TCDn Word0 - Source Address */
17996           SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_24;/* offset: 0x1300 size: 32 bit */
17997   
17998           /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
17999           SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_24;/* offset: 0x1304 size: 32 bit */
18000   
18001           /* SPP_DMA2_TCDn Word2 - nbytes */
18002           SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_24;/* offset: 0x1308 size: 32 bit */
18003   
18004           /* SPP_DMA2_TCDn Word3 - slast */
18005           SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_24;/* offset: 0x130C size: 32 bit */
18006   
18007           /* SPP_DMA2_TCDn Word4 - daddr */
18008           SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_24;/* offset: 0x1310 size: 32 bit */
18009   
18010           /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
18011           SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_24;/* offset: 0x1314 size: 32 bit */
18012   
18013           /* SPP_DMA2_TCDn Word6 -  dlast_sga */
18014           SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_24;/* offset: 0x1318 size: 32 bit */
18015   
18016           /* SPP_DMA2_TCDn Word7 -  biter, etc. */
18017           SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_24;/* offset: 0x131C size: 32 bit */
18018   
18019           /* SPP_DMA2_TCDn Word0 - Source Address */
18020           SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_25;/* offset: 0x1320 size: 32 bit */
18021   
18022           /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
18023           SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_25;/* offset: 0x1324 size: 32 bit */
18024   
18025           /* SPP_DMA2_TCDn Word2 - nbytes */
18026           SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_25;/* offset: 0x1328 size: 32 bit */
18027   
18028           /* SPP_DMA2_TCDn Word3 - slast */
18029           SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_25;/* offset: 0x132C size: 32 bit */
18030   
18031           /* SPP_DMA2_TCDn Word4 - daddr */
18032           SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_25;/* offset: 0x1330 size: 32 bit */
18033   
18034           /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
18035           SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_25;/* offset: 0x1334 size: 32 bit */
18036   
18037           /* SPP_DMA2_TCDn Word6 -  dlast_sga */
18038           SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_25;/* offset: 0x1338 size: 32 bit */
18039   
18040           /* SPP_DMA2_TCDn Word7 -  biter, etc. */
18041           SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_25;/* offset: 0x133C size: 32 bit */
18042   
18043           /* SPP_DMA2_TCDn Word0 - Source Address */
18044           SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_26;/* offset: 0x1340 size: 32 bit */
18045   
18046           /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
18047           SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_26;/* offset: 0x1344 size: 32 bit */
18048   
18049           /* SPP_DMA2_TCDn Word2 - nbytes */
18050           SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_26;/* offset: 0x1348 size: 32 bit */
18051   
18052           /* SPP_DMA2_TCDn Word3 - slast */
18053           SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_26;/* offset: 0x134C size: 32 bit */
18054   
18055           /* SPP_DMA2_TCDn Word4 - daddr */
18056           SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_26;/* offset: 0x1350 size: 32 bit */
18057   
18058           /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
18059           SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_26;/* offset: 0x1354 size: 32 bit */
18060   
18061           /* SPP_DMA2_TCDn Word6 -  dlast_sga */
18062           SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_26;/* offset: 0x1358 size: 32 bit */
18063   
18064           /* SPP_DMA2_TCDn Word7 -  biter, etc. */
18065           SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_26;/* offset: 0x135C size: 32 bit */
18066   
18067           /* SPP_DMA2_TCDn Word0 - Source Address */
18068           SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_27;/* offset: 0x1360 size: 32 bit */
18069   
18070           /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
18071           SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_27;/* offset: 0x1364 size: 32 bit */
18072   
18073           /* SPP_DMA2_TCDn Word2 - nbytes */
18074           SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_27;/* offset: 0x1368 size: 32 bit */
18075   
18076           /* SPP_DMA2_TCDn Word3 - slast */
18077           SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_27;/* offset: 0x136C size: 32 bit */
18078   
18079           /* SPP_DMA2_TCDn Word4 - daddr */
18080           SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_27;/* offset: 0x1370 size: 32 bit */
18081   
18082           /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
18083           SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_27;/* offset: 0x1374 size: 32 bit */
18084   
18085           /* SPP_DMA2_TCDn Word6 -  dlast_sga */
18086           SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_27;/* offset: 0x1378 size: 32 bit */
18087   
18088           /* SPP_DMA2_TCDn Word7 -  biter, etc. */
18089           SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_27;/* offset: 0x137C size: 32 bit */
18090   
18091           /* SPP_DMA2_TCDn Word0 - Source Address */
18092           SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_28;/* offset: 0x1380 size: 32 bit */
18093   
18094           /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
18095           SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_28;/* offset: 0x1384 size: 32 bit */
18096   
18097           /* SPP_DMA2_TCDn Word2 - nbytes */
18098           SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_28;/* offset: 0x1388 size: 32 bit */
18099   
18100           /* SPP_DMA2_TCDn Word3 - slast */
18101           SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_28;/* offset: 0x138C size: 32 bit */
18102   
18103           /* SPP_DMA2_TCDn Word4 - daddr */
18104           SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_28;/* offset: 0x1390 size: 32 bit */
18105   
18106           /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
18107           SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_28;/* offset: 0x1394 size: 32 bit */
18108   
18109           /* SPP_DMA2_TCDn Word6 -  dlast_sga */
18110           SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_28;/* offset: 0x1398 size: 32 bit */
18111   
18112           /* SPP_DMA2_TCDn Word7 -  biter, etc. */
18113           SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_28;/* offset: 0x139C size: 32 bit */
18114   
18115           /* SPP_DMA2_TCDn Word0 - Source Address */
18116           SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_29;/* offset: 0x13A0 size: 32 bit */
18117   
18118           /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
18119           SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_29;/* offset: 0x13A4 size: 32 bit */
18120   
18121           /* SPP_DMA2_TCDn Word2 - nbytes */
18122           SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_29;/* offset: 0x13A8 size: 32 bit */
18123   
18124           /* SPP_DMA2_TCDn Word3 - slast */
18125           SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_29;/* offset: 0x13AC size: 32 bit */
18126   
18127           /* SPP_DMA2_TCDn Word4 - daddr */
18128           SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_29;/* offset: 0x13B0 size: 32 bit */
18129   
18130           /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
18131           SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_29;/* offset: 0x13B4 size: 32 bit */
18132   
18133           /* SPP_DMA2_TCDn Word6 -  dlast_sga */
18134           SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_29;/* offset: 0x13B8 size: 32 bit */
18135   
18136           /* SPP_DMA2_TCDn Word7 -  biter, etc. */
18137           SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_29;/* offset: 0x13BC size: 32 bit */
18138   
18139           /* SPP_DMA2_TCDn Word0 - Source Address */
18140           SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_30;/* offset: 0x13C0 size: 32 bit */
18141   
18142           /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
18143           SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_30;/* offset: 0x13C4 size: 32 bit */
18144   
18145           /* SPP_DMA2_TCDn Word2 - nbytes */
18146           SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_30;/* offset: 0x13C8 size: 32 bit */
18147   
18148           /* SPP_DMA2_TCDn Word3 - slast */
18149           SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_30;/* offset: 0x13CC size: 32 bit */
18150   
18151           /* SPP_DMA2_TCDn Word4 - daddr */
18152           SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_30;/* offset: 0x13D0 size: 32 bit */
18153   
18154           /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
18155           SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_30;/* offset: 0x13D4 size: 32 bit */
18156   
18157           /* SPP_DMA2_TCDn Word6 -  dlast_sga */
18158           SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_30;/* offset: 0x13D8 size: 32 bit */
18159   
18160           /* SPP_DMA2_TCDn Word7 -  biter, etc. */
18161           SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_30;/* offset: 0x13DC size: 32 bit */
18162   
18163           /* SPP_DMA2_TCDn Word0 - Source Address */
18164           SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_31;/* offset: 0x13E0 size: 32 bit */
18165   
18166           /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
18167           SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_31;/* offset: 0x13E4 size: 32 bit */
18168   
18169           /* SPP_DMA2_TCDn Word2 - nbytes */
18170           SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_31;/* offset: 0x13E8 size: 32 bit */
18171   
18172           /* SPP_DMA2_TCDn Word3 - slast */
18173           SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_31;/* offset: 0x13EC size: 32 bit */
18174   
18175           /* SPP_DMA2_TCDn Word4 - daddr */
18176           SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_31;/* offset: 0x13F0 size: 32 bit */
18177   
18178           /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
18179           SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_31;/* offset: 0x13F4 size: 32 bit */
18180   
18181           /* SPP_DMA2_TCDn Word6 -  dlast_sga */
18182           SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_31;/* offset: 0x13F8 size: 32 bit */
18183   
18184           /* SPP_DMA2_TCDn Word7 -  biter, etc. */
18185           SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_31;/* offset: 0x13FC size: 32 bit */
18186   
18187           /* SPP_DMA2_TCDn Word0 - Source Address */
18188           SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_32;/* offset: 0x1400 size: 32 bit */
18189   
18190           /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
18191           SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_32;/* offset: 0x1404 size: 32 bit */
18192   
18193           /* SPP_DMA2_TCDn Word2 - nbytes */
18194           SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_32;/* offset: 0x1408 size: 32 bit */
18195   
18196           /* SPP_DMA2_TCDn Word3 - slast */
18197           SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_32;/* offset: 0x140C size: 32 bit */
18198   
18199           /* SPP_DMA2_TCDn Word4 - daddr */
18200           SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_32;/* offset: 0x1410 size: 32 bit */
18201   
18202           /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
18203           SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_32;/* offset: 0x1414 size: 32 bit */
18204   
18205           /* SPP_DMA2_TCDn Word6 -  dlast_sga */
18206           SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_32;/* offset: 0x1418 size: 32 bit */
18207   
18208           /* SPP_DMA2_TCDn Word7 -  biter, etc. */
18209           SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_32;/* offset: 0x141C size: 32 bit */
18210   
18211           /* SPP_DMA2_TCDn Word0 - Source Address */
18212           SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_33;/* offset: 0x1420 size: 32 bit */
18213   
18214           /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
18215           SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_33;/* offset: 0x1424 size: 32 bit */
18216   
18217           /* SPP_DMA2_TCDn Word2 - nbytes */
18218           SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_33;/* offset: 0x1428 size: 32 bit */
18219   
18220           /* SPP_DMA2_TCDn Word3 - slast */
18221           SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_33;/* offset: 0x142C size: 32 bit */
18222   
18223           /* SPP_DMA2_TCDn Word4 - daddr */
18224           SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_33;/* offset: 0x1430 size: 32 bit */
18225   
18226           /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
18227           SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_33;/* offset: 0x1434 size: 32 bit */
18228   
18229           /* SPP_DMA2_TCDn Word6 -  dlast_sga */
18230           SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_33;/* offset: 0x1438 size: 32 bit */
18231   
18232           /* SPP_DMA2_TCDn Word7 -  biter, etc. */
18233           SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_33;/* offset: 0x143C size: 32 bit */
18234   
18235           /* SPP_DMA2_TCDn Word0 - Source Address */
18236           SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_34;/* offset: 0x1440 size: 32 bit */
18237   
18238           /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
18239           SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_34;/* offset: 0x1444 size: 32 bit */
18240   
18241           /* SPP_DMA2_TCDn Word2 - nbytes */
18242           SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_34;/* offset: 0x1448 size: 32 bit */
18243   
18244           /* SPP_DMA2_TCDn Word3 - slast */
18245           SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_34;/* offset: 0x144C size: 32 bit */
18246   
18247           /* SPP_DMA2_TCDn Word4 - daddr */
18248           SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_34;/* offset: 0x1450 size: 32 bit */
18249   
18250           /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
18251           SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_34;/* offset: 0x1454 size: 32 bit */
18252   
18253           /* SPP_DMA2_TCDn Word6 -  dlast_sga */
18254           SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_34;/* offset: 0x1458 size: 32 bit */
18255   
18256           /* SPP_DMA2_TCDn Word7 -  biter, etc. */
18257           SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_34;/* offset: 0x145C size: 32 bit */
18258   
18259           /* SPP_DMA2_TCDn Word0 - Source Address */
18260           SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_35;/* offset: 0x1460 size: 32 bit */
18261   
18262           /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
18263           SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_35;/* offset: 0x1464 size: 32 bit */
18264   
18265           /* SPP_DMA2_TCDn Word2 - nbytes */
18266           SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_35;/* offset: 0x1468 size: 32 bit */
18267   
18268           /* SPP_DMA2_TCDn Word3 - slast */
18269           SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_35;/* offset: 0x146C size: 32 bit */
18270   
18271           /* SPP_DMA2_TCDn Word4 - daddr */
18272           SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_35;/* offset: 0x1470 size: 32 bit */
18273   
18274           /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
18275           SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_35;/* offset: 0x1474 size: 32 bit */
18276   
18277           /* SPP_DMA2_TCDn Word6 -  dlast_sga */
18278           SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_35;/* offset: 0x1478 size: 32 bit */
18279   
18280           /* SPP_DMA2_TCDn Word7 -  biter, etc. */
18281           SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_35;/* offset: 0x147C size: 32 bit */
18282   
18283           /* SPP_DMA2_TCDn Word0 - Source Address */
18284           SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_36;/* offset: 0x1480 size: 32 bit */
18285   
18286           /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
18287           SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_36;/* offset: 0x1484 size: 32 bit */
18288   
18289           /* SPP_DMA2_TCDn Word2 - nbytes */
18290           SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_36;/* offset: 0x1488 size: 32 bit */
18291   
18292           /* SPP_DMA2_TCDn Word3 - slast */
18293           SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_36;/* offset: 0x148C size: 32 bit */
18294   
18295           /* SPP_DMA2_TCDn Word4 - daddr */
18296           SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_36;/* offset: 0x1490 size: 32 bit */
18297   
18298           /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
18299           SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_36;/* offset: 0x1494 size: 32 bit */
18300   
18301           /* SPP_DMA2_TCDn Word6 -  dlast_sga */
18302           SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_36;/* offset: 0x1498 size: 32 bit */
18303   
18304           /* SPP_DMA2_TCDn Word7 -  biter, etc. */
18305           SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_36;/* offset: 0x149C size: 32 bit */
18306   
18307           /* SPP_DMA2_TCDn Word0 - Source Address */
18308           SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_37;/* offset: 0x14A0 size: 32 bit */
18309   
18310           /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
18311           SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_37;/* offset: 0x14A4 size: 32 bit */
18312   
18313           /* SPP_DMA2_TCDn Word2 - nbytes */
18314           SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_37;/* offset: 0x14A8 size: 32 bit */
18315   
18316           /* SPP_DMA2_TCDn Word3 - slast */
18317           SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_37;/* offset: 0x14AC size: 32 bit */
18318   
18319           /* SPP_DMA2_TCDn Word4 - daddr */
18320           SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_37;/* offset: 0x14B0 size: 32 bit */
18321   
18322           /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
18323           SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_37;/* offset: 0x14B4 size: 32 bit */
18324   
18325           /* SPP_DMA2_TCDn Word6 -  dlast_sga */
18326           SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_37;/* offset: 0x14B8 size: 32 bit */
18327   
18328           /* SPP_DMA2_TCDn Word7 -  biter, etc. */
18329           SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_37;/* offset: 0x14BC size: 32 bit */
18330   
18331           /* SPP_DMA2_TCDn Word0 - Source Address */
18332           SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_38;/* offset: 0x14C0 size: 32 bit */
18333   
18334           /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
18335           SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_38;/* offset: 0x14C4 size: 32 bit */
18336   
18337           /* SPP_DMA2_TCDn Word2 - nbytes */
18338           SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_38;/* offset: 0x14C8 size: 32 bit */
18339   
18340           /* SPP_DMA2_TCDn Word3 - slast */
18341           SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_38;/* offset: 0x14CC size: 32 bit */
18342   
18343           /* SPP_DMA2_TCDn Word4 - daddr */
18344           SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_38;/* offset: 0x14D0 size: 32 bit */
18345   
18346           /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
18347           SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_38;/* offset: 0x14D4 size: 32 bit */
18348   
18349           /* SPP_DMA2_TCDn Word6 -  dlast_sga */
18350           SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_38;/* offset: 0x14D8 size: 32 bit */
18351   
18352           /* SPP_DMA2_TCDn Word7 -  biter, etc. */
18353           SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_38;/* offset: 0x14DC size: 32 bit */
18354   
18355           /* SPP_DMA2_TCDn Word0 - Source Address */
18356           SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_39;/* offset: 0x14E0 size: 32 bit */
18357   
18358           /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
18359           SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_39;/* offset: 0x14E4 size: 32 bit */
18360   
18361           /* SPP_DMA2_TCDn Word2 - nbytes */
18362           SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_39;/* offset: 0x14E8 size: 32 bit */
18363   
18364           /* SPP_DMA2_TCDn Word3 - slast */
18365           SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_39;/* offset: 0x14EC size: 32 bit */
18366   
18367           /* SPP_DMA2_TCDn Word4 - daddr */
18368           SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_39;/* offset: 0x14F0 size: 32 bit */
18369   
18370           /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
18371           SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_39;/* offset: 0x14F4 size: 32 bit */
18372   
18373           /* SPP_DMA2_TCDn Word6 -  dlast_sga */
18374           SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_39;/* offset: 0x14F8 size: 32 bit */
18375   
18376           /* SPP_DMA2_TCDn Word7 -  biter, etc. */
18377           SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_39;/* offset: 0x14FC size: 32 bit */
18378   
18379           /* SPP_DMA2_TCDn Word0 - Source Address */
18380           SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_40;/* offset: 0x1500 size: 32 bit */
18381   
18382           /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
18383           SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_40;/* offset: 0x1504 size: 32 bit */
18384   
18385           /* SPP_DMA2_TCDn Word2 - nbytes */
18386           SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_40;/* offset: 0x1508 size: 32 bit */
18387   
18388           /* SPP_DMA2_TCDn Word3 - slast */
18389           SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_40;/* offset: 0x150C size: 32 bit */
18390   
18391           /* SPP_DMA2_TCDn Word4 - daddr */
18392           SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_40;/* offset: 0x1510 size: 32 bit */
18393   
18394           /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
18395           SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_40;/* offset: 0x1514 size: 32 bit */
18396   
18397           /* SPP_DMA2_TCDn Word6 -  dlast_sga */
18398           SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_40;/* offset: 0x1518 size: 32 bit */
18399   
18400           /* SPP_DMA2_TCDn Word7 -  biter, etc. */
18401           SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_40;/* offset: 0x151C size: 32 bit */
18402   
18403           /* SPP_DMA2_TCDn Word0 - Source Address */
18404           SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_41;/* offset: 0x1520 size: 32 bit */
18405   
18406           /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
18407           SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_41;/* offset: 0x1524 size: 32 bit */
18408   
18409           /* SPP_DMA2_TCDn Word2 - nbytes */
18410           SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_41;/* offset: 0x1528 size: 32 bit */
18411   
18412           /* SPP_DMA2_TCDn Word3 - slast */
18413           SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_41;/* offset: 0x152C size: 32 bit */
18414   
18415           /* SPP_DMA2_TCDn Word4 - daddr */
18416           SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_41;/* offset: 0x1530 size: 32 bit */
18417   
18418           /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
18419           SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_41;/* offset: 0x1534 size: 32 bit */
18420   
18421           /* SPP_DMA2_TCDn Word6 -  dlast_sga */
18422           SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_41;/* offset: 0x1538 size: 32 bit */
18423   
18424           /* SPP_DMA2_TCDn Word7 -  biter, etc. */
18425           SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_41;/* offset: 0x153C size: 32 bit */
18426   
18427           /* SPP_DMA2_TCDn Word0 - Source Address */
18428           SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_42;/* offset: 0x1540 size: 32 bit */
18429   
18430           /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
18431           SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_42;/* offset: 0x1544 size: 32 bit */
18432   
18433           /* SPP_DMA2_TCDn Word2 - nbytes */
18434           SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_42;/* offset: 0x1548 size: 32 bit */
18435   
18436           /* SPP_DMA2_TCDn Word3 - slast */
18437           SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_42;/* offset: 0x154C size: 32 bit */
18438   
18439           /* SPP_DMA2_TCDn Word4 - daddr */
18440           SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_42;/* offset: 0x1550 size: 32 bit */
18441   
18442           /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
18443           SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_42;/* offset: 0x1554 size: 32 bit */
18444   
18445           /* SPP_DMA2_TCDn Word6 -  dlast_sga */
18446           SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_42;/* offset: 0x1558 size: 32 bit */
18447   
18448           /* SPP_DMA2_TCDn Word7 -  biter, etc. */
18449           SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_42;/* offset: 0x155C size: 32 bit */
18450   
18451           /* SPP_DMA2_TCDn Word0 - Source Address */
18452           SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_43;/* offset: 0x1560 size: 32 bit */
18453   
18454           /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
18455           SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_43;/* offset: 0x1564 size: 32 bit */
18456   
18457           /* SPP_DMA2_TCDn Word2 - nbytes */
18458           SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_43;/* offset: 0x1568 size: 32 bit */
18459   
18460           /* SPP_DMA2_TCDn Word3 - slast */
18461           SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_43;/* offset: 0x156C size: 32 bit */
18462   
18463           /* SPP_DMA2_TCDn Word4 - daddr */
18464           SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_43;/* offset: 0x1570 size: 32 bit */
18465   
18466           /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
18467           SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_43;/* offset: 0x1574 size: 32 bit */
18468   
18469           /* SPP_DMA2_TCDn Word6 -  dlast_sga */
18470           SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_43;/* offset: 0x1578 size: 32 bit */
18471   
18472           /* SPP_DMA2_TCDn Word7 -  biter, etc. */
18473           SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_43;/* offset: 0x157C size: 32 bit */
18474   
18475           /* SPP_DMA2_TCDn Word0 - Source Address */
18476           SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_44;/* offset: 0x1580 size: 32 bit */
18477   
18478           /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
18479           SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_44;/* offset: 0x1584 size: 32 bit */
18480   
18481           /* SPP_DMA2_TCDn Word2 - nbytes */
18482           SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_44;/* offset: 0x1588 size: 32 bit */
18483   
18484           /* SPP_DMA2_TCDn Word3 - slast */
18485           SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_44;/* offset: 0x158C size: 32 bit */
18486   
18487           /* SPP_DMA2_TCDn Word4 - daddr */
18488           SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_44;/* offset: 0x1590 size: 32 bit */
18489   
18490           /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
18491           SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_44;/* offset: 0x1594 size: 32 bit */
18492   
18493           /* SPP_DMA2_TCDn Word6 -  dlast_sga */
18494           SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_44;/* offset: 0x1598 size: 32 bit */
18495   
18496           /* SPP_DMA2_TCDn Word7 -  biter, etc. */
18497           SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_44;/* offset: 0x159C size: 32 bit */
18498   
18499           /* SPP_DMA2_TCDn Word0 - Source Address */
18500           SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_45;/* offset: 0x15A0 size: 32 bit */
18501   
18502           /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
18503           SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_45;/* offset: 0x15A4 size: 32 bit */
18504   
18505           /* SPP_DMA2_TCDn Word2 - nbytes */
18506           SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_45;/* offset: 0x15A8 size: 32 bit */
18507   
18508           /* SPP_DMA2_TCDn Word3 - slast */
18509           SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_45;/* offset: 0x15AC size: 32 bit */
18510   
18511           /* SPP_DMA2_TCDn Word4 - daddr */
18512           SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_45;/* offset: 0x15B0 size: 32 bit */
18513   
18514           /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
18515           SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_45;/* offset: 0x15B4 size: 32 bit */
18516   
18517           /* SPP_DMA2_TCDn Word6 -  dlast_sga */
18518           SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_45;/* offset: 0x15B8 size: 32 bit */
18519   
18520           /* SPP_DMA2_TCDn Word7 -  biter, etc. */
18521           SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_45;/* offset: 0x15BC size: 32 bit */
18522   
18523           /* SPP_DMA2_TCDn Word0 - Source Address */
18524           SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_46;/* offset: 0x15C0 size: 32 bit */
18525   
18526           /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
18527           SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_46;/* offset: 0x15C4 size: 32 bit */
18528   
18529           /* SPP_DMA2_TCDn Word2 - nbytes */
18530           SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_46;/* offset: 0x15C8 size: 32 bit */
18531   
18532           /* SPP_DMA2_TCDn Word3 - slast */
18533           SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_46;/* offset: 0x15CC size: 32 bit */
18534   
18535           /* SPP_DMA2_TCDn Word4 - daddr */
18536           SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_46;/* offset: 0x15D0 size: 32 bit */
18537   
18538           /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
18539           SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_46;/* offset: 0x15D4 size: 32 bit */
18540   
18541           /* SPP_DMA2_TCDn Word6 -  dlast_sga */
18542           SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_46;/* offset: 0x15D8 size: 32 bit */
18543   
18544           /* SPP_DMA2_TCDn Word7 -  biter, etc. */
18545           SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_46;/* offset: 0x15DC size: 32 bit */
18546   
18547           /* SPP_DMA2_TCDn Word0 - Source Address */
18548           SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_47;/* offset: 0x15E0 size: 32 bit */
18549   
18550           /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
18551           SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_47;/* offset: 0x15E4 size: 32 bit */
18552   
18553           /* SPP_DMA2_TCDn Word2 - nbytes */
18554           SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_47;/* offset: 0x15E8 size: 32 bit */
18555   
18556           /* SPP_DMA2_TCDn Word3 - slast */
18557           SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_47;/* offset: 0x15EC size: 32 bit */
18558   
18559           /* SPP_DMA2_TCDn Word4 - daddr */
18560           SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_47;/* offset: 0x15F0 size: 32 bit */
18561   
18562           /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
18563           SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_47;/* offset: 0x15F4 size: 32 bit */
18564   
18565           /* SPP_DMA2_TCDn Word6 -  dlast_sga */
18566           SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_47;/* offset: 0x15F8 size: 32 bit */
18567   
18568           /* SPP_DMA2_TCDn Word7 -  biter, etc. */
18569           SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_47;/* offset: 0x15FC size: 32 bit */
18570   
18571           /* SPP_DMA2_TCDn Word0 - Source Address */
18572           SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_48;/* offset: 0x1600 size: 32 bit */
18573   
18574           /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
18575           SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_48;/* offset: 0x1604 size: 32 bit */
18576   
18577           /* SPP_DMA2_TCDn Word2 - nbytes */
18578           SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_48;/* offset: 0x1608 size: 32 bit */
18579   
18580           /* SPP_DMA2_TCDn Word3 - slast */
18581           SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_48;/* offset: 0x160C size: 32 bit */
18582   
18583           /* SPP_DMA2_TCDn Word4 - daddr */
18584           SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_48;/* offset: 0x1610 size: 32 bit */
18585   
18586           /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
18587           SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_48;/* offset: 0x1614 size: 32 bit */
18588   
18589           /* SPP_DMA2_TCDn Word6 -  dlast_sga */
18590           SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_48;/* offset: 0x1618 size: 32 bit */
18591   
18592           /* SPP_DMA2_TCDn Word7 -  biter, etc. */
18593           SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_48;/* offset: 0x161C size: 32 bit */
18594   
18595           /* SPP_DMA2_TCDn Word0 - Source Address */
18596           SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_49;/* offset: 0x1620 size: 32 bit */
18597   
18598           /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
18599           SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_49;/* offset: 0x1624 size: 32 bit */
18600   
18601           /* SPP_DMA2_TCDn Word2 - nbytes */
18602           SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_49;/* offset: 0x1628 size: 32 bit */
18603   
18604           /* SPP_DMA2_TCDn Word3 - slast */
18605           SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_49;/* offset: 0x162C size: 32 bit */
18606   
18607           /* SPP_DMA2_TCDn Word4 - daddr */
18608           SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_49;/* offset: 0x1630 size: 32 bit */
18609   
18610           /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
18611           SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_49;/* offset: 0x1634 size: 32 bit */
18612   
18613           /* SPP_DMA2_TCDn Word6 -  dlast_sga */
18614           SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_49;/* offset: 0x1638 size: 32 bit */
18615   
18616           /* SPP_DMA2_TCDn Word7 -  biter, etc. */
18617           SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_49;/* offset: 0x163C size: 32 bit */
18618   
18619           /* SPP_DMA2_TCDn Word0 - Source Address */
18620           SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_50;/* offset: 0x1640 size: 32 bit */
18621   
18622           /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
18623           SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_50;/* offset: 0x1644 size: 32 bit */
18624   
18625           /* SPP_DMA2_TCDn Word2 - nbytes */
18626           SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_50;/* offset: 0x1648 size: 32 bit */
18627   
18628           /* SPP_DMA2_TCDn Word3 - slast */
18629           SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_50;/* offset: 0x164C size: 32 bit */
18630   
18631           /* SPP_DMA2_TCDn Word4 - daddr */
18632           SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_50;/* offset: 0x1650 size: 32 bit */
18633   
18634           /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
18635           SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_50;/* offset: 0x1654 size: 32 bit */
18636   
18637           /* SPP_DMA2_TCDn Word6 -  dlast_sga */
18638           SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_50;/* offset: 0x1658 size: 32 bit */
18639   
18640           /* SPP_DMA2_TCDn Word7 -  biter, etc. */
18641           SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_50;/* offset: 0x165C size: 32 bit */
18642   
18643           /* SPP_DMA2_TCDn Word0 - Source Address */
18644           SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_51;/* offset: 0x1660 size: 32 bit */
18645   
18646           /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
18647           SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_51;/* offset: 0x1664 size: 32 bit */
18648   
18649           /* SPP_DMA2_TCDn Word2 - nbytes */
18650           SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_51;/* offset: 0x1668 size: 32 bit */
18651   
18652           /* SPP_DMA2_TCDn Word3 - slast */
18653           SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_51;/* offset: 0x166C size: 32 bit */
18654   
18655           /* SPP_DMA2_TCDn Word4 - daddr */
18656           SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_51;/* offset: 0x1670 size: 32 bit */
18657   
18658           /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
18659           SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_51;/* offset: 0x1674 size: 32 bit */
18660   
18661           /* SPP_DMA2_TCDn Word6 -  dlast_sga */
18662           SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_51;/* offset: 0x1678 size: 32 bit */
18663   
18664           /* SPP_DMA2_TCDn Word7 -  biter, etc. */
18665           SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_51;/* offset: 0x167C size: 32 bit */
18666   
18667           /* SPP_DMA2_TCDn Word0 - Source Address */
18668           SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_52;/* offset: 0x1680 size: 32 bit */
18669   
18670           /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
18671           SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_52;/* offset: 0x1684 size: 32 bit */
18672   
18673           /* SPP_DMA2_TCDn Word2 - nbytes */
18674           SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_52;/* offset: 0x1688 size: 32 bit */
18675   
18676           /* SPP_DMA2_TCDn Word3 - slast */
18677           SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_52;/* offset: 0x168C size: 32 bit */
18678   
18679           /* SPP_DMA2_TCDn Word4 - daddr */
18680           SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_52;/* offset: 0x1690 size: 32 bit */
18681   
18682           /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
18683           SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_52;/* offset: 0x1694 size: 32 bit */
18684   
18685           /* SPP_DMA2_TCDn Word6 -  dlast_sga */
18686           SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_52;/* offset: 0x1698 size: 32 bit */
18687   
18688           /* SPP_DMA2_TCDn Word7 -  biter, etc. */
18689           SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_52;/* offset: 0x169C size: 32 bit */
18690   
18691           /* SPP_DMA2_TCDn Word0 - Source Address */
18692           SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_53;/* offset: 0x16A0 size: 32 bit */
18693   
18694           /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
18695           SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_53;/* offset: 0x16A4 size: 32 bit */
18696   
18697           /* SPP_DMA2_TCDn Word2 - nbytes */
18698           SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_53;/* offset: 0x16A8 size: 32 bit */
18699   
18700           /* SPP_DMA2_TCDn Word3 - slast */
18701           SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_53;/* offset: 0x16AC size: 32 bit */
18702   
18703           /* SPP_DMA2_TCDn Word4 - daddr */
18704           SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_53;/* offset: 0x16B0 size: 32 bit */
18705   
18706           /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
18707           SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_53;/* offset: 0x16B4 size: 32 bit */
18708   
18709           /* SPP_DMA2_TCDn Word6 -  dlast_sga */
18710           SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_53;/* offset: 0x16B8 size: 32 bit */
18711   
18712           /* SPP_DMA2_TCDn Word7 -  biter, etc. */
18713           SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_53;/* offset: 0x16BC size: 32 bit */
18714   
18715           /* SPP_DMA2_TCDn Word0 - Source Address */
18716           SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_54;/* offset: 0x16C0 size: 32 bit */
18717   
18718           /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
18719           SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_54;/* offset: 0x16C4 size: 32 bit */
18720   
18721           /* SPP_DMA2_TCDn Word2 - nbytes */
18722           SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_54;/* offset: 0x16C8 size: 32 bit */
18723   
18724           /* SPP_DMA2_TCDn Word3 - slast */
18725           SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_54;/* offset: 0x16CC size: 32 bit */
18726   
18727           /* SPP_DMA2_TCDn Word4 - daddr */
18728           SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_54;/* offset: 0x16D0 size: 32 bit */
18729   
18730           /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
18731           SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_54;/* offset: 0x16D4 size: 32 bit */
18732   
18733           /* SPP_DMA2_TCDn Word6 -  dlast_sga */
18734           SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_54;/* offset: 0x16D8 size: 32 bit */
18735   
18736           /* SPP_DMA2_TCDn Word7 -  biter, etc. */
18737           SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_54;/* offset: 0x16DC size: 32 bit */
18738   
18739           /* SPP_DMA2_TCDn Word0 - Source Address */
18740           SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_55;/* offset: 0x16E0 size: 32 bit */
18741   
18742           /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
18743           SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_55;/* offset: 0x16E4 size: 32 bit */
18744   
18745           /* SPP_DMA2_TCDn Word2 - nbytes */
18746           SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_55;/* offset: 0x16E8 size: 32 bit */
18747   
18748           /* SPP_DMA2_TCDn Word3 - slast */
18749           SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_55;/* offset: 0x16EC size: 32 bit */
18750   
18751           /* SPP_DMA2_TCDn Word4 - daddr */
18752           SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_55;/* offset: 0x16F0 size: 32 bit */
18753   
18754           /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
18755           SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_55;/* offset: 0x16F4 size: 32 bit */
18756   
18757           /* SPP_DMA2_TCDn Word6 -  dlast_sga */
18758           SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_55;/* offset: 0x16F8 size: 32 bit */
18759   
18760           /* SPP_DMA2_TCDn Word7 -  biter, etc. */
18761           SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_55;/* offset: 0x16FC size: 32 bit */
18762   
18763           /* SPP_DMA2_TCDn Word0 - Source Address */
18764           SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_56;/* offset: 0x1700 size: 32 bit */
18765   
18766           /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
18767           SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_56;/* offset: 0x1704 size: 32 bit */
18768   
18769           /* SPP_DMA2_TCDn Word2 - nbytes */
18770           SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_56;/* offset: 0x1708 size: 32 bit */
18771   
18772           /* SPP_DMA2_TCDn Word3 - slast */
18773           SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_56;/* offset: 0x170C size: 32 bit */
18774   
18775           /* SPP_DMA2_TCDn Word4 - daddr */
18776           SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_56;/* offset: 0x1710 size: 32 bit */
18777   
18778           /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
18779           SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_56;/* offset: 0x1714 size: 32 bit */
18780   
18781           /* SPP_DMA2_TCDn Word6 -  dlast_sga */
18782           SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_56;/* offset: 0x1718 size: 32 bit */
18783   
18784           /* SPP_DMA2_TCDn Word7 -  biter, etc. */
18785           SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_56;/* offset: 0x171C size: 32 bit */
18786   
18787           /* SPP_DMA2_TCDn Word0 - Source Address */
18788           SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_57;/* offset: 0x1720 size: 32 bit */
18789   
18790           /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
18791           SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_57;/* offset: 0x1724 size: 32 bit */
18792   
18793           /* SPP_DMA2_TCDn Word2 - nbytes */
18794           SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_57;/* offset: 0x1728 size: 32 bit */
18795   
18796           /* SPP_DMA2_TCDn Word3 - slast */
18797           SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_57;/* offset: 0x172C size: 32 bit */
18798   
18799           /* SPP_DMA2_TCDn Word4 - daddr */
18800           SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_57;/* offset: 0x1730 size: 32 bit */
18801   
18802           /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
18803           SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_57;/* offset: 0x1734 size: 32 bit */
18804   
18805           /* SPP_DMA2_TCDn Word6 -  dlast_sga */
18806           SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_57;/* offset: 0x1738 size: 32 bit */
18807   
18808           /* SPP_DMA2_TCDn Word7 -  biter, etc. */
18809           SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_57;/* offset: 0x173C size: 32 bit */
18810   
18811           /* SPP_DMA2_TCDn Word0 - Source Address */
18812           SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_58;/* offset: 0x1740 size: 32 bit */
18813   
18814           /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
18815           SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_58;/* offset: 0x1744 size: 32 bit */
18816   
18817           /* SPP_DMA2_TCDn Word2 - nbytes */
18818           SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_58;/* offset: 0x1748 size: 32 bit */
18819   
18820           /* SPP_DMA2_TCDn Word3 - slast */
18821           SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_58;/* offset: 0x174C size: 32 bit */
18822   
18823           /* SPP_DMA2_TCDn Word4 - daddr */
18824           SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_58;/* offset: 0x1750 size: 32 bit */
18825   
18826           /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
18827           SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_58;/* offset: 0x1754 size: 32 bit */
18828   
18829           /* SPP_DMA2_TCDn Word6 -  dlast_sga */
18830           SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_58;/* offset: 0x1758 size: 32 bit */
18831   
18832           /* SPP_DMA2_TCDn Word7 -  biter, etc. */
18833           SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_58;/* offset: 0x175C size: 32 bit */
18834   
18835           /* SPP_DMA2_TCDn Word0 - Source Address */
18836           SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_59;/* offset: 0x1760 size: 32 bit */
18837   
18838           /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
18839           SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_59;/* offset: 0x1764 size: 32 bit */
18840   
18841           /* SPP_DMA2_TCDn Word2 - nbytes */
18842           SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_59;/* offset: 0x1768 size: 32 bit */
18843   
18844           /* SPP_DMA2_TCDn Word3 - slast */
18845           SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_59;/* offset: 0x176C size: 32 bit */
18846   
18847           /* SPP_DMA2_TCDn Word4 - daddr */
18848           SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_59;/* offset: 0x1770 size: 32 bit */
18849   
18850           /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
18851           SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_59;/* offset: 0x1774 size: 32 bit */
18852   
18853           /* SPP_DMA2_TCDn Word6 -  dlast_sga */
18854           SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_59;/* offset: 0x1778 size: 32 bit */
18855   
18856           /* SPP_DMA2_TCDn Word7 -  biter, etc. */
18857           SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_59;/* offset: 0x177C size: 32 bit */
18858   
18859           /* SPP_DMA2_TCDn Word0 - Source Address */
18860           SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_60;/* offset: 0x1780 size: 32 bit */
18861   
18862           /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
18863           SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_60;/* offset: 0x1784 size: 32 bit */
18864   
18865           /* SPP_DMA2_TCDn Word2 - nbytes */
18866           SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_60;/* offset: 0x1788 size: 32 bit */
18867   
18868           /* SPP_DMA2_TCDn Word3 - slast */
18869           SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_60;/* offset: 0x178C size: 32 bit */
18870   
18871           /* SPP_DMA2_TCDn Word4 - daddr */
18872           SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_60;/* offset: 0x1790 size: 32 bit */
18873   
18874           /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
18875           SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_60;/* offset: 0x1794 size: 32 bit */
18876   
18877           /* SPP_DMA2_TCDn Word6 -  dlast_sga */
18878           SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_60;/* offset: 0x1798 size: 32 bit */
18879   
18880           /* SPP_DMA2_TCDn Word7 -  biter, etc. */
18881           SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_60;/* offset: 0x179C size: 32 bit */
18882   
18883           /* SPP_DMA2_TCDn Word0 - Source Address */
18884           SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_61;/* offset: 0x17A0 size: 32 bit */
18885   
18886           /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
18887           SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_61;/* offset: 0x17A4 size: 32 bit */
18888   
18889           /* SPP_DMA2_TCDn Word2 - nbytes */
18890           SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_61;/* offset: 0x17A8 size: 32 bit */
18891   
18892           /* SPP_DMA2_TCDn Word3 - slast */
18893           SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_61;/* offset: 0x17AC size: 32 bit */
18894   
18895           /* SPP_DMA2_TCDn Word4 - daddr */
18896           SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_61;/* offset: 0x17B0 size: 32 bit */
18897   
18898           /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
18899           SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_61;/* offset: 0x17B4 size: 32 bit */
18900   
18901           /* SPP_DMA2_TCDn Word6 -  dlast_sga */
18902           SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_61;/* offset: 0x17B8 size: 32 bit */
18903   
18904           /* SPP_DMA2_TCDn Word7 -  biter, etc. */
18905           SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_61;/* offset: 0x17BC size: 32 bit */
18906   
18907           /* SPP_DMA2_TCDn Word0 - Source Address */
18908           SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_62;/* offset: 0x17C0 size: 32 bit */
18909   
18910           /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
18911           SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_62;/* offset: 0x17C4 size: 32 bit */
18912   
18913           /* SPP_DMA2_TCDn Word2 - nbytes */
18914           SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_62;/* offset: 0x17C8 size: 32 bit */
18915   
18916           /* SPP_DMA2_TCDn Word3 - slast */
18917           SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_62;/* offset: 0x17CC size: 32 bit */
18918   
18919           /* SPP_DMA2_TCDn Word4 - daddr */
18920           SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_62;/* offset: 0x17D0 size: 32 bit */
18921   
18922           /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
18923           SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_62;/* offset: 0x17D4 size: 32 bit */
18924   
18925           /* SPP_DMA2_TCDn Word6 -  dlast_sga */
18926           SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_62;/* offset: 0x17D8 size: 32 bit */
18927   
18928           /* SPP_DMA2_TCDn Word7 -  biter, etc. */
18929           SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_62;/* offset: 0x17DC size: 32 bit */
18930   
18931           /* SPP_DMA2_TCDn Word0 - Source Address */
18932           SPP_DMA2_TCDWORD0__32B_tag TCDWORD0_63;/* offset: 0x17E0 size: 32 bit */
18933   
18934           /* SPP_DMA2_TCDn Word1 - smod, ssize, dmod, dsize, soff */
18935           SPP_DMA2_TCDWORD4__32B_tag TCDWORD4_63;/* offset: 0x17E4 size: 32 bit */
18936   
18937           /* SPP_DMA2_TCDn Word2 - nbytes */
18938           SPP_DMA2_TCDWORD8__32B_tag TCDWORD8_63;/* offset: 0x17E8 size: 32 bit */
18939   
18940           /* SPP_DMA2_TCDn Word3 - slast */
18941           SPP_DMA2_TCDWORD12__32B_tag TCDWORD12_63;/* offset: 0x17EC size: 32 bit */
18942   
18943           /* SPP_DMA2_TCDn Word4 - daddr */
18944           SPP_DMA2_TCDWORD16__32B_tag TCDWORD16_63;/* offset: 0x17F0 size: 32 bit */
18945   
18946           /* SPP_DMA2_TCDn Word5 -  citer.e_link, citer, doff */
18947           SPP_DMA2_TCDWORD20__32B_tag TCDWORD20_63;/* offset: 0x17F4 size: 32 bit */
18948   
18949           /* SPP_DMA2_TCDn Word6 -  dlast_sga */
18950           SPP_DMA2_TCDWORD24__32B_tag TCDWORD24_63;/* offset: 0x17F8 size: 32 bit */
18951   
18952           /* SPP_DMA2_TCDn Word7 -  biter, etc. */
18953           SPP_DMA2_TCDWORD28__32B_tag TCDWORD28_63;/* offset: 0x17FC size: 32 bit */
18954         };
18955       };
18956   
18957       int8_t SPP_DMA2_reserved_1800[10240];
18958     } SPP_DMA2_tag;
18959   
18960   #define SPP_DMA2                       (*(volatile SPP_DMA2_tag *) 0xFFF44000UL)
18961   
18962     /****************************************************************/
18963     /*                                                              */
18964     /* Module: INTC  */
18965     /*                                                              */
18966     /****************************************************************/
18967     typedef union {                      /* BCR - Block Configuration Register */
18968       vuint32_t R;
18969       struct {
18970        vuint32_t:
18971         18;
18972         vuint32_t VTES_PRC1:1;           /* Vector Table Entry Size - Processor 1 */
18973        vuint32_t:
18974         4;
18975         vuint32_t HVEN_PRC1:1;           /* Hardware Vector Enable - Processor 1 */
18976        vuint32_t:
18977         2;
18978   
18979   #ifndef USE_FIELD_ALIASES_INTC
18980   
18981         vuint32_t VTES_PRC0:1;           /* Vector Table Entry Size - Processor 0 */
18982   
18983   #else
18984   
18985         vuint32_t VTES:1;                /* deprecated name - please avoid */
18986   
18987   #endif
18988   
18989        vuint32_t:
18990         4;
18991   
18992   #ifndef USE_FIELD_ALIASES_INTC
18993   
18994         vuint32_t HVEN_PRC0:1;           /* Hardware Vector Enable - Processor 0 */
18995   
18996   #else
18997   
18998         vuint32_t HVEN:1;                /* deprecated name - please avoid */
18999   
19000   #endif
19001   
19002       } B;
19003     } INTC_BCR_32B_tag;
19004   
19005     typedef union {                      /* CPR - Current Priority Register - Processor 0 */
19006       vuint32_t R;
19007       struct {
19008        vuint32_t:
19009         28;
19010         vuint32_t PRI:4;                 /* Priority Bits */
19011       } B;
19012     } INTC_CPR_PRC0_32B_tag;
19013   
19014     typedef union {                      /* CPR - Current Priority Register - Processor 1 */
19015       vuint32_t R;
19016       struct {
19017        vuint32_t:
19018         28;
19019         vuint32_t PRI:4;                 /* Priority Bits */
19020       } B;
19021     } INTC_CPR_PRC1_32B_tag;
19022   
19023     typedef union {                      /* IACKR- Interrupt Acknowledge Register - Processor 0 */
19024       vuint32_t R;
19025       struct {
19026   
19027   #ifndef USE_FIELD_ALIASES_INTC
19028   
19029         vuint32_t VTBA_PRC0:21;          /* Vector Table Base Address - Processor 0 */
19030   
19031   #else
19032   
19033         vuint32_t VTBA:21;               /* deprecated name - please avoid */
19034   
19035   #endif
19036   
19037   #ifndef USE_FIELD_ALIASES_INTC
19038   
19039         vuint32_t INTEC_PRC0:9;          /* Interrupt Vector - Processor 0 */
19040   
19041   #else
19042   
19043         vuint32_t INTVEC:9;              /* deprecated name - please avoid */
19044   
19045   #endif
19046   
19047        vuint32_t:
19048         2;
19049       } B;
19050     } INTC_IACKR_PRC0_32B_tag;
19051   
19052     typedef union {                      /* IACKR- Interrupt Acknowledge Register - Processor 1 */
19053       vuint32_t R;
19054       struct {
19055         vuint32_t VTBA_PRC1:21;          /* Vector Table Base Address - Processor 1 */
19056         vuint32_t INTEC_PRC1:9;          /* Interrupt Vector - Processor 1 */
19057        vuint32_t:
19058         2;
19059       } B;
19060     } INTC_IACKR_PRC1_32B_tag;
19061   
19062     typedef union {                      /* EOIR- End of Interrupt Register - Processor 0 */
19063       vuint32_t R;
19064     } INTC_EOIR_PRC0_32B_tag;
19065   
19066     typedef union {                      /* EOIR- End of Interrupt Register - Processor 1 */
19067       vuint32_t R;
19068     } INTC_EOIR_PRC1_32B_tag;
19069   
19070     /* Register layout for all registers SSCIR ... */
19071     typedef union {                      /* SSCIR0-7 INTC Software Set/Clear Interrupt Registers */
19072       vuint8_t R;
19073       struct {
19074        vuint8_t:
19075         6;
19076         vuint8_t SET:1;                  /* Set Flag bit */
19077         vuint8_t CLR:1;                  /* Clear Flag bit */
19078       } B;
19079     } INTC_SSCIR_8B_tag;
19080   
19081     typedef union {                      /* SSCIR0_3 - Software Set/Clear Interrupt Registers */
19082       vuint32_t R;
19083       struct {
19084        vuint32_t:
19085         6;
19086         vuint32_t SET0:1;                /* Set Flag 0 bit */
19087         vuint32_t CLR0:1;                /* Clear Flag 0 bit */
19088        vuint32_t:
19089         6;
19090         vuint32_t SET1:1;                /* Set Flag 1 bit */
19091         vuint32_t CLR1:1;                /* Clear Flag 1 bit */
19092        vuint32_t:
19093         6;
19094         vuint32_t SET2:1;                /* Set Flag 2 bit */
19095         vuint32_t CLR2:1;                /* Clear Flag 2 bit */
19096        vuint32_t:
19097         6;
19098         vuint32_t SET3:1;                /* Set Flag 3 bit */
19099         vuint32_t CLR3:1;                /* Clear Flag 3 bit */
19100       } B;
19101     } INTC_SSCIR0_3_32B_tag;
19102   
19103     typedef union {                      /* SSCIR4_7 - Software Set/Clear Interrupt Registers */
19104       vuint32_t R;
19105       struct {
19106        vuint32_t:
19107         6;
19108         vuint32_t SET4:1;                /* Set Flag 4 bit */
19109         vuint32_t CLR4:1;                /* Clear Flag 4 bit */
19110        vuint32_t:
19111         6;
19112         vuint32_t SET5:1;                /* Set Flag 5 bit */
19113         vuint32_t CLR5:1;                /* Clear Flag 5 bit */
19114        vuint32_t:
19115         6;
19116         vuint32_t SET6:1;                /* Set Flag 6 bit */
19117         vuint32_t CLR6:1;                /* Clear Flag 6 bit */
19118        vuint32_t:
19119         6;
19120         vuint32_t SET7:1;                /* Set Flag 7 bit */
19121         vuint32_t CLR7:1;                /* Clear Flag 7 bit */
19122       } B;
19123     } INTC_SSCIR4_7_32B_tag;
19124   
19125     /* Register layout for all registers PSR ... */
19126     typedef union {                      /* PSR0-511 - Priority Select Registers */
19127       vuint8_t R;
19128       struct {
19129         vuint8_t PRC_SEL:2;              /* Processor Select */
19130        vuint8_t:
19131         2;
19132         vuint8_t PRI:4;                  /* Priority Select */
19133       } B;
19134     } INTC_PSR_8B_tag;
19135   
19136     /* Register layout for all registers PSR ... */
19137     typedef union {                      /* PSR0_3 - 508_511 - Priority Select Registers */
19138       vuint32_t R;
19139       struct {
19140         vuint32_t PRC_SEL0:2;            /* Processor Select - Entry 0 */
19141        vuint32_t:
19142         2;
19143         vuint32_t PRI0:4;                /* Priority Select - Entry 0 */
19144         vuint32_t PRC_SEL1:2;            /* Processor Select - Entry 1 */
19145        vuint32_t:
19146         2;
19147         vuint32_t PRI1:4;                /* Priority Select - Entry 1 */
19148         vuint32_t PRC_SEL2:2;            /* Processor Select - Entry 2 */
19149        vuint32_t:
19150         2;
19151         vuint32_t PRI2:4;                /* Priority Select - Entry 2 */
19152         vuint32_t PRC_SEL3:2;            /* Processor Select - Entry 3 */
19153        vuint32_t:
19154         2;
19155         vuint32_t PRI3:4;                /* Priority Select - Entry 3 */
19156       } B;
19157     } INTC_PSR_32B_tag;
19158   
19159     typedef struct INTC_struct_tag {
19160       union {
19161         /* BCR - Block Configuration Register */
19162         INTC_BCR_32B_tag BCR;            /* offset: 0x0000 size: 32 bit */
19163         INTC_BCR_32B_tag MCR;            /* deprecated - please avoid */
19164       };
19165   
19166       int8_t INTC_reserved_0004[4];
19167       union {
19168         /* CPR - Current Priority Register - Processor 0 */
19169         INTC_CPR_PRC0_32B_tag CPR_PRC0;  /* offset: 0x0008 size: 32 bit */
19170         INTC_CPR_PRC0_32B_tag CPR;       /* deprecated - please avoid */
19171       };
19172   
19173       /* CPR - Current Priority Register - Processor 1 */
19174       INTC_CPR_PRC1_32B_tag CPR_PRC1;    /* offset: 0x000C size: 32 bit */
19175       union {
19176         /* IACKR- Interrupt Acknowledge Register - Processor 0 */
19177         INTC_IACKR_PRC0_32B_tag IACKR_PRC0;/* offset: 0x0010 size: 32 bit */
19178         INTC_IACKR_PRC0_32B_tag IACKR;   /* deprecated - please avoid */
19179       };
19180   
19181       /* IACKR- Interrupt Acknowledge Register - Processor 1 */
19182       INTC_IACKR_PRC1_32B_tag IACKR_PRC1;/* offset: 0x0014 size: 32 bit */
19183       union {
19184         /* EOIR- End of Interrupt Register - Processor 0 */
19185         INTC_EOIR_PRC0_32B_tag EOIR_PRC0;/* offset: 0x0018 size: 32 bit */
19186         INTC_EOIR_PRC0_32B_tag EOIR;     /* deprecated - please avoid */
19187       };
19188   
19189       /* EOIR- End of Interrupt Register - Processor 1 */
19190       INTC_EOIR_PRC1_32B_tag EOIR_PRC1;  /* offset: 0x001C size: 32 bit */
19191       union {
19192         /* SSCIR0-7 INTC Software Set/Clear Interrupt Registers */
19193         INTC_SSCIR_8B_tag SSCIR[8];      /* offset: 0x0020  (0x0001 x 8) */
19194         struct {
19195           /* SSCIR0-7 INTC Software Set/Clear Interrupt Registers */
19196           INTC_SSCIR_8B_tag SSCIR0;      /* offset: 0x0020 size: 8 bit */
19197           INTC_SSCIR_8B_tag SSCIR1;      /* offset: 0x0021 size: 8 bit */
19198           INTC_SSCIR_8B_tag SSCIR2;      /* offset: 0x0022 size: 8 bit */
19199           INTC_SSCIR_8B_tag SSCIR3;      /* offset: 0x0023 size: 8 bit */
19200           INTC_SSCIR_8B_tag SSCIR4;      /* offset: 0x0024 size: 8 bit */
19201           INTC_SSCIR_8B_tag SSCIR5;      /* offset: 0x0025 size: 8 bit */
19202           INTC_SSCIR_8B_tag SSCIR6;      /* offset: 0x0026 size: 8 bit */
19203           INTC_SSCIR_8B_tag SSCIR7;      /* offset: 0x0027 size: 8 bit */
19204         };
19205   
19206         struct {
19207           /* SSCIR0_3 - Software Set/Clear Interrupt Registers */
19208           INTC_SSCIR0_3_32B_tag SSCIR0_3;/* offset: 0x0020 size: 32 bit */
19209   
19210           /* SSCIR4_7 - Software Set/Clear Interrupt Registers */
19211           INTC_SSCIR4_7_32B_tag SSCIR4_7;/* offset: 0x0024 size: 32 bit */
19212         };
19213       };
19214   
19215       int8_t INTC_reserved_0028[24];
19216       union {
19217         /* PSR0_3 - 508_511 - Priority Select Registers */
19218         INTC_PSR_32B_tag PSR_32B[128];   /* offset: 0x0040  (0x0004 x 128) */
19219   
19220         /* PSR0-511 - Priority Select Registers */
19221         INTC_PSR_8B_tag PSR[512];        /* offset: 0x0040  (0x0001 x 512) */
19222         struct {
19223           /* PSR0_3 - 508_511 - Priority Select Registers */
19224           INTC_PSR_32B_tag PSR0_3;       /* offset: 0x0040 size: 32 bit */
19225           INTC_PSR_32B_tag PSR4_7;       /* offset: 0x0044 size: 32 bit */
19226           INTC_PSR_32B_tag PSR8_11;      /* offset: 0x0048 size: 32 bit */
19227           INTC_PSR_32B_tag PSR12_15;     /* offset: 0x004C size: 32 bit */
19228           INTC_PSR_32B_tag PSR16_19;     /* offset: 0x0050 size: 32 bit */
19229           INTC_PSR_32B_tag PSR20_23;     /* offset: 0x0054 size: 32 bit */
19230           INTC_PSR_32B_tag PSR24_27;     /* offset: 0x0058 size: 32 bit */
19231           INTC_PSR_32B_tag PSR28_31;     /* offset: 0x005C size: 32 bit */
19232           INTC_PSR_32B_tag PSR32_35;     /* offset: 0x0060 size: 32 bit */
19233           INTC_PSR_32B_tag PSR36_39;     /* offset: 0x0064 size: 32 bit */
19234           INTC_PSR_32B_tag PSR40_43;     /* offset: 0x0068 size: 32 bit */
19235           INTC_PSR_32B_tag PSR44_47;     /* offset: 0x006C size: 32 bit */
19236           INTC_PSR_32B_tag PSR48_51;     /* offset: 0x0070 size: 32 bit */
19237           INTC_PSR_32B_tag PSR52_55;     /* offset: 0x0074 size: 32 bit */
19238           INTC_PSR_32B_tag PSR56_59;     /* offset: 0x0078 size: 32 bit */
19239           INTC_PSR_32B_tag PSR60_63;     /* offset: 0x007C size: 32 bit */
19240           INTC_PSR_32B_tag PSR64_67;     /* offset: 0x0080 size: 32 bit */
19241           INTC_PSR_32B_tag PSR68_71;     /* offset: 0x0084 size: 32 bit */
19242           INTC_PSR_32B_tag PSR72_75;     /* offset: 0x0088 size: 32 bit */
19243           INTC_PSR_32B_tag PSR76_79;     /* offset: 0x008C size: 32 bit */
19244           INTC_PSR_32B_tag PSR80_83;     /* offset: 0x0090 size: 32 bit */
19245           INTC_PSR_32B_tag PSR84_87;     /* offset: 0x0094 size: 32 bit */
19246           INTC_PSR_32B_tag PSR88_91;     /* offset: 0x0098 size: 32 bit */
19247           INTC_PSR_32B_tag PSR92_95;     /* offset: 0x009C size: 32 bit */
19248           INTC_PSR_32B_tag PSR96_99;     /* offset: 0x00A0 size: 32 bit */
19249           INTC_PSR_32B_tag PSR100_103;   /* offset: 0x00A4 size: 32 bit */
19250           INTC_PSR_32B_tag PSR104_107;   /* offset: 0x00A8 size: 32 bit */
19251           INTC_PSR_32B_tag PSR108_111;   /* offset: 0x00AC size: 32 bit */
19252           INTC_PSR_32B_tag PSR112_115;   /* offset: 0x00B0 size: 32 bit */
19253           INTC_PSR_32B_tag PSR116_119;   /* offset: 0x00B4 size: 32 bit */
19254           INTC_PSR_32B_tag PSR120_123;   /* offset: 0x00B8 size: 32 bit */
19255           INTC_PSR_32B_tag PSR124_127;   /* offset: 0x00BC size: 32 bit */
19256           INTC_PSR_32B_tag PSR128_131;   /* offset: 0x00C0 size: 32 bit */
19257           INTC_PSR_32B_tag PSR132_135;   /* offset: 0x00C4 size: 32 bit */
19258           INTC_PSR_32B_tag PSR136_139;   /* offset: 0x00C8 size: 32 bit */
19259           INTC_PSR_32B_tag PSR140_143;   /* offset: 0x00CC size: 32 bit */
19260           INTC_PSR_32B_tag PSR144_147;   /* offset: 0x00D0 size: 32 bit */
19261           INTC_PSR_32B_tag PSR148_151;   /* offset: 0x00D4 size: 32 bit */
19262           INTC_PSR_32B_tag PSR152_155;   /* offset: 0x00D8 size: 32 bit */
19263           INTC_PSR_32B_tag PSR156_159;   /* offset: 0x00DC size: 32 bit */
19264           INTC_PSR_32B_tag PSR160_163;   /* offset: 0x00E0 size: 32 bit */
19265           INTC_PSR_32B_tag PSR164_167;   /* offset: 0x00E4 size: 32 bit */
19266           INTC_PSR_32B_tag PSR168_171;   /* offset: 0x00E8 size: 32 bit */
19267           INTC_PSR_32B_tag PSR172_175;   /* offset: 0x00EC size: 32 bit */
19268           INTC_PSR_32B_tag PSR176_179;   /* offset: 0x00F0 size: 32 bit */
19269           INTC_PSR_32B_tag PSR180_183;   /* offset: 0x00F4 size: 32 bit */
19270           INTC_PSR_32B_tag PSR184_187;   /* offset: 0x00F8 size: 32 bit */
19271           INTC_PSR_32B_tag PSR188_191;   /* offset: 0x00FC size: 32 bit */
19272           INTC_PSR_32B_tag PSR192_195;   /* offset: 0x0100 size: 32 bit */
19273           INTC_PSR_32B_tag PSR196_199;   /* offset: 0x0104 size: 32 bit */
19274           INTC_PSR_32B_tag PSR200_203;   /* offset: 0x0108 size: 32 bit */
19275           INTC_PSR_32B_tag PSR204_207;   /* offset: 0x010C size: 32 bit */
19276           INTC_PSR_32B_tag PSR208_211;   /* offset: 0x0110 size: 32 bit */
19277           INTC_PSR_32B_tag PSR212_215;   /* offset: 0x0114 size: 32 bit */
19278           INTC_PSR_32B_tag PSR216_219;   /* offset: 0x0118 size: 32 bit */
19279           INTC_PSR_32B_tag PSR220_223;   /* offset: 0x011C size: 32 bit */
19280           INTC_PSR_32B_tag PSR224_227;   /* offset: 0x0120 size: 32 bit */
19281           INTC_PSR_32B_tag PSR228_231;   /* offset: 0x0124 size: 32 bit */
19282           INTC_PSR_32B_tag PSR232_235;   /* offset: 0x0128 size: 32 bit */
19283           INTC_PSR_32B_tag PSR236_239;   /* offset: 0x012C size: 32 bit */
19284           INTC_PSR_32B_tag PSR240_243;   /* offset: 0x0130 size: 32 bit */
19285           INTC_PSR_32B_tag PSR244_247;   /* offset: 0x0134 size: 32 bit */
19286           INTC_PSR_32B_tag PSR248_251;   /* offset: 0x0138 size: 32 bit */
19287           INTC_PSR_32B_tag PSR252_255;   /* offset: 0x013C size: 32 bit */
19288           INTC_PSR_32B_tag PSR256_259;   /* offset: 0x0140 size: 32 bit */
19289           INTC_PSR_32B_tag PSR260_263;   /* offset: 0x0144 size: 32 bit */
19290           INTC_PSR_32B_tag PSR264_267;   /* offset: 0x0148 size: 32 bit */
19291           INTC_PSR_32B_tag PSR268_271;   /* offset: 0x014C size: 32 bit */
19292           INTC_PSR_32B_tag PSR272_275;   /* offset: 0x0150 size: 32 bit */
19293           INTC_PSR_32B_tag PSR276_279;   /* offset: 0x0154 size: 32 bit */
19294           INTC_PSR_32B_tag PSR280_283;   /* offset: 0x0158 size: 32 bit */
19295           INTC_PSR_32B_tag PSR284_287;   /* offset: 0x015C size: 32 bit */
19296           INTC_PSR_32B_tag PSR288_291;   /* offset: 0x0160 size: 32 bit */
19297           INTC_PSR_32B_tag PSR292_295;   /* offset: 0x0164 size: 32 bit */
19298           INTC_PSR_32B_tag PSR296_299;   /* offset: 0x0168 size: 32 bit */
19299           INTC_PSR_32B_tag PSR300_303;   /* offset: 0x016C size: 32 bit */
19300           INTC_PSR_32B_tag PSR304_307;   /* offset: 0x0170 size: 32 bit */
19301           INTC_PSR_32B_tag PSR308_311;   /* offset: 0x0174 size: 32 bit */
19302           INTC_PSR_32B_tag PSR312_315;   /* offset: 0x0178 size: 32 bit */
19303           INTC_PSR_32B_tag PSR316_319;   /* offset: 0x017C size: 32 bit */
19304           INTC_PSR_32B_tag PSR320_323;   /* offset: 0x0180 size: 32 bit */
19305           INTC_PSR_32B_tag PSR324_327;   /* offset: 0x0184 size: 32 bit */
19306           INTC_PSR_32B_tag PSR328_331;   /* offset: 0x0188 size: 32 bit */
19307           INTC_PSR_32B_tag PSR332_335;   /* offset: 0x018C size: 32 bit */
19308           INTC_PSR_32B_tag PSR336_339;   /* offset: 0x0190 size: 32 bit */
19309           INTC_PSR_32B_tag PSR340_343;   /* offset: 0x0194 size: 32 bit */
19310           INTC_PSR_32B_tag PSR344_347;   /* offset: 0x0198 size: 32 bit */
19311           INTC_PSR_32B_tag PSR348_351;   /* offset: 0x019C size: 32 bit */
19312           INTC_PSR_32B_tag PSR352_355;   /* offset: 0x01A0 size: 32 bit */
19313           INTC_PSR_32B_tag PSR356_359;   /* offset: 0x01A4 size: 32 bit */
19314           INTC_PSR_32B_tag PSR360_363;   /* offset: 0x01A8 size: 32 bit */
19315           INTC_PSR_32B_tag PSR364_367;   /* offset: 0x01AC size: 32 bit */
19316           INTC_PSR_32B_tag PSR368_371;   /* offset: 0x01B0 size: 32 bit */
19317           INTC_PSR_32B_tag PSR372_375;   /* offset: 0x01B4 size: 32 bit */
19318           INTC_PSR_32B_tag PSR376_379;   /* offset: 0x01B8 size: 32 bit */
19319           INTC_PSR_32B_tag PSR380_383;   /* offset: 0x01BC size: 32 bit */
19320           INTC_PSR_32B_tag PSR384_387;   /* offset: 0x01C0 size: 32 bit */
19321           INTC_PSR_32B_tag PSR388_391;   /* offset: 0x01C4 size: 32 bit */
19322           INTC_PSR_32B_tag PSR392_395;   /* offset: 0x01C8 size: 32 bit */
19323           INTC_PSR_32B_tag PSR396_399;   /* offset: 0x01CC size: 32 bit */
19324           INTC_PSR_32B_tag PSR400_403;   /* offset: 0x01D0 size: 32 bit */
19325           INTC_PSR_32B_tag PSR404_407;   /* offset: 0x01D4 size: 32 bit */
19326           INTC_PSR_32B_tag PSR408_411;   /* offset: 0x01D8 size: 32 bit */
19327           INTC_PSR_32B_tag PSR412_415;   /* offset: 0x01DC size: 32 bit */
19328           INTC_PSR_32B_tag PSR416_419;   /* offset: 0x01E0 size: 32 bit */
19329           INTC_PSR_32B_tag PSR420_423;   /* offset: 0x01E4 size: 32 bit */
19330           INTC_PSR_32B_tag PSR424_427;   /* offset: 0x01E8 size: 32 bit */
19331           INTC_PSR_32B_tag PSR428_431;   /* offset: 0x01EC size: 32 bit */
19332           INTC_PSR_32B_tag PSR432_435;   /* offset: 0x01F0 size: 32 bit */
19333           INTC_PSR_32B_tag PSR436_439;   /* offset: 0x01F4 size: 32 bit */
19334           INTC_PSR_32B_tag PSR440_443;   /* offset: 0x01F8 size: 32 bit */
19335           INTC_PSR_32B_tag PSR444_447;   /* offset: 0x01FC size: 32 bit */
19336           INTC_PSR_32B_tag PSR448_451;   /* offset: 0x0200 size: 32 bit */
19337           INTC_PSR_32B_tag PSR452_455;   /* offset: 0x0204 size: 32 bit */
19338           INTC_PSR_32B_tag PSR456_459;   /* offset: 0x0208 size: 32 bit */
19339           INTC_PSR_32B_tag PSR460_463;   /* offset: 0x020C size: 32 bit */
19340           INTC_PSR_32B_tag PSR464_467;   /* offset: 0x0210 size: 32 bit */
19341           INTC_PSR_32B_tag PSR468_471;   /* offset: 0x0214 size: 32 bit */
19342           INTC_PSR_32B_tag PSR472_475;   /* offset: 0x0218 size: 32 bit */
19343           INTC_PSR_32B_tag PSR476_479;   /* offset: 0x021C size: 32 bit */
19344           INTC_PSR_32B_tag PSR480_483;   /* offset: 0x0220 size: 32 bit */
19345           INTC_PSR_32B_tag PSR484_487;   /* offset: 0x0224 size: 32 bit */
19346           INTC_PSR_32B_tag PSR488_491;   /* offset: 0x0228 size: 32 bit */
19347           INTC_PSR_32B_tag PSR492_495;   /* offset: 0x022C size: 32 bit */
19348           INTC_PSR_32B_tag PSR496_499;   /* offset: 0x0230 size: 32 bit */
19349           INTC_PSR_32B_tag PSR500_503;   /* offset: 0x0234 size: 32 bit */
19350           INTC_PSR_32B_tag PSR504_507;   /* offset: 0x0238 size: 32 bit */
19351           INTC_PSR_32B_tag PSR508_511;   /* offset: 0x023C size: 32 bit */
19352         };
19353   
19354         struct {
19355           /* PSR0-511 - Priority Select Registers */
19356           INTC_PSR_8B_tag PSR0;          /* offset: 0x0040 size: 8 bit */
19357           INTC_PSR_8B_tag PSR1;          /* offset: 0x0041 size: 8 bit */
19358           INTC_PSR_8B_tag PSR2;          /* offset: 0x0042 size: 8 bit */
19359           INTC_PSR_8B_tag PSR3;          /* offset: 0x0043 size: 8 bit */
19360           INTC_PSR_8B_tag PSR4;          /* offset: 0x0044 size: 8 bit */
19361           INTC_PSR_8B_tag PSR5;          /* offset: 0x0045 size: 8 bit */
19362           INTC_PSR_8B_tag PSR6;          /* offset: 0x0046 size: 8 bit */
19363           INTC_PSR_8B_tag PSR7;          /* offset: 0x0047 size: 8 bit */
19364           INTC_PSR_8B_tag PSR8;          /* offset: 0x0048 size: 8 bit */
19365           INTC_PSR_8B_tag PSR9;          /* offset: 0x0049 size: 8 bit */
19366           INTC_PSR_8B_tag PSR10;         /* offset: 0x004A size: 8 bit */
19367           INTC_PSR_8B_tag PSR11;         /* offset: 0x004B size: 8 bit */
19368           INTC_PSR_8B_tag PSR12;         /* offset: 0x004C size: 8 bit */
19369           INTC_PSR_8B_tag PSR13;         /* offset: 0x004D size: 8 bit */
19370           INTC_PSR_8B_tag PSR14;         /* offset: 0x004E size: 8 bit */
19371           INTC_PSR_8B_tag PSR15;         /* offset: 0x004F size: 8 bit */
19372           INTC_PSR_8B_tag PSR16;         /* offset: 0x0050 size: 8 bit */
19373           INTC_PSR_8B_tag PSR17;         /* offset: 0x0051 size: 8 bit */
19374           INTC_PSR_8B_tag PSR18;         /* offset: 0x0052 size: 8 bit */
19375           INTC_PSR_8B_tag PSR19;         /* offset: 0x0053 size: 8 bit */
19376           INTC_PSR_8B_tag PSR20;         /* offset: 0x0054 size: 8 bit */
19377           INTC_PSR_8B_tag PSR21;         /* offset: 0x0055 size: 8 bit */
19378           INTC_PSR_8B_tag PSR22;         /* offset: 0x0056 size: 8 bit */
19379           INTC_PSR_8B_tag PSR23;         /* offset: 0x0057 size: 8 bit */
19380           INTC_PSR_8B_tag PSR24;         /* offset: 0x0058 size: 8 bit */
19381           INTC_PSR_8B_tag PSR25;         /* offset: 0x0059 size: 8 bit */
19382           INTC_PSR_8B_tag PSR26;         /* offset: 0x005A size: 8 bit */
19383           INTC_PSR_8B_tag PSR27;         /* offset: 0x005B size: 8 bit */
19384           INTC_PSR_8B_tag PSR28;         /* offset: 0x005C size: 8 bit */
19385           INTC_PSR_8B_tag PSR29;         /* offset: 0x005D size: 8 bit */
19386           INTC_PSR_8B_tag PSR30;         /* offset: 0x005E size: 8 bit */
19387           INTC_PSR_8B_tag PSR31;         /* offset: 0x005F size: 8 bit */
19388           INTC_PSR_8B_tag PSR32;         /* offset: 0x0060 size: 8 bit */
19389           INTC_PSR_8B_tag PSR33;         /* offset: 0x0061 size: 8 bit */
19390           INTC_PSR_8B_tag PSR34;         /* offset: 0x0062 size: 8 bit */
19391           INTC_PSR_8B_tag PSR35;         /* offset: 0x0063 size: 8 bit */
19392           INTC_PSR_8B_tag PSR36;         /* offset: 0x0064 size: 8 bit */
19393           INTC_PSR_8B_tag PSR37;         /* offset: 0x0065 size: 8 bit */
19394           INTC_PSR_8B_tag PSR38;         /* offset: 0x0066 size: 8 bit */
19395           INTC_PSR_8B_tag PSR39;         /* offset: 0x0067 size: 8 bit */
19396           INTC_PSR_8B_tag PSR40;         /* offset: 0x0068 size: 8 bit */
19397           INTC_PSR_8B_tag PSR41;         /* offset: 0x0069 size: 8 bit */
19398           INTC_PSR_8B_tag PSR42;         /* offset: 0x006A size: 8 bit */
19399           INTC_PSR_8B_tag PSR43;         /* offset: 0x006B size: 8 bit */
19400           INTC_PSR_8B_tag PSR44;         /* offset: 0x006C size: 8 bit */
19401           INTC_PSR_8B_tag PSR45;         /* offset: 0x006D size: 8 bit */
19402           INTC_PSR_8B_tag PSR46;         /* offset: 0x006E size: 8 bit */
19403           INTC_PSR_8B_tag PSR47;         /* offset: 0x006F size: 8 bit */
19404           INTC_PSR_8B_tag PSR48;         /* offset: 0x0070 size: 8 bit */
19405           INTC_PSR_8B_tag PSR49;         /* offset: 0x0071 size: 8 bit */
19406           INTC_PSR_8B_tag PSR50;         /* offset: 0x0072 size: 8 bit */
19407           INTC_PSR_8B_tag PSR51;         /* offset: 0x0073 size: 8 bit */
19408           INTC_PSR_8B_tag PSR52;         /* offset: 0x0074 size: 8 bit */
19409           INTC_PSR_8B_tag PSR53;         /* offset: 0x0075 size: 8 bit */
19410           INTC_PSR_8B_tag PSR54;         /* offset: 0x0076 size: 8 bit */
19411           INTC_PSR_8B_tag PSR55;         /* offset: 0x0077 size: 8 bit */
19412           INTC_PSR_8B_tag PSR56;         /* offset: 0x0078 size: 8 bit */
19413           INTC_PSR_8B_tag PSR57;         /* offset: 0x0079 size: 8 bit */
19414           INTC_PSR_8B_tag PSR58;         /* offset: 0x007A size: 8 bit */
19415           INTC_PSR_8B_tag PSR59;         /* offset: 0x007B size: 8 bit */
19416           INTC_PSR_8B_tag PSR60;         /* offset: 0x007C size: 8 bit */
19417           INTC_PSR_8B_tag PSR61;         /* offset: 0x007D size: 8 bit */
19418           INTC_PSR_8B_tag PSR62;         /* offset: 0x007E size: 8 bit */
19419           INTC_PSR_8B_tag PSR63;         /* offset: 0x007F size: 8 bit */
19420           INTC_PSR_8B_tag PSR64;         /* offset: 0x0080 size: 8 bit */
19421           INTC_PSR_8B_tag PSR65;         /* offset: 0x0081 size: 8 bit */
19422           INTC_PSR_8B_tag PSR66;         /* offset: 0x0082 size: 8 bit */
19423           INTC_PSR_8B_tag PSR67;         /* offset: 0x0083 size: 8 bit */
19424           INTC_PSR_8B_tag PSR68;         /* offset: 0x0084 size: 8 bit */
19425           INTC_PSR_8B_tag PSR69;         /* offset: 0x0085 size: 8 bit */
19426           INTC_PSR_8B_tag PSR70;         /* offset: 0x0086 size: 8 bit */
19427           INTC_PSR_8B_tag PSR71;         /* offset: 0x0087 size: 8 bit */
19428           INTC_PSR_8B_tag PSR72;         /* offset: 0x0088 size: 8 bit */
19429           INTC_PSR_8B_tag PSR73;         /* offset: 0x0089 size: 8 bit */
19430           INTC_PSR_8B_tag PSR74;         /* offset: 0x008A size: 8 bit */
19431           INTC_PSR_8B_tag PSR75;         /* offset: 0x008B size: 8 bit */
19432           INTC_PSR_8B_tag PSR76;         /* offset: 0x008C size: 8 bit */
19433           INTC_PSR_8B_tag PSR77;         /* offset: 0x008D size: 8 bit */
19434           INTC_PSR_8B_tag PSR78;         /* offset: 0x008E size: 8 bit */
19435           INTC_PSR_8B_tag PSR79;         /* offset: 0x008F size: 8 bit */
19436           INTC_PSR_8B_tag PSR80;         /* offset: 0x0090 size: 8 bit */
19437           INTC_PSR_8B_tag PSR81;         /* offset: 0x0091 size: 8 bit */
19438           INTC_PSR_8B_tag PSR82;         /* offset: 0x0092 size: 8 bit */
19439           INTC_PSR_8B_tag PSR83;         /* offset: 0x0093 size: 8 bit */
19440           INTC_PSR_8B_tag PSR84;         /* offset: 0x0094 size: 8 bit */
19441           INTC_PSR_8B_tag PSR85;         /* offset: 0x0095 size: 8 bit */
19442           INTC_PSR_8B_tag PSR86;         /* offset: 0x0096 size: 8 bit */
19443           INTC_PSR_8B_tag PSR87;         /* offset: 0x0097 size: 8 bit */
19444           INTC_PSR_8B_tag PSR88;         /* offset: 0x0098 size: 8 bit */
19445           INTC_PSR_8B_tag PSR89;         /* offset: 0x0099 size: 8 bit */
19446           INTC_PSR_8B_tag PSR90;         /* offset: 0x009A size: 8 bit */
19447           INTC_PSR_8B_tag PSR91;         /* offset: 0x009B size: 8 bit */
19448           INTC_PSR_8B_tag PSR92;         /* offset: 0x009C size: 8 bit */
19449           INTC_PSR_8B_tag PSR93;         /* offset: 0x009D size: 8 bit */
19450           INTC_PSR_8B_tag PSR94;         /* offset: 0x009E size: 8 bit */
19451           INTC_PSR_8B_tag PSR95;         /* offset: 0x009F size: 8 bit */
19452           INTC_PSR_8B_tag PSR96;         /* offset: 0x00A0 size: 8 bit */
19453           INTC_PSR_8B_tag PSR97;         /* offset: 0x00A1 size: 8 bit */
19454           INTC_PSR_8B_tag PSR98;         /* offset: 0x00A2 size: 8 bit */
19455           INTC_PSR_8B_tag PSR99;         /* offset: 0x00A3 size: 8 bit */
19456           INTC_PSR_8B_tag PSR100;        /* offset: 0x00A4 size: 8 bit */
19457           INTC_PSR_8B_tag PSR101;        /* offset: 0x00A5 size: 8 bit */
19458           INTC_PSR_8B_tag PSR102;        /* offset: 0x00A6 size: 8 bit */
19459           INTC_PSR_8B_tag PSR103;        /* offset: 0x00A7 size: 8 bit */
19460           INTC_PSR_8B_tag PSR104;        /* offset: 0x00A8 size: 8 bit */
19461           INTC_PSR_8B_tag PSR105;        /* offset: 0x00A9 size: 8 bit */
19462           INTC_PSR_8B_tag PSR106;        /* offset: 0x00AA size: 8 bit */
19463           INTC_PSR_8B_tag PSR107;        /* offset: 0x00AB size: 8 bit */
19464           INTC_PSR_8B_tag PSR108;        /* offset: 0x00AC size: 8 bit */
19465           INTC_PSR_8B_tag PSR109;        /* offset: 0x00AD size: 8 bit */
19466           INTC_PSR_8B_tag PSR110;        /* offset: 0x00AE size: 8 bit */
19467           INTC_PSR_8B_tag PSR111;        /* offset: 0x00AF size: 8 bit */
19468           INTC_PSR_8B_tag PSR112;        /* offset: 0x00B0 size: 8 bit */
19469           INTC_PSR_8B_tag PSR113;        /* offset: 0x00B1 size: 8 bit */
19470           INTC_PSR_8B_tag PSR114;        /* offset: 0x00B2 size: 8 bit */
19471           INTC_PSR_8B_tag PSR115;        /* offset: 0x00B3 size: 8 bit */
19472           INTC_PSR_8B_tag PSR116;        /* offset: 0x00B4 size: 8 bit */
19473           INTC_PSR_8B_tag PSR117;        /* offset: 0x00B5 size: 8 bit */
19474           INTC_PSR_8B_tag PSR118;        /* offset: 0x00B6 size: 8 bit */
19475           INTC_PSR_8B_tag PSR119;        /* offset: 0x00B7 size: 8 bit */
19476           INTC_PSR_8B_tag PSR120;        /* offset: 0x00B8 size: 8 bit */
19477           INTC_PSR_8B_tag PSR121;        /* offset: 0x00B9 size: 8 bit */
19478           INTC_PSR_8B_tag PSR122;        /* offset: 0x00BA size: 8 bit */
19479           INTC_PSR_8B_tag PSR123;        /* offset: 0x00BB size: 8 bit */
19480           INTC_PSR_8B_tag PSR124;        /* offset: 0x00BC size: 8 bit */
19481           INTC_PSR_8B_tag PSR125;        /* offset: 0x00BD size: 8 bit */
19482           INTC_PSR_8B_tag PSR126;        /* offset: 0x00BE size: 8 bit */
19483           INTC_PSR_8B_tag PSR127;        /* offset: 0x00BF size: 8 bit */
19484           INTC_PSR_8B_tag PSR128;        /* offset: 0x00C0 size: 8 bit */
19485           INTC_PSR_8B_tag PSR129;        /* offset: 0x00C1 size: 8 bit */
19486           INTC_PSR_8B_tag PSR130;        /* offset: 0x00C2 size: 8 bit */
19487           INTC_PSR_8B_tag PSR131;        /* offset: 0x00C3 size: 8 bit */
19488           INTC_PSR_8B_tag PSR132;        /* offset: 0x00C4 size: 8 bit */
19489           INTC_PSR_8B_tag PSR133;        /* offset: 0x00C5 size: 8 bit */
19490           INTC_PSR_8B_tag PSR134;        /* offset: 0x00C6 size: 8 bit */
19491           INTC_PSR_8B_tag PSR135;        /* offset: 0x00C7 size: 8 bit */
19492           INTC_PSR_8B_tag PSR136;        /* offset: 0x00C8 size: 8 bit */
19493           INTC_PSR_8B_tag PSR137;        /* offset: 0x00C9 size: 8 bit */
19494           INTC_PSR_8B_tag PSR138;        /* offset: 0x00CA size: 8 bit */
19495           INTC_PSR_8B_tag PSR139;        /* offset: 0x00CB size: 8 bit */
19496           INTC_PSR_8B_tag PSR140;        /* offset: 0x00CC size: 8 bit */
19497           INTC_PSR_8B_tag PSR141;        /* offset: 0x00CD size: 8 bit */
19498           INTC_PSR_8B_tag PSR142;        /* offset: 0x00CE size: 8 bit */
19499           INTC_PSR_8B_tag PSR143;        /* offset: 0x00CF size: 8 bit */
19500           INTC_PSR_8B_tag PSR144;        /* offset: 0x00D0 size: 8 bit */
19501           INTC_PSR_8B_tag PSR145;        /* offset: 0x00D1 size: 8 bit */
19502           INTC_PSR_8B_tag PSR146;        /* offset: 0x00D2 size: 8 bit */
19503           INTC_PSR_8B_tag PSR147;        /* offset: 0x00D3 size: 8 bit */
19504           INTC_PSR_8B_tag PSR148;        /* offset: 0x00D4 size: 8 bit */
19505           INTC_PSR_8B_tag PSR149;        /* offset: 0x00D5 size: 8 bit */
19506           INTC_PSR_8B_tag PSR150;        /* offset: 0x00D6 size: 8 bit */
19507           INTC_PSR_8B_tag PSR151;        /* offset: 0x00D7 size: 8 bit */
19508           INTC_PSR_8B_tag PSR152;        /* offset: 0x00D8 size: 8 bit */
19509           INTC_PSR_8B_tag PSR153;        /* offset: 0x00D9 size: 8 bit */
19510           INTC_PSR_8B_tag PSR154;        /* offset: 0x00DA size: 8 bit */
19511           INTC_PSR_8B_tag PSR155;        /* offset: 0x00DB size: 8 bit */
19512           INTC_PSR_8B_tag PSR156;        /* offset: 0x00DC size: 8 bit */
19513           INTC_PSR_8B_tag PSR157;        /* offset: 0x00DD size: 8 bit */
19514           INTC_PSR_8B_tag PSR158;        /* offset: 0x00DE size: 8 bit */
19515           INTC_PSR_8B_tag PSR159;        /* offset: 0x00DF size: 8 bit */
19516           INTC_PSR_8B_tag PSR160;        /* offset: 0x00E0 size: 8 bit */
19517           INTC_PSR_8B_tag PSR161;        /* offset: 0x00E1 size: 8 bit */
19518           INTC_PSR_8B_tag PSR162;        /* offset: 0x00E2 size: 8 bit */
19519           INTC_PSR_8B_tag PSR163;        /* offset: 0x00E3 size: 8 bit */
19520           INTC_PSR_8B_tag PSR164;        /* offset: 0x00E4 size: 8 bit */
19521           INTC_PSR_8B_tag PSR165;        /* offset: 0x00E5 size: 8 bit */
19522           INTC_PSR_8B_tag PSR166;        /* offset: 0x00E6 size: 8 bit */
19523           INTC_PSR_8B_tag PSR167;        /* offset: 0x00E7 size: 8 bit */
19524           INTC_PSR_8B_tag PSR168;        /* offset: 0x00E8 size: 8 bit */
19525           INTC_PSR_8B_tag PSR169;        /* offset: 0x00E9 size: 8 bit */
19526           INTC_PSR_8B_tag PSR170;        /* offset: 0x00EA size: 8 bit */
19527           INTC_PSR_8B_tag PSR171;        /* offset: 0x00EB size: 8 bit */
19528           INTC_PSR_8B_tag PSR172;        /* offset: 0x00EC size: 8 bit */
19529           INTC_PSR_8B_tag PSR173;        /* offset: 0x00ED size: 8 bit */
19530           INTC_PSR_8B_tag PSR174;        /* offset: 0x00EE size: 8 bit */
19531           INTC_PSR_8B_tag PSR175;        /* offset: 0x00EF size: 8 bit */
19532           INTC_PSR_8B_tag PSR176;        /* offset: 0x00F0 size: 8 bit */
19533           INTC_PSR_8B_tag PSR177;        /* offset: 0x00F1 size: 8 bit */
19534           INTC_PSR_8B_tag PSR178;        /* offset: 0x00F2 size: 8 bit */
19535           INTC_PSR_8B_tag PSR179;        /* offset: 0x00F3 size: 8 bit */
19536           INTC_PSR_8B_tag PSR180;        /* offset: 0x00F4 size: 8 bit */
19537           INTC_PSR_8B_tag PSR181;        /* offset: 0x00F5 size: 8 bit */
19538           INTC_PSR_8B_tag PSR182;        /* offset: 0x00F6 size: 8 bit */
19539           INTC_PSR_8B_tag PSR183;        /* offset: 0x00F7 size: 8 bit */
19540           INTC_PSR_8B_tag PSR184;        /* offset: 0x00F8 size: 8 bit */
19541           INTC_PSR_8B_tag PSR185;        /* offset: 0x00F9 size: 8 bit */
19542           INTC_PSR_8B_tag PSR186;        /* offset: 0x00FA size: 8 bit */
19543           INTC_PSR_8B_tag PSR187;        /* offset: 0x00FB size: 8 bit */
19544           INTC_PSR_8B_tag PSR188;        /* offset: 0x00FC size: 8 bit */
19545           INTC_PSR_8B_tag PSR189;        /* offset: 0x00FD size: 8 bit */
19546           INTC_PSR_8B_tag PSR190;        /* offset: 0x00FE size: 8 bit */
19547           INTC_PSR_8B_tag PSR191;        /* offset: 0x00FF size: 8 bit */
19548           INTC_PSR_8B_tag PSR192;        /* offset: 0x0100 size: 8 bit */
19549           INTC_PSR_8B_tag PSR193;        /* offset: 0x0101 size: 8 bit */
19550           INTC_PSR_8B_tag PSR194;        /* offset: 0x0102 size: 8 bit */
19551           INTC_PSR_8B_tag PSR195;        /* offset: 0x0103 size: 8 bit */
19552           INTC_PSR_8B_tag PSR196;        /* offset: 0x0104 size: 8 bit */
19553           INTC_PSR_8B_tag PSR197;        /* offset: 0x0105 size: 8 bit */
19554           INTC_PSR_8B_tag PSR198;        /* offset: 0x0106 size: 8 bit */
19555           INTC_PSR_8B_tag PSR199;        /* offset: 0x0107 size: 8 bit */
19556           INTC_PSR_8B_tag PSR200;        /* offset: 0x0108 size: 8 bit */
19557           INTC_PSR_8B_tag PSR201;        /* offset: 0x0109 size: 8 bit */
19558           INTC_PSR_8B_tag PSR202;        /* offset: 0x010A size: 8 bit */
19559           INTC_PSR_8B_tag PSR203;        /* offset: 0x010B size: 8 bit */
19560           INTC_PSR_8B_tag PSR204;        /* offset: 0x010C size: 8 bit */
19561           INTC_PSR_8B_tag PSR205;        /* offset: 0x010D size: 8 bit */
19562           INTC_PSR_8B_tag PSR206;        /* offset: 0x010E size: 8 bit */
19563           INTC_PSR_8B_tag PSR207;        /* offset: 0x010F size: 8 bit */
19564           INTC_PSR_8B_tag PSR208;        /* offset: 0x0110 size: 8 bit */
19565           INTC_PSR_8B_tag PSR209;        /* offset: 0x0111 size: 8 bit */
19566           INTC_PSR_8B_tag PSR210;        /* offset: 0x0112 size: 8 bit */
19567           INTC_PSR_8B_tag PSR211;        /* offset: 0x0113 size: 8 bit */
19568           INTC_PSR_8B_tag PSR212;        /* offset: 0x0114 size: 8 bit */
19569           INTC_PSR_8B_tag PSR213;        /* offset: 0x0115 size: 8 bit */
19570           INTC_PSR_8B_tag PSR214;        /* offset: 0x0116 size: 8 bit */
19571           INTC_PSR_8B_tag PSR215;        /* offset: 0x0117 size: 8 bit */
19572           INTC_PSR_8B_tag PSR216;        /* offset: 0x0118 size: 8 bit */
19573           INTC_PSR_8B_tag PSR217;        /* offset: 0x0119 size: 8 bit */
19574           INTC_PSR_8B_tag PSR218;        /* offset: 0x011A size: 8 bit */
19575           INTC_PSR_8B_tag PSR219;        /* offset: 0x011B size: 8 bit */
19576           INTC_PSR_8B_tag PSR220;        /* offset: 0x011C size: 8 bit */
19577           INTC_PSR_8B_tag PSR221;        /* offset: 0x011D size: 8 bit */
19578           INTC_PSR_8B_tag PSR222;        /* offset: 0x011E size: 8 bit */
19579           INTC_PSR_8B_tag PSR223;        /* offset: 0x011F size: 8 bit */
19580           INTC_PSR_8B_tag PSR224;        /* offset: 0x0120 size: 8 bit */
19581           INTC_PSR_8B_tag PSR225;        /* offset: 0x0121 size: 8 bit */
19582           INTC_PSR_8B_tag PSR226;        /* offset: 0x0122 size: 8 bit */
19583           INTC_PSR_8B_tag PSR227;        /* offset: 0x0123 size: 8 bit */
19584           INTC_PSR_8B_tag PSR228;        /* offset: 0x0124 size: 8 bit */
19585           INTC_PSR_8B_tag PSR229;        /* offset: 0x0125 size: 8 bit */
19586           INTC_PSR_8B_tag PSR230;        /* offset: 0x0126 size: 8 bit */
19587           INTC_PSR_8B_tag PSR231;        /* offset: 0x0127 size: 8 bit */
19588           INTC_PSR_8B_tag PSR232;        /* offset: 0x0128 size: 8 bit */
19589           INTC_PSR_8B_tag PSR233;        /* offset: 0x0129 size: 8 bit */
19590           INTC_PSR_8B_tag PSR234;        /* offset: 0x012A size: 8 bit */
19591           INTC_PSR_8B_tag PSR235;        /* offset: 0x012B size: 8 bit */
19592           INTC_PSR_8B_tag PSR236;        /* offset: 0x012C size: 8 bit */
19593           INTC_PSR_8B_tag PSR237;        /* offset: 0x012D size: 8 bit */
19594           INTC_PSR_8B_tag PSR238;        /* offset: 0x012E size: 8 bit */
19595           INTC_PSR_8B_tag PSR239;        /* offset: 0x012F size: 8 bit */
19596           INTC_PSR_8B_tag PSR240;        /* offset: 0x0130 size: 8 bit */
19597           INTC_PSR_8B_tag PSR241;        /* offset: 0x0131 size: 8 bit */
19598           INTC_PSR_8B_tag PSR242;        /* offset: 0x0132 size: 8 bit */
19599           INTC_PSR_8B_tag PSR243;        /* offset: 0x0133 size: 8 bit */
19600           INTC_PSR_8B_tag PSR244;        /* offset: 0x0134 size: 8 bit */
19601           INTC_PSR_8B_tag PSR245;        /* offset: 0x0135 size: 8 bit */
19602           INTC_PSR_8B_tag PSR246;        /* offset: 0x0136 size: 8 bit */
19603           INTC_PSR_8B_tag PSR247;        /* offset: 0x0137 size: 8 bit */
19604           INTC_PSR_8B_tag PSR248;        /* offset: 0x0138 size: 8 bit */
19605           INTC_PSR_8B_tag PSR249;        /* offset: 0x0139 size: 8 bit */
19606           INTC_PSR_8B_tag PSR250;        /* offset: 0x013A size: 8 bit */
19607           INTC_PSR_8B_tag PSR251;        /* offset: 0x013B size: 8 bit */
19608           INTC_PSR_8B_tag PSR252;        /* offset: 0x013C size: 8 bit */
19609           INTC_PSR_8B_tag PSR253;        /* offset: 0x013D size: 8 bit */
19610           INTC_PSR_8B_tag PSR254;        /* offset: 0x013E size: 8 bit */
19611           INTC_PSR_8B_tag PSR255;        /* offset: 0x013F size: 8 bit */
19612           INTC_PSR_8B_tag PSR256;        /* offset: 0x0140 size: 8 bit */
19613           INTC_PSR_8B_tag PSR257;        /* offset: 0x0141 size: 8 bit */
19614           INTC_PSR_8B_tag PSR258;        /* offset: 0x0142 size: 8 bit */
19615           INTC_PSR_8B_tag PSR259;        /* offset: 0x0143 size: 8 bit */
19616           INTC_PSR_8B_tag PSR260;        /* offset: 0x0144 size: 8 bit */
19617           INTC_PSR_8B_tag PSR261;        /* offset: 0x0145 size: 8 bit */
19618           INTC_PSR_8B_tag PSR262;        /* offset: 0x0146 size: 8 bit */
19619           INTC_PSR_8B_tag PSR263;        /* offset: 0x0147 size: 8 bit */
19620           INTC_PSR_8B_tag PSR264;        /* offset: 0x0148 size: 8 bit */
19621           INTC_PSR_8B_tag PSR265;        /* offset: 0x0149 size: 8 bit */
19622           INTC_PSR_8B_tag PSR266;        /* offset: 0x014A size: 8 bit */
19623           INTC_PSR_8B_tag PSR267;        /* offset: 0x014B size: 8 bit */
19624           INTC_PSR_8B_tag PSR268;        /* offset: 0x014C size: 8 bit */
19625           INTC_PSR_8B_tag PSR269;        /* offset: 0x014D size: 8 bit */
19626           INTC_PSR_8B_tag PSR270;        /* offset: 0x014E size: 8 bit */
19627           INTC_PSR_8B_tag PSR271;        /* offset: 0x014F size: 8 bit */
19628           INTC_PSR_8B_tag PSR272;        /* offset: 0x0150 size: 8 bit */
19629           INTC_PSR_8B_tag PSR273;        /* offset: 0x0151 size: 8 bit */
19630           INTC_PSR_8B_tag PSR274;        /* offset: 0x0152 size: 8 bit */
19631           INTC_PSR_8B_tag PSR275;        /* offset: 0x0153 size: 8 bit */
19632           INTC_PSR_8B_tag PSR276;        /* offset: 0x0154 size: 8 bit */
19633           INTC_PSR_8B_tag PSR277;        /* offset: 0x0155 size: 8 bit */
19634           INTC_PSR_8B_tag PSR278;        /* offset: 0x0156 size: 8 bit */
19635           INTC_PSR_8B_tag PSR279;        /* offset: 0x0157 size: 8 bit */
19636           INTC_PSR_8B_tag PSR280;        /* offset: 0x0158 size: 8 bit */
19637           INTC_PSR_8B_tag PSR281;        /* offset: 0x0159 size: 8 bit */
19638           INTC_PSR_8B_tag PSR282;        /* offset: 0x015A size: 8 bit */
19639           INTC_PSR_8B_tag PSR283;        /* offset: 0x015B size: 8 bit */
19640           INTC_PSR_8B_tag PSR284;        /* offset: 0x015C size: 8 bit */
19641           INTC_PSR_8B_tag PSR285;        /* offset: 0x015D size: 8 bit */
19642           INTC_PSR_8B_tag PSR286;        /* offset: 0x015E size: 8 bit */
19643           INTC_PSR_8B_tag PSR287;        /* offset: 0x015F size: 8 bit */
19644           INTC_PSR_8B_tag PSR288;        /* offset: 0x0160 size: 8 bit */
19645           INTC_PSR_8B_tag PSR289;        /* offset: 0x0161 size: 8 bit */
19646           INTC_PSR_8B_tag PSR290;        /* offset: 0x0162 size: 8 bit */
19647           INTC_PSR_8B_tag PSR291;        /* offset: 0x0163 size: 8 bit */
19648           INTC_PSR_8B_tag PSR292;        /* offset: 0x0164 size: 8 bit */
19649           INTC_PSR_8B_tag PSR293;        /* offset: 0x0165 size: 8 bit */
19650           INTC_PSR_8B_tag PSR294;        /* offset: 0x0166 size: 8 bit */
19651           INTC_PSR_8B_tag PSR295;        /* offset: 0x0167 size: 8 bit */
19652           INTC_PSR_8B_tag PSR296;        /* offset: 0x0168 size: 8 bit */
19653           INTC_PSR_8B_tag PSR297;        /* offset: 0x0169 size: 8 bit */
19654           INTC_PSR_8B_tag PSR298;        /* offset: 0x016A size: 8 bit */
19655           INTC_PSR_8B_tag PSR299;        /* offset: 0x016B size: 8 bit */
19656           INTC_PSR_8B_tag PSR300;        /* offset: 0x016C size: 8 bit */
19657           INTC_PSR_8B_tag PSR301;        /* offset: 0x016D size: 8 bit */
19658           INTC_PSR_8B_tag PSR302;        /* offset: 0x016E size: 8 bit */
19659           INTC_PSR_8B_tag PSR303;        /* offset: 0x016F size: 8 bit */
19660           INTC_PSR_8B_tag PSR304;        /* offset: 0x0170 size: 8 bit */
19661           INTC_PSR_8B_tag PSR305;        /* offset: 0x0171 size: 8 bit */
19662           INTC_PSR_8B_tag PSR306;        /* offset: 0x0172 size: 8 bit */
19663           INTC_PSR_8B_tag PSR307;        /* offset: 0x0173 size: 8 bit */
19664           INTC_PSR_8B_tag PSR308;        /* offset: 0x0174 size: 8 bit */
19665           INTC_PSR_8B_tag PSR309;        /* offset: 0x0175 size: 8 bit */
19666           INTC_PSR_8B_tag PSR310;        /* offset: 0x0176 size: 8 bit */
19667           INTC_PSR_8B_tag PSR311;        /* offset: 0x0177 size: 8 bit */
19668           INTC_PSR_8B_tag PSR312;        /* offset: 0x0178 size: 8 bit */
19669           INTC_PSR_8B_tag PSR313;        /* offset: 0x0179 size: 8 bit */
19670           INTC_PSR_8B_tag PSR314;        /* offset: 0x017A size: 8 bit */
19671           INTC_PSR_8B_tag PSR315;        /* offset: 0x017B size: 8 bit */
19672           INTC_PSR_8B_tag PSR316;        /* offset: 0x017C size: 8 bit */
19673           INTC_PSR_8B_tag PSR317;        /* offset: 0x017D size: 8 bit */
19674           INTC_PSR_8B_tag PSR318;        /* offset: 0x017E size: 8 bit */
19675           INTC_PSR_8B_tag PSR319;        /* offset: 0x017F size: 8 bit */
19676           INTC_PSR_8B_tag PSR320;        /* offset: 0x0180 size: 8 bit */
19677           INTC_PSR_8B_tag PSR321;        /* offset: 0x0181 size: 8 bit */
19678           INTC_PSR_8B_tag PSR322;        /* offset: 0x0182 size: 8 bit */
19679           INTC_PSR_8B_tag PSR323;        /* offset: 0x0183 size: 8 bit */
19680           INTC_PSR_8B_tag PSR324;        /* offset: 0x0184 size: 8 bit */
19681           INTC_PSR_8B_tag PSR325;        /* offset: 0x0185 size: 8 bit */
19682           INTC_PSR_8B_tag PSR326;        /* offset: 0x0186 size: 8 bit */
19683           INTC_PSR_8B_tag PSR327;        /* offset: 0x0187 size: 8 bit */
19684           INTC_PSR_8B_tag PSR328;        /* offset: 0x0188 size: 8 bit */
19685           INTC_PSR_8B_tag PSR329;        /* offset: 0x0189 size: 8 bit */
19686           INTC_PSR_8B_tag PSR330;        /* offset: 0x018A size: 8 bit */
19687           INTC_PSR_8B_tag PSR331;        /* offset: 0x018B size: 8 bit */
19688           INTC_PSR_8B_tag PSR332;        /* offset: 0x018C size: 8 bit */
19689           INTC_PSR_8B_tag PSR333;        /* offset: 0x018D size: 8 bit */
19690           INTC_PSR_8B_tag PSR334;        /* offset: 0x018E size: 8 bit */
19691           INTC_PSR_8B_tag PSR335;        /* offset: 0x018F size: 8 bit */
19692           INTC_PSR_8B_tag PSR336;        /* offset: 0x0190 size: 8 bit */
19693           INTC_PSR_8B_tag PSR337;        /* offset: 0x0191 size: 8 bit */
19694           INTC_PSR_8B_tag PSR338;        /* offset: 0x0192 size: 8 bit */
19695           INTC_PSR_8B_tag PSR339;        /* offset: 0x0193 size: 8 bit */
19696           INTC_PSR_8B_tag PSR340;        /* offset: 0x0194 size: 8 bit */
19697           INTC_PSR_8B_tag PSR341;        /* offset: 0x0195 size: 8 bit */
19698           INTC_PSR_8B_tag PSR342;        /* offset: 0x0196 size: 8 bit */
19699           INTC_PSR_8B_tag PSR343;        /* offset: 0x0197 size: 8 bit */
19700           INTC_PSR_8B_tag PSR344;        /* offset: 0x0198 size: 8 bit */
19701           INTC_PSR_8B_tag PSR345;        /* offset: 0x0199 size: 8 bit */
19702           INTC_PSR_8B_tag PSR346;        /* offset: 0x019A size: 8 bit */
19703           INTC_PSR_8B_tag PSR347;        /* offset: 0x019B size: 8 bit */
19704           INTC_PSR_8B_tag PSR348;        /* offset: 0x019C size: 8 bit */
19705           INTC_PSR_8B_tag PSR349;        /* offset: 0x019D size: 8 bit */
19706           INTC_PSR_8B_tag PSR350;        /* offset: 0x019E size: 8 bit */
19707           INTC_PSR_8B_tag PSR351;        /* offset: 0x019F size: 8 bit */
19708           INTC_PSR_8B_tag PSR352;        /* offset: 0x01A0 size: 8 bit */
19709           INTC_PSR_8B_tag PSR353;        /* offset: 0x01A1 size: 8 bit */
19710           INTC_PSR_8B_tag PSR354;        /* offset: 0x01A2 size: 8 bit */
19711           INTC_PSR_8B_tag PSR355;        /* offset: 0x01A3 size: 8 bit */
19712           INTC_PSR_8B_tag PSR356;        /* offset: 0x01A4 size: 8 bit */
19713           INTC_PSR_8B_tag PSR357;        /* offset: 0x01A5 size: 8 bit */
19714           INTC_PSR_8B_tag PSR358;        /* offset: 0x01A6 size: 8 bit */
19715           INTC_PSR_8B_tag PSR359;        /* offset: 0x01A7 size: 8 bit */
19716           INTC_PSR_8B_tag PSR360;        /* offset: 0x01A8 size: 8 bit */
19717           INTC_PSR_8B_tag PSR361;        /* offset: 0x01A9 size: 8 bit */
19718           INTC_PSR_8B_tag PSR362;        /* offset: 0x01AA size: 8 bit */
19719           INTC_PSR_8B_tag PSR363;        /* offset: 0x01AB size: 8 bit */
19720           INTC_PSR_8B_tag PSR364;        /* offset: 0x01AC size: 8 bit */
19721           INTC_PSR_8B_tag PSR365;        /* offset: 0x01AD size: 8 bit */
19722           INTC_PSR_8B_tag PSR366;        /* offset: 0x01AE size: 8 bit */
19723           INTC_PSR_8B_tag PSR367;        /* offset: 0x01AF size: 8 bit */
19724           INTC_PSR_8B_tag PSR368;        /* offset: 0x01B0 size: 8 bit */
19725           INTC_PSR_8B_tag PSR369;        /* offset: 0x01B1 size: 8 bit */
19726           INTC_PSR_8B_tag PSR370;        /* offset: 0x01B2 size: 8 bit */
19727           INTC_PSR_8B_tag PSR371;        /* offset: 0x01B3 size: 8 bit */
19728           INTC_PSR_8B_tag PSR372;        /* offset: 0x01B4 size: 8 bit */
19729           INTC_PSR_8B_tag PSR373;        /* offset: 0x01B5 size: 8 bit */
19730           INTC_PSR_8B_tag PSR374;        /* offset: 0x01B6 size: 8 bit */
19731           INTC_PSR_8B_tag PSR375;        /* offset: 0x01B7 size: 8 bit */
19732           INTC_PSR_8B_tag PSR376;        /* offset: 0x01B8 size: 8 bit */
19733           INTC_PSR_8B_tag PSR377;        /* offset: 0x01B9 size: 8 bit */
19734           INTC_PSR_8B_tag PSR378;        /* offset: 0x01BA size: 8 bit */
19735           INTC_PSR_8B_tag PSR379;        /* offset: 0x01BB size: 8 bit */
19736           INTC_PSR_8B_tag PSR380;        /* offset: 0x01BC size: 8 bit */
19737           INTC_PSR_8B_tag PSR381;        /* offset: 0x01BD size: 8 bit */
19738           INTC_PSR_8B_tag PSR382;        /* offset: 0x01BE size: 8 bit */
19739           INTC_PSR_8B_tag PSR383;        /* offset: 0x01BF size: 8 bit */
19740           INTC_PSR_8B_tag PSR384;        /* offset: 0x01C0 size: 8 bit */
19741           INTC_PSR_8B_tag PSR385;        /* offset: 0x01C1 size: 8 bit */
19742           INTC_PSR_8B_tag PSR386;        /* offset: 0x01C2 size: 8 bit */
19743           INTC_PSR_8B_tag PSR387;        /* offset: 0x01C3 size: 8 bit */
19744           INTC_PSR_8B_tag PSR388;        /* offset: 0x01C4 size: 8 bit */
19745           INTC_PSR_8B_tag PSR389;        /* offset: 0x01C5 size: 8 bit */
19746           INTC_PSR_8B_tag PSR390;        /* offset: 0x01C6 size: 8 bit */
19747           INTC_PSR_8B_tag PSR391;        /* offset: 0x01C7 size: 8 bit */
19748           INTC_PSR_8B_tag PSR392;        /* offset: 0x01C8 size: 8 bit */
19749           INTC_PSR_8B_tag PSR393;        /* offset: 0x01C9 size: 8 bit */
19750           INTC_PSR_8B_tag PSR394;        /* offset: 0x01CA size: 8 bit */
19751           INTC_PSR_8B_tag PSR395;        /* offset: 0x01CB size: 8 bit */
19752           INTC_PSR_8B_tag PSR396;        /* offset: 0x01CC size: 8 bit */
19753           INTC_PSR_8B_tag PSR397;        /* offset: 0x01CD size: 8 bit */
19754           INTC_PSR_8B_tag PSR398;        /* offset: 0x01CE size: 8 bit */
19755           INTC_PSR_8B_tag PSR399;        /* offset: 0x01CF size: 8 bit */
19756           INTC_PSR_8B_tag PSR400;        /* offset: 0x01D0 size: 8 bit */
19757           INTC_PSR_8B_tag PSR401;        /* offset: 0x01D1 size: 8 bit */
19758           INTC_PSR_8B_tag PSR402;        /* offset: 0x01D2 size: 8 bit */
19759           INTC_PSR_8B_tag PSR403;        /* offset: 0x01D3 size: 8 bit */
19760           INTC_PSR_8B_tag PSR404;        /* offset: 0x01D4 size: 8 bit */
19761           INTC_PSR_8B_tag PSR405;        /* offset: 0x01D5 size: 8 bit */
19762           INTC_PSR_8B_tag PSR406;        /* offset: 0x01D6 size: 8 bit */
19763           INTC_PSR_8B_tag PSR407;        /* offset: 0x01D7 size: 8 bit */
19764           INTC_PSR_8B_tag PSR408;        /* offset: 0x01D8 size: 8 bit */
19765           INTC_PSR_8B_tag PSR409;        /* offset: 0x01D9 size: 8 bit */
19766           INTC_PSR_8B_tag PSR410;        /* offset: 0x01DA size: 8 bit */
19767           INTC_PSR_8B_tag PSR411;        /* offset: 0x01DB size: 8 bit */
19768           INTC_PSR_8B_tag PSR412;        /* offset: 0x01DC size: 8 bit */
19769           INTC_PSR_8B_tag PSR413;        /* offset: 0x01DD size: 8 bit */
19770           INTC_PSR_8B_tag PSR414;        /* offset: 0x01DE size: 8 bit */
19771           INTC_PSR_8B_tag PSR415;        /* offset: 0x01DF size: 8 bit */
19772           INTC_PSR_8B_tag PSR416;        /* offset: 0x01E0 size: 8 bit */
19773           INTC_PSR_8B_tag PSR417;        /* offset: 0x01E1 size: 8 bit */
19774           INTC_PSR_8B_tag PSR418;        /* offset: 0x01E2 size: 8 bit */
19775           INTC_PSR_8B_tag PSR419;        /* offset: 0x01E3 size: 8 bit */
19776           INTC_PSR_8B_tag PSR420;        /* offset: 0x01E4 size: 8 bit */
19777           INTC_PSR_8B_tag PSR421;        /* offset: 0x01E5 size: 8 bit */
19778           INTC_PSR_8B_tag PSR422;        /* offset: 0x01E6 size: 8 bit */
19779           INTC_PSR_8B_tag PSR423;        /* offset: 0x01E7 size: 8 bit */
19780           INTC_PSR_8B_tag PSR424;        /* offset: 0x01E8 size: 8 bit */
19781           INTC_PSR_8B_tag PSR425;        /* offset: 0x01E9 size: 8 bit */
19782           INTC_PSR_8B_tag PSR426;        /* offset: 0x01EA size: 8 bit */
19783           INTC_PSR_8B_tag PSR427;        /* offset: 0x01EB size: 8 bit */
19784           INTC_PSR_8B_tag PSR428;        /* offset: 0x01EC size: 8 bit */
19785           INTC_PSR_8B_tag PSR429;        /* offset: 0x01ED size: 8 bit */
19786           INTC_PSR_8B_tag PSR430;        /* offset: 0x01EE size: 8 bit */
19787           INTC_PSR_8B_tag PSR431;        /* offset: 0x01EF size: 8 bit */
19788           INTC_PSR_8B_tag PSR432;        /* offset: 0x01F0 size: 8 bit */
19789           INTC_PSR_8B_tag PSR433;        /* offset: 0x01F1 size: 8 bit */
19790           INTC_PSR_8B_tag PSR434;        /* offset: 0x01F2 size: 8 bit */
19791           INTC_PSR_8B_tag PSR435;        /* offset: 0x01F3 size: 8 bit */
19792           INTC_PSR_8B_tag PSR436;        /* offset: 0x01F4 size: 8 bit */
19793           INTC_PSR_8B_tag PSR437;        /* offset: 0x01F5 size: 8 bit */
19794           INTC_PSR_8B_tag PSR438;        /* offset: 0x01F6 size: 8 bit */
19795           INTC_PSR_8B_tag PSR439;        /* offset: 0x01F7 size: 8 bit */
19796           INTC_PSR_8B_tag PSR440;        /* offset: 0x01F8 size: 8 bit */
19797           INTC_PSR_8B_tag PSR441;        /* offset: 0x01F9 size: 8 bit */
19798           INTC_PSR_8B_tag PSR442;        /* offset: 0x01FA size: 8 bit */
19799           INTC_PSR_8B_tag PSR443;        /* offset: 0x01FB size: 8 bit */
19800           INTC_PSR_8B_tag PSR444;        /* offset: 0x01FC size: 8 bit */
19801           INTC_PSR_8B_tag PSR445;        /* offset: 0x01FD size: 8 bit */
19802           INTC_PSR_8B_tag PSR446;        /* offset: 0x01FE size: 8 bit */
19803           INTC_PSR_8B_tag PSR447;        /* offset: 0x01FF size: 8 bit */
19804           INTC_PSR_8B_tag PSR448;        /* offset: 0x0200 size: 8 bit */
19805           INTC_PSR_8B_tag PSR449;        /* offset: 0x0201 size: 8 bit */
19806           INTC_PSR_8B_tag PSR450;        /* offset: 0x0202 size: 8 bit */
19807           INTC_PSR_8B_tag PSR451;        /* offset: 0x0203 size: 8 bit */
19808           INTC_PSR_8B_tag PSR452;        /* offset: 0x0204 size: 8 bit */
19809           INTC_PSR_8B_tag PSR453;        /* offset: 0x0205 size: 8 bit */
19810           INTC_PSR_8B_tag PSR454;        /* offset: 0x0206 size: 8 bit */
19811           INTC_PSR_8B_tag PSR455;        /* offset: 0x0207 size: 8 bit */
19812           INTC_PSR_8B_tag PSR456;        /* offset: 0x0208 size: 8 bit */
19813           INTC_PSR_8B_tag PSR457;        /* offset: 0x0209 size: 8 bit */
19814           INTC_PSR_8B_tag PSR458;        /* offset: 0x020A size: 8 bit */
19815           INTC_PSR_8B_tag PSR459;        /* offset: 0x020B size: 8 bit */
19816           INTC_PSR_8B_tag PSR460;        /* offset: 0x020C size: 8 bit */
19817           INTC_PSR_8B_tag PSR461;        /* offset: 0x020D size: 8 bit */
19818           INTC_PSR_8B_tag PSR462;        /* offset: 0x020E size: 8 bit */
19819           INTC_PSR_8B_tag PSR463;        /* offset: 0x020F size: 8 bit */
19820           INTC_PSR_8B_tag PSR464;        /* offset: 0x0210 size: 8 bit */
19821           INTC_PSR_8B_tag PSR465;        /* offset: 0x0211 size: 8 bit */
19822           INTC_PSR_8B_tag PSR466;        /* offset: 0x0212 size: 8 bit */
19823           INTC_PSR_8B_tag PSR467;        /* offset: 0x0213 size: 8 bit */
19824           INTC_PSR_8B_tag PSR468;        /* offset: 0x0214 size: 8 bit */
19825           INTC_PSR_8B_tag PSR469;        /* offset: 0x0215 size: 8 bit */
19826           INTC_PSR_8B_tag PSR470;        /* offset: 0x0216 size: 8 bit */
19827           INTC_PSR_8B_tag PSR471;        /* offset: 0x0217 size: 8 bit */
19828           INTC_PSR_8B_tag PSR472;        /* offset: 0x0218 size: 8 bit */
19829           INTC_PSR_8B_tag PSR473;        /* offset: 0x0219 size: 8 bit */
19830           INTC_PSR_8B_tag PSR474;        /* offset: 0x021A size: 8 bit */
19831           INTC_PSR_8B_tag PSR475;        /* offset: 0x021B size: 8 bit */
19832           INTC_PSR_8B_tag PSR476;        /* offset: 0x021C size: 8 bit */
19833           INTC_PSR_8B_tag PSR477;        /* offset: 0x021D size: 8 bit */
19834           INTC_PSR_8B_tag PSR478;        /* offset: 0x021E size: 8 bit */
19835           INTC_PSR_8B_tag PSR479;        /* offset: 0x021F size: 8 bit */
19836           INTC_PSR_8B_tag PSR480;        /* offset: 0x0220 size: 8 bit */
19837           INTC_PSR_8B_tag PSR481;        /* offset: 0x0221 size: 8 bit */
19838           INTC_PSR_8B_tag PSR482;        /* offset: 0x0222 size: 8 bit */
19839           INTC_PSR_8B_tag PSR483;        /* offset: 0x0223 size: 8 bit */
19840           INTC_PSR_8B_tag PSR484;        /* offset: 0x0224 size: 8 bit */
19841           INTC_PSR_8B_tag PSR485;        /* offset: 0x0225 size: 8 bit */
19842           INTC_PSR_8B_tag PSR486;        /* offset: 0x0226 size: 8 bit */
19843           INTC_PSR_8B_tag PSR487;        /* offset: 0x0227 size: 8 bit */
19844           INTC_PSR_8B_tag PSR488;        /* offset: 0x0228 size: 8 bit */
19845           INTC_PSR_8B_tag PSR489;        /* offset: 0x0229 size: 8 bit */
19846           INTC_PSR_8B_tag PSR490;        /* offset: 0x022A size: 8 bit */
19847           INTC_PSR_8B_tag PSR491;        /* offset: 0x022B size: 8 bit */
19848           INTC_PSR_8B_tag PSR492;        /* offset: 0x022C size: 8 bit */
19849           INTC_PSR_8B_tag PSR493;        /* offset: 0x022D size: 8 bit */
19850           INTC_PSR_8B_tag PSR494;        /* offset: 0x022E size: 8 bit */
19851           INTC_PSR_8B_tag PSR495;        /* offset: 0x022F size: 8 bit */
19852           INTC_PSR_8B_tag PSR496;        /* offset: 0x0230 size: 8 bit */
19853           INTC_PSR_8B_tag PSR497;        /* offset: 0x0231 size: 8 bit */
19854           INTC_PSR_8B_tag PSR498;        /* offset: 0x0232 size: 8 bit */
19855           INTC_PSR_8B_tag PSR499;        /* offset: 0x0233 size: 8 bit */
19856           INTC_PSR_8B_tag PSR500;        /* offset: 0x0234 size: 8 bit */
19857           INTC_PSR_8B_tag PSR501;        /* offset: 0x0235 size: 8 bit */
19858           INTC_PSR_8B_tag PSR502;        /* offset: 0x0236 size: 8 bit */
19859           INTC_PSR_8B_tag PSR503;        /* offset: 0x0237 size: 8 bit */
19860           INTC_PSR_8B_tag PSR504;        /* offset: 0x0238 size: 8 bit */
19861           INTC_PSR_8B_tag PSR505;        /* offset: 0x0239 size: 8 bit */
19862           INTC_PSR_8B_tag PSR506;        /* offset: 0x023A size: 8 bit */
19863           INTC_PSR_8B_tag PSR507;        /* offset: 0x023B size: 8 bit */
19864           INTC_PSR_8B_tag PSR508;        /* offset: 0x023C size: 8 bit */
19865           INTC_PSR_8B_tag PSR509;        /* offset: 0x023D size: 8 bit */
19866           INTC_PSR_8B_tag PSR510;        /* offset: 0x023E size: 8 bit */
19867           INTC_PSR_8B_tag PSR511;        /* offset: 0x023F size: 8 bit */
19868         };
19869       };
19870   
19871       int8_t INTC_reserved_0240[15808];
19872     } INTC_tag;
19873   
19874   #define INTC                           (*(volatile INTC_tag *) 0xFFF48000UL)
19875   
19876     /****************************************************************/
19877     /*                                                              */
19878     /* Module: DSPI  */
19879     /*                                                              */
19880     /****************************************************************/
19881     typedef union {                      /* MCR - Module Configuration Register */
19882       vuint32_t R;
19883       struct {
19884         vuint32_t MSTR:1;                /* Master/Slave mode select */
19885         vuint32_t CONT_SCKE:1;           /* Continuous SCK Enable */
19886         vuint32_t DCONF:2;               /* DSPI Configuration */
19887         vuint32_t FRZ:1;                 /* Freeze */
19888         vuint32_t MTFE:1;                /* Modified Timing Format Enable */
19889         vuint32_t PCSSE:1;               /* Peripheral Chip Select Strobe Enable */
19890         vuint32_t ROOE:1;                /* Receive FIFO Overflow Overwrite Enable */
19891         vuint32_t PCSIS7:1;              /* Peripheral Chip Select 7 Inactive State */
19892         vuint32_t PCSIS6:1;              /* Peripheral Chip Select 6 Inactive State */
19893         vuint32_t PCSIS5:1;              /* Peripheral Chip Select 5 Inactive State */
19894         vuint32_t PCSIS4:1;              /* Peripheral Chip Select 4 Inactive State */
19895         vuint32_t PCSIS3:1;              /* Peripheral Chip Select 3 Inactive State */
19896         vuint32_t PCSIS2:1;              /* Peripheral Chip Select 2 Inactive State */
19897         vuint32_t PCSIS1:1;              /* Peripheral Chip Select 1 Inactive State */
19898         vuint32_t PCSIS0:1;              /* Peripheral Chip Select 0 Inactive State */
19899         vuint32_t DOZE:1;                /* Doze Enable */
19900         vuint32_t MDIS:1;                /* Module Disable */
19901         vuint32_t DIS_TXF:1;             /* Disable Transmit FIFO */
19902         vuint32_t DIS_RXF:1;             /* Disable Receive FIFO */
19903         vuint32_t CLR_TXF:1;             /* Clear TX FIFO */
19904         vuint32_t CLR_RXF:1;             /* Clear RX FIFO */
19905         vuint32_t SMPL_PT:2;             /* Sample Point */
19906        vuint32_t:
19907         6;
19908         vuint32_t PES:1;                 /* Parity Error Stop */
19909         vuint32_t HALT:1;                /* Halt */
19910       } B;
19911     } DSPI_MCR_32B_tag;
19912   
19913     typedef union {                      /* HCR - Hardware Configuration Register */
19914       vuint32_t R;
19915       struct {
19916         vuint32_t DSI:1;                 /* DSI feature implemented flag */
19917         vuint32_t PISR:1;                /* DSPI_PISR registers implemented flag */
19918        vuint32_t:
19919         3;
19920         vuint32_t CTAR:3;                /* Number of implemented DSPI_CTAR registers */
19921         vuint32_t TXFR:4;                /* Number of implemented DSPI_TXFR registers */
19922         vuint32_t RXFR:4;                /* Number of implemented DSPI_RXFR registers */
19923        vuint32_t:
19924         16;
19925       } B;
19926     } DSPI_HCR_32B_tag;
19927   
19928     typedef union {                      /* TCR - Transfer Count Register */
19929       vuint32_t R;
19930       struct {
19931   
19932   #ifndef USE_FIELD_ALIASES_DSPI
19933   
19934         vuint32_t SPI_TCNT:16;           /* SPI Transfer Counter */
19935   
19936   #else
19937   
19938         vuint32_t TCNT:16;               /* deprecated name - please avoid */
19939   
19940   #endif
19941   
19942        vuint32_t:
19943         16;
19944       } B;
19945     } DSPI_TCR_32B_tag;
19946   
19947     /* Register layout for all registers SLAVE_CTAR ... */
19948     typedef union {                      /* CTAR0-1 - Clock and Transfer Attribute Registers (in slave mode) */
19949       vuint32_t R;
19950       struct {
19951         vuint32_t SLAVE_FMSZ:5;          /* Frame Size (in slave mode) */
19952         vuint32_t SLAVE_CPOL:1;          /* Clock Polarity (in slave mode) */
19953         vuint32_t SLAVE_CPHA:1;          /* Clock Phase (in slave mode) */
19954         vuint32_t SLAVE_PE:1;            /* Parity Enable (in slave mode) */
19955         vuint32_t SLAVE_PP:1;            /* Parity Polarity (in slave mode) */
19956        vuint32_t:
19957         23;
19958       } B;
19959     } DSPI_SLAVE_CTAR_32B_tag;
19960   
19961     /* Register layout for all registers CTAR ... */
19962     typedef union {                      /* CTAR0-7 - Clock and Transfer Attribute Registers */
19963       vuint32_t R;
19964       struct {
19965         vuint32_t DBR:1;                 /* Double Baud Rate */
19966         vuint32_t FMSZ:4;                /* Frame Size */
19967         vuint32_t CPOL:1;                /* Clock Polarity */
19968         vuint32_t CPHA:1;                /* Clock Phase */
19969         vuint32_t LSBFE:1;               /* LSB First Enable */
19970         vuint32_t PCSSCK:2;              /* PCS to SCK Delay Prescaler */
19971         vuint32_t PASC:2;                /* After SCK Delay Prescaler */
19972         vuint32_t PDT:2;                 /* Delay after Transfer Prescaler */
19973         vuint32_t PBR:2;                 /* Baud Rate Prescaler */
19974         vuint32_t CSSCK:4;               /* PCS to SCK Delay Scaler */
19975         vuint32_t ASC:4;                 /* After SCK Delay Scaler */
19976         vuint32_t DT:4;                  /* Delay after Transfer Scaler */
19977         vuint32_t BR:4;                  /* Baud Rate Scaler */
19978       } B;
19979     } DSPI_CTAR_32B_tag;
19980   
19981     typedef union {                      /* SR - Status Register */
19982       vuint32_t R;
19983       struct {
19984         vuint32_t TCF:1;                 /* Transfer Complete Flag */
19985         vuint32_t TXRXS:1;               /* TX & RX Status */
19986        vuint32_t:
19987         1;
19988         vuint32_t EOQF:1;                /* End of queue Flag */
19989         vuint32_t TFUF:1;                /* Transmit FIFO Underflow Flag */
19990        vuint32_t:
19991         1;
19992         vuint32_t TFFF:1;                /* Transmit FIFO FIll Flag */
19993        vuint32_t:
19994         2;
19995         vuint32_t DPEF:1;                /* DSI Parity Error Flag */
19996         vuint32_t SPEF:1;                /* SPI Parity Error Flag */
19997         vuint32_t DDIF:1;                /* DSI data received with active bits */
19998         vuint32_t RFOF:1;                /* Receive FIFO Overflow Flag */
19999        vuint32_t:
20000         1;
20001         vuint32_t RFDF:1;                /* Receive FIFO Drain Flag */
20002        vuint32_t:
20003         1;
20004         vuint32_t TXCTR:4;               /* TX FIFO Counter */
20005         vuint32_t TXNXTPTR:4;            /* Transmit Next Pointer */
20006         vuint32_t RXCTR:4;               /* RX FIFO Counter */
20007         vuint32_t POPNXTPTR:4;           /* Pop Next Pointer */
20008       } B;
20009     } DSPI_SR_32B_tag;
20010   
20011     typedef union {                      /* RSER - DMA/Interrupt Request Register */
20012       vuint32_t R;
20013       struct {
20014   
20015   #ifndef USE_FIELD_ALIASES_DSPI
20016   
20017         vuint32_t TCF_RE:1;              /* Transmission Complete Request Enable */
20018   
20019   #else
20020   
20021         vuint32_t TCFRE:1;               /* deprecated name - please avoid */
20022   
20023   #endif
20024   
20025        vuint32_t:
20026         2;
20027   
20028   #ifndef USE_FIELD_ALIASES_DSPI
20029   
20030         vuint32_t EOQF_RE:1;             /* DSPI Finished Request Enable */
20031   
20032   #else
20033   
20034         vuint32_t EOQFRE:1;              /* deprecated name - please avoid */
20035   
20036   #endif
20037   
20038   #ifndef USE_FIELD_ALIASES_DSPI
20039   
20040         vuint32_t TFUF_RE:1;             /* Transmit FIFO Underflow Request Enable */
20041   
20042   #else
20043   
20044         vuint32_t TFUFRE:1;              /* deprecated name - please avoid */
20045   
20046   #endif
20047   
20048        vuint32_t:
20049         1;
20050   
20051   #ifndef USE_FIELD_ALIASES_DSPI
20052   
20053         vuint32_t TFFF_RE:1;             /* Transmit FIFO Fill Request Enable */
20054   
20055   #else
20056   
20057         vuint32_t TFFFRE:1;              /* deprecated name - please avoid */
20058   
20059   #endif
20060   
20061   #ifndef USE_FIELD_ALIASES_DSPI
20062   
20063         vuint32_t TFFF_DIRS:1;           /* Transmit FIFO Fill DMA or Interrupt Request Select */
20064   
20065   #else
20066   
20067         vuint32_t TFFFDIRS:1;            /* deprecated name - please avoid */
20068   
20069   #endif
20070   
20071        vuint32_t:
20072         1;
20073         vuint32_t DPEF_RE:1;             /* DSI Parity Error Request Enable */
20074         vuint32_t SPEF_RE:1;             /* SPI Parity Error Request Enable */
20075         vuint32_t DDIF_RE:1;             /* DSI data received with active bits Request Enable */
20076   
20077   #ifndef USE_FIELD_ALIASES_DSPI
20078   
20079         vuint32_t RFOF_RE:1;             /* Receive FIFO overflow Request Enable */
20080   
20081   #else
20082   
20083         vuint32_t RFOFRE:1;              /* deprecated name - please avoid */
20084   
20085   #endif
20086   
20087        vuint32_t:
20088         1;
20089   
20090   #ifndef USE_FIELD_ALIASES_DSPI
20091   
20092         vuint32_t RFDF_RE:1;             /* Receive FIFO Drain Request Enable */
20093   
20094   #else
20095   
20096         vuint32_t RFDFRE:1;              /* deprecated name - please avoid */
20097   
20098   #endif
20099   
20100   #ifndef USE_FIELD_ALIASES_DSPI
20101   
20102         vuint32_t RFDF_DIRS:1;           /* Receive FIFO Drain DMA or Interrupt Request Select */
20103   
20104   #else
20105   
20106         vuint32_t RFDFDIRS:1;            /* deprecated name - please avoid */
20107   
20108   #endif
20109   
20110        vuint32_t:
20111         16;
20112       } B;
20113     } DSPI_RSER_32B_tag;
20114   
20115     typedef union {                      /* PUSHR - PUSH TX FIFO Register */
20116       vuint32_t R;
20117       struct {
20118         vuint32_t CONT:1;                /* Continuous Peripheral Chip Select Enable */
20119         vuint32_t CTAS:3;                /* Clock and Transfer Attributes Select */
20120         vuint32_t EOQ:1;                 /* End of Queue */
20121         vuint32_t CTCNT:1;               /* Clear SPI_TCNT */
20122         vuint32_t PUSHR_PE:1;            /* Parity Enable */
20123         vuint32_t PUSHR_PP:1;            /* Parity Polarity */
20124         vuint32_t PCS7:1;                /* Peripheral Chip Select 7 */
20125         vuint32_t PCS6:1;                /* Peripheral Chip Select 6 */
20126         vuint32_t PCS5:1;                /* Peripheral Chip Select 5 */
20127         vuint32_t PCS4:1;                /* Peripheral Chip Select 4 */
20128         vuint32_t PCS3:1;                /* Peripheral Chip Select 3 */
20129         vuint32_t PCS2:1;                /* Peripheral Chip Select 2 */
20130         vuint32_t PCS1:1;                /* Peripheral Chip Select 1 */
20131         vuint32_t PCS0:1;                /* Peripheral Chip Select 0 */
20132         vuint32_t TXDATA:16;             /* Transmit Data */
20133       } B;
20134     } DSPI_PUSHR_32B_tag;
20135   
20136     typedef union {                      /* POPR - POP RX FIFO Register */
20137       vuint32_t R;
20138       struct {
20139        vuint32_t:
20140         16;
20141         vuint32_t RXDATA:16;             /* Receive Data */
20142       } B;
20143     } DSPI_POPR_32B_tag;
20144   
20145     /* Register layout for all registers TXFR ... */
20146     typedef union {                      /* Transmit FIFO Registers */
20147       vuint32_t R;
20148       struct {
20149   
20150   #ifndef USE_FIELD_ALIASES_DSPI
20151   
20152         vuint32_t FIFO_TXCMD:16;         /* Transmit Command */
20153   
20154   #else
20155   
20156         vuint32_t TXCMD:16;              /* deprecated name - please avoid */
20157   
20158   #endif
20159   
20160   #ifndef USE_FIELD_ALIASES_DSPI
20161   
20162         vuint32_t FIFO_TXDATA:16;        /* Transmit Data */
20163   
20164   #else
20165   
20166         vuint32_t TXDATA:16;             /* deprecated name - please avoid */
20167   
20168   #endif
20169   
20170       } B;
20171     } DSPI_TXFR_32B_tag;
20172   
20173     /* Register layout for all registers RXFR ... */
20174     typedef union {                      /* Receive FIFO Registers */
20175       vuint32_t R;
20176       struct {
20177        vuint32_t:
20178         16;
20179   
20180   #ifndef USE_FIELD_ALIASES_DSPI
20181   
20182         vuint32_t FIFO_RXDATA:16;        /* Transmit Data */
20183   
20184   #else
20185   
20186         vuint32_t RXDATA:16;             /* deprecated name - please avoid */
20187   
20188   #endif
20189   
20190       } B;
20191     } DSPI_RXFR_32B_tag;
20192   
20193     typedef union {                      /* DSICR - DSI Configuration Register */
20194       vuint32_t R;
20195       struct {
20196         vuint32_t MTOE:1;                /* Multiple Transfer Operation Enable */
20197         vuint32_t DSI_FMSZ:1;            /* MSB of the frame size */
20198         vuint32_t MTOCNT:6;              /* Multiple Transfer Operation Count */
20199        vuint32_t:
20200         3;
20201         vuint32_t TSBC:1;                /* Timed Serial Bus Configuration */
20202         vuint32_t TXSS:1;                /* Transmit Data Source Select */
20203         vuint32_t TPOL:1;                /* Trigger Polarity */
20204         vuint32_t TRRE:1;                /* Trigger Reception Enable */
20205         vuint32_t CID:1;                 /* Change in Data Transfer Enable */
20206         vuint32_t DCONT:1;               /* DSI Continuous Peripheral Chip Select Enable */
20207         vuint32_t DSICTAS:3;             /* DSI CLock and Transfer Attributes Select */
20208         vuint32_t DMS:1;                 /* Data Match Stop */
20209         vuint32_t DSI_PES:1;             /* Parity Error Stop */
20210         vuint32_t DSI_PE:1;              /* Parity Enable */
20211         vuint32_t DSI_PP:1;              /* Parity Polarity */
20212         vuint32_t DPCS7:1;               /* DSI Peripheral Chip Select 7 */
20213         vuint32_t DPCS6:1;               /* DSI Peripheral Chip Select 6 */
20214         vuint32_t DPCS5:1;               /* DSI Peripheral Chip Select 5 */
20215         vuint32_t DPCS4:1;               /* DSI Peripheral Chip Select 4 */
20216         vuint32_t DPCS3:1;               /* DSI Peripheral Chip Select 3 */
20217         vuint32_t DPCS2:1;               /* DSI Peripheral Chip Select 2 */
20218         vuint32_t DPCS1:1;               /* DSI Peripheral Chip Select 1 */
20219         vuint32_t DPCS0:1;               /* DSI Peripheral Chip Select 0 */
20220       } B;
20221     } DSPI_DSICR_32B_tag;
20222   
20223     typedef union {                      /* SDR - DSI Serialization Data Register */
20224       vuint32_t R;
20225       struct {
20226        vuint32_t:
20227         16;
20228         vuint32_t SER_DATA:16;           /* Serialized Data */
20229       } B;
20230     } DSPI_SDR_32B_tag;
20231   
20232     typedef union {                      /* ASDR - DSI Alternate Serialization Data Register */
20233       vuint32_t R;
20234       struct {
20235        vuint32_t:
20236         16;
20237         vuint32_t ASER_DATA:16;          /* Alternate Serialized Data */
20238       } B;
20239     } DSPI_ASDR_32B_tag;
20240   
20241     typedef union {                      /* COMPR - DSI Transmit Comparison Register */
20242       vuint32_t R;
20243       struct {
20244        vuint32_t:
20245         16;
20246         vuint32_t COMP_DATA:16;          /* Compare Data */
20247       } B;
20248     } DSPI_COMPR_32B_tag;
20249   
20250     typedef union {                      /* DDR - DSI Deserialization Data Register */
20251       vuint32_t R;
20252       struct {
20253        vuint32_t:
20254         16;
20255         vuint32_t DESER_DATA:16;         /* Deserialized Data */
20256       } B;
20257     } DSPI_DDR_32B_tag;
20258   
20259     typedef union {                      /* DSICR1 - DSI Configuration Register 1 */
20260       vuint32_t R;
20261       struct {
20262        vuint32_t:
20263         3;
20264         vuint32_t TSBCNT:5;              /* Timed Serial Bus Operation Count */
20265        vuint32_t:
20266         6;
20267         vuint32_t DSE1:1;                /* Data Select Enable1 */
20268         vuint32_t DSE0:1;                /* Data Select Enable0 */
20269        vuint32_t:
20270         8;
20271         vuint32_t DPCS1_7:1;             /* DSI Peripheral Chip Select 7 */
20272         vuint32_t DPCS1_6:1;             /* DSI Peripheral Chip Select 6 */
20273         vuint32_t DPCS1_5:1;             /* DSI Peripheral Chip Select 5 */
20274         vuint32_t DPCS1_4:1;             /* DSI Peripheral Chip Select 4 */
20275         vuint32_t DPCS1_3:1;             /* DSI Peripheral Chip Select 3 */
20276         vuint32_t DPCS1_2:1;             /* DSI Peripheral Chip Select 2 */
20277         vuint32_t DPCS1_1:1;             /* DSI Peripheral Chip Select 1 */
20278         vuint32_t DPCS1_0:1;             /* DSI Peripheral Chip Select 0 */
20279       } B;
20280     } DSPI_DSICR1_32B_tag;
20281   
20282     typedef union {                      /* DSI Serialization Source Select Register */
20283       vuint32_t R;
20284     } DSPI_SSR_32B_tag;
20285   
20286     typedef union {                      /* DSI Parallel Input Select Register 0 */
20287       vuint32_t R;
20288       struct {
20289         vuint32_t IPS7:4;                /* Input Pin Select 7 */
20290         vuint32_t IPS6:4;                /* Input Pin Select 6 */
20291         vuint32_t IPS5:4;                /* Input Pin Select 5 */
20292         vuint32_t IPS4:4;                /* Input Pin Select 4 */
20293         vuint32_t IPS3:4;                /* Input Pin Select 3 */
20294         vuint32_t IPS2:4;                /* Input Pin Select 2 */
20295         vuint32_t IPS1:4;                /* Input Pin Select 1 */
20296         vuint32_t IPS0:4;                /* Input Pin Select 0 */
20297       } B;
20298     } DSPI_PISR0_32B_tag;
20299   
20300     typedef union {                      /* DSI Parallel Input Select Register 1 */
20301       vuint32_t R;
20302       struct {
20303         vuint32_t IPS15:4;               /* Input Pin Select 15 */
20304         vuint32_t IPS14:4;               /* Input Pin Select 14 */
20305         vuint32_t IPS13:4;               /* Input Pin Select 13 */
20306         vuint32_t IPS12:4;               /* Input Pin Select 12 */
20307         vuint32_t IPS11:4;               /* Input Pin Select 11 */
20308         vuint32_t IPS10:4;               /* Input Pin Select 10 */
20309         vuint32_t IPS9:4;                /* Input Pin Select 9 */
20310         vuint32_t IPS8:4;                /* Input Pin Select 8 */
20311       } B;
20312     } DSPI_PISR1_32B_tag;
20313   
20314     typedef union {                      /* DSI Parallel Input Select Register 2 */
20315       vuint32_t R;
20316       struct {
20317         vuint32_t IPS23:4;               /* Input Pin Select 23 */
20318         vuint32_t IPS22:4;               /* Input Pin Select 22 */
20319         vuint32_t IPS21:4;               /* Input Pin Select 21 */
20320         vuint32_t IPS20:4;               /* Input Pin Select 20 */
20321         vuint32_t IPS19:4;               /* Input Pin Select 19 */
20322         vuint32_t IPS18:4;               /* Input Pin Select 18 */
20323         vuint32_t IPS17:4;               /* Input Pin Select 17 */
20324         vuint32_t IPS16:4;               /* Input Pin Select 16 */
20325       } B;
20326     } DSPI_PISR2_32B_tag;
20327   
20328     typedef union {                      /* DSI Parallel Input Select Register 3 */
20329       vuint32_t R;
20330       struct {
20331         vuint32_t IPS31:4;               /* Input Pin Select 31 */
20332         vuint32_t IPS30:4;               /* Input Pin Select 30 */
20333         vuint32_t IPS29:4;               /* Input Pin Select 29 */
20334         vuint32_t IPS28:4;               /* Input Pin Select 28 */
20335         vuint32_t IPS27:4;               /* Input Pin Select 27 */
20336         vuint32_t IPS26:4;               /* Input Pin Select 26 */
20337         vuint32_t IPS25:4;               /* Input Pin Select 25 */
20338         vuint32_t IPS24:4;               /* Input Pin Select 24 */
20339       } B;
20340     } DSPI_PISR3_32B_tag;
20341   
20342     typedef union {                      /* DSI Deserialized Data Interrupt Mask Register */
20343       vuint32_t R;
20344     } DSPI_DIMR_32B_tag;
20345   
20346     typedef union {                      /* DSI Deserialized Data Polarity Interrupt Register */
20347       vuint32_t R;
20348     } DSPI_DPIR_32B_tag;
20349   
20350     typedef struct DSPI_struct_tag {
20351       /* MCR - Module Configuration Register */
20352       DSPI_MCR_32B_tag MCR;              /* offset: 0x0000 size: 32 bit */
20353   
20354       /* HCR - Hardware Configuration Register */
20355       DSPI_HCR_32B_tag HCR;              /* offset: 0x0004 size: 32 bit */
20356   
20357       /* TCR - Transfer Count Register */
20358       DSPI_TCR_32B_tag TCR;              /* offset: 0x0008 size: 32 bit */
20359       union {
20360         struct {
20361           /* CTAR0-1 - Clock and Transfer Attribute Registers (in slave mode) */
20362           DSPI_SLAVE_CTAR_32B_tag SLAVE_CTAR[2];/* offset: 0x000C  (0x0004 x 2) */
20363           int8_t DSPI_reserved_0014_E0[24];
20364         };
20365   
20366         /* CTAR0-7 - Clock and Transfer Attribute Registers */
20367         DSPI_CTAR_32B_tag CTAR[8];       /* offset: 0x000C  (0x0004 x 8) */
20368         struct {
20369           /* CTAR0-1 - Clock and Transfer Attribute Registers (in slave mode) */
20370           DSPI_SLAVE_CTAR_32B_tag SLAVE_CTAR0;/* offset: 0x000C size: 32 bit */
20371           DSPI_SLAVE_CTAR_32B_tag SLAVE_CTAR1;/* offset: 0x0010 size: 32 bit */
20372           int8_t DSPI_reserved_0014_E2[24];
20373         };
20374   
20375         struct {
20376           /* CTAR0-7 - Clock and Transfer Attribute Registers */
20377           DSPI_CTAR_32B_tag CTAR0;       /* offset: 0x000C size: 32 bit */
20378           DSPI_CTAR_32B_tag CTAR1;       /* offset: 0x0010 size: 32 bit */
20379           DSPI_CTAR_32B_tag CTAR2;       /* offset: 0x0014 size: 32 bit */
20380           DSPI_CTAR_32B_tag CTAR3;       /* offset: 0x0018 size: 32 bit */
20381           DSPI_CTAR_32B_tag CTAR4;       /* offset: 0x001C size: 32 bit */
20382           DSPI_CTAR_32B_tag CTAR5;       /* offset: 0x0020 size: 32 bit */
20383           DSPI_CTAR_32B_tag CTAR6;       /* offset: 0x0024 size: 32 bit */
20384           DSPI_CTAR_32B_tag CTAR7;       /* offset: 0x0028 size: 32 bit */
20385         };
20386       };
20387   
20388       /* SR - Status Register */
20389       DSPI_SR_32B_tag SR;                /* offset: 0x002C size: 32 bit */
20390   
20391       /* RSER - DMA/Interrupt Request Register */
20392       DSPI_RSER_32B_tag RSER;            /* offset: 0x0030 size: 32 bit */
20393   
20394       /* PUSHR - PUSH TX FIFO Register */
20395       DSPI_PUSHR_32B_tag PUSHR;          /* offset: 0x0034 size: 32 bit */
20396   
20397       /* POPR - POP RX FIFO Register */
20398       DSPI_POPR_32B_tag POPR;            /* offset: 0x0038 size: 32 bit */
20399       union {
20400         /* Transmit FIFO Registers */
20401         DSPI_TXFR_32B_tag TXFR[5];       /* offset: 0x003C  (0x0004 x 5) */
20402         struct {
20403           /* Transmit FIFO Registers */
20404           DSPI_TXFR_32B_tag TXFR0;       /* offset: 0x003C size: 32 bit */
20405           DSPI_TXFR_32B_tag TXFR1;       /* offset: 0x0040 size: 32 bit */
20406           DSPI_TXFR_32B_tag TXFR2;       /* offset: 0x0044 size: 32 bit */
20407           DSPI_TXFR_32B_tag TXFR3;       /* offset: 0x0048 size: 32 bit */
20408           DSPI_TXFR_32B_tag TXFR4;       /* offset: 0x004C size: 32 bit */
20409         };
20410       };
20411   
20412       int8_t DSPI_reserved_0050[44];
20413       union {
20414         /* Receive FIFO Registers */
20415         DSPI_RXFR_32B_tag RXFR[5];       /* offset: 0x007C  (0x0004 x 5) */
20416         struct {
20417           /* Receive FIFO Registers */
20418           DSPI_RXFR_32B_tag RXFR0;       /* offset: 0x007C size: 32 bit */
20419           DSPI_RXFR_32B_tag RXFR1;       /* offset: 0x0080 size: 32 bit */
20420           DSPI_RXFR_32B_tag RXFR2;       /* offset: 0x0084 size: 32 bit */
20421           DSPI_RXFR_32B_tag RXFR3;       /* offset: 0x0088 size: 32 bit */
20422           DSPI_RXFR_32B_tag RXFR4;       /* offset: 0x008C size: 32 bit */
20423         };
20424       };
20425   
20426       int8_t DSPI_reserved_0090[44];
20427   
20428       /* DSICR - DSI Configuration Register */
20429       DSPI_DSICR_32B_tag DSICR;          /* offset: 0x00BC size: 32 bit */
20430   
20431       /* SDR - DSI Serialization Data Register */
20432       DSPI_SDR_32B_tag SDR;              /* offset: 0x00C0 size: 32 bit */
20433   
20434       /* ASDR - DSI Alternate Serialization Data Register */
20435       DSPI_ASDR_32B_tag ASDR;            /* offset: 0x00C4 size: 32 bit */
20436   
20437       /* COMPR - DSI Transmit Comparison Register */
20438       DSPI_COMPR_32B_tag COMPR;          /* offset: 0x00C8 size: 32 bit */
20439   
20440       /* DDR - DSI Deserialization Data Register */
20441       DSPI_DDR_32B_tag DDR;              /* offset: 0x00CC size: 32 bit */
20442   
20443       /* DSICR1 - DSI Configuration Register 1 */
20444       DSPI_DSICR1_32B_tag DSICR1;        /* offset: 0x00D0 size: 32 bit */
20445   
20446       /* DSI Serialization Source Select Register */
20447       DSPI_SSR_32B_tag SSR;              /* offset: 0x00D4 size: 32 bit */
20448   
20449       /* DSI Parallel Input Select Register 0 */
20450       DSPI_PISR0_32B_tag PISR0;          /* offset: 0x00D8 size: 32 bit */
20451   
20452       /* DSI Parallel Input Select Register 1 */
20453       DSPI_PISR1_32B_tag PISR1;          /* offset: 0x00DC size: 32 bit */
20454   
20455       /* DSI Parallel Input Select Register 2 */
20456       DSPI_PISR2_32B_tag PISR2;          /* offset: 0x00E0 size: 32 bit */
20457   
20458       /* DSI Parallel Input Select Register 3 */
20459       DSPI_PISR3_32B_tag PISR3;          /* offset: 0x00E4 size: 32 bit */
20460   
20461       /* DSI Deserialized Data Interrupt Mask Register */
20462       DSPI_DIMR_32B_tag DIMR;            /* offset: 0x00E8 size: 32 bit */
20463   
20464       /* DSI Deserialized Data Polarity Interrupt Register */
20465       DSPI_DPIR_32B_tag DPIR;            /* offset: 0x00EC size: 32 bit */
20466       int8_t DSPI_reserved_00F0[16144];
20467     } DSPI_tag;
20468   
20469   #define DSPI_A                         (*(volatile DSPI_tag *) 0xFFF90000UL)
20470   #define DSPI_B                         (*(volatile DSPI_tag *) 0xFFF94000UL)
20471   #define DSPI_C                         (*(volatile DSPI_tag *) 0xFFF98000UL)
20472   
20473     /****************************************************************/
20474     /*                                                              */
20475     /* Module: FLEXCAN  */
20476     /*                                                              */
20477     /****************************************************************/
20478     typedef union {                      /* MCR - Module Configuration Register */
20479       vuint32_t R;
20480       struct {
20481         vuint32_t MDIS:1;                /* Module Disable */
20482         vuint32_t FRZ:1;                 /* Freeze Enable */
20483         vuint32_t FEN:1;                 /* FIFO Enable */
20484         vuint32_t HALT:1;                /* Halt Flexcan */
20485   
20486   #ifndef USE_FIELD_ALIASES_FLEXCAN
20487   
20488         vuint32_t NOT_RDY:1;             /* Flexcan Not Ready */
20489   
20490   #else
20491   
20492         vuint32_t NOTRDY:1;              /* deprecated name - please avoid */
20493   
20494   #endif
20495   
20496   #ifndef USE_FIELD_ALIASES_FLEXCAN
20497   
20498         vuint32_t WAK_MSK:1;             /* Wake Up Interrupt Mask */
20499   
20500   #else
20501   
20502         vuint32_t WAKMSK:1;              /* deprecated name - please avoid */
20503   
20504   #endif
20505   
20506   #ifndef USE_FIELD_ALIASES_FLEXCAN
20507   
20508         vuint32_t SOFT_RST:1;            /* Soft Reset */
20509   
20510   #else
20511   
20512         vuint32_t SOFTRST:1;             /* deprecated name - please avoid */
20513   
20514   #endif
20515   
20516   #ifndef USE_FIELD_ALIASES_FLEXCAN
20517   
20518         vuint32_t FRZ_ACK:1;             /* Freeze Mode Acknowledge */
20519   
20520   #else
20521   
20522         vuint32_t FRZACK:1;              /* deprecated name - please avoid */
20523   
20524   #endif
20525   
20526         vuint32_t SUPV:1;                /* Supervisor Mode */
20527   
20528   #ifndef USE_FIELD_ALIASES_FLEXCAN
20529   
20530         vuint32_t SLF_WAK:1;             /* Self Wake Up */
20531   
20532   #else
20533   
20534         vuint32_t SLFWAK:1;              /* deprecated name - please avoid */
20535   
20536   #endif
20537   
20538   #ifndef USE_FIELD_ALIASES_FLEXCAN
20539   
20540         vuint32_t WRN_EN:1;              /* Warning Interrupt Enable */
20541   
20542   #else
20543   
20544         vuint32_t WRNEN:1;               /* deprecated name - please avoid */
20545   
20546   #endif
20547   
20548   #ifndef USE_FIELD_ALIASES_FLEXCAN
20549   
20550         vuint32_t LPM_ACK:1;             /* Low Power Mode Acknowledge */
20551   
20552   #else
20553   
20554         vuint32_t LPMACK:1;              /* deprecated name - please avoid */
20555   
20556   #endif
20557   
20558   #ifndef USE_FIELD_ALIASES_FLEXCAN
20559   
20560         vuint32_t WAK_SRC:1;             /* Wake Up Source */
20561   
20562   #else
20563   
20564         vuint32_t WAKSRC:1;              /* deprecated name - please avoid */
20565   
20566   #endif
20567   
20568         vuint32_t DOZE:1;                /* Doze Mode Enable */
20569   
20570   #ifndef USE_FIELD_ALIASES_FLEXCAN
20571   
20572         vuint32_t SRX_DIS:1;             /* Self Reception Disable */
20573   
20574   #else
20575   
20576         vuint32_t SRXDIS:1;              /* deprecated name - please avoid */
20577   
20578   #endif
20579   
20580         vuint32_t BCC:1;                 /* Backwards Compatibility Configuration */
20581        vuint32_t:
20582         2;
20583         vuint32_t LPRIO_EN:1;            /* Local Priority Enable */
20584         vuint32_t AEN:1;                 /* Abort Enable */
20585        vuint32_t:
20586         2;
20587         vuint32_t IDAM:2;                /* ID Acceptance Mode */
20588        vuint32_t:
20589         2;
20590         vuint32_t MAXMB:6;               /* Maximum Number of Message Buffers */
20591       } B;
20592     } FLEXCAN_MCR_32B_tag;
20593   
20594     typedef union {                      /* CTRL -  Control Register */
20595       vuint32_t R;
20596       struct {
20597         vuint32_t PRESDIV:8;             /* Prescaler Divsion Factor */
20598         vuint32_t RJW:2;                 /* Resync Jump Width */
20599         vuint32_t PSEG1:3;               /* Phase Segment 1 */
20600         vuint32_t PSEG2:3;               /* Phase Segment 2 */
20601   
20602   #ifndef USE_FIELD_ALIASES_FLEXCAN
20603   
20604         vuint32_t BOFF_MSK:1;            /* Bus Off Mask */
20605   
20606   #else
20607   
20608         vuint32_t BOFFMSK:1;             /* deprecated name - please avoid */
20609   
20610   #endif
20611   
20612   #ifndef USE_FIELD_ALIASES_FLEXCAN
20613   
20614         vuint32_t ERR_MSK:1;             /* Error Mask */
20615   
20616   #else
20617   
20618         vuint32_t ERRMSK:1;              /* deprecated name - please avoid */
20619   
20620   #endif
20621   
20622   #ifndef USE_FIELD_ALIASES_FLEXCAN
20623   
20624         vuint32_t CLK_SRC:1;             /* CAN Engine Clock Source */
20625   
20626   #else
20627   
20628         vuint32_t CLKSRC:1;              /* deprecated name - please avoid */
20629   
20630   #endif
20631   
20632         vuint32_t LPB:1;                 /* Loop Back */
20633   
20634   #ifndef USE_FIELD_ALIASES_FLEXCAN
20635   
20636         vuint32_t TWRN_MSK:1;            /* Tx Warning Interrupt Mask */
20637   
20638   #else
20639   
20640         vuint32_t TWRNMSK:1;             /* deprecated name - please avoid */
20641   
20642   #endif
20643   
20644   #ifndef USE_FIELD_ALIASES_FLEXCAN
20645   
20646         vuint32_t RWRN_MSK:1;            /* Rx Warning Interrupt Mask */
20647   
20648   #else
20649   
20650         vuint32_t RWRNMSK:1;             /* deprecated name - please avoid */
20651   
20652   #endif
20653   
20654        vuint32_t:
20655         2;
20656         vuint32_t SMP:1;                 /* Sampling Mode */
20657   
20658   #ifndef USE_FIELD_ALIASES_FLEXCAN
20659   
20660         vuint32_t BOFF_REC:1;            /* Bus Off Recovery Mode */
20661   
20662   #else
20663   
20664         vuint32_t BOFFREC:1;             /* deprecated name - please avoid */
20665   
20666   #endif
20667   
20668         vuint32_t TSYN:1;                /* Timer Sync Mode */
20669         vuint32_t LBUF:1;                /* Lowest Buffer Transmitted First */
20670         vuint32_t LOM:1;                 /* Listen-Only Mode */
20671         vuint32_t PROPSEG:3;             /* Propagation Segment */
20672       } B;
20673     } FLEXCAN_CTRL_32B_tag;
20674   
20675     typedef union {                      /* TIMER - Free Running Timer */
20676       vuint32_t R;
20677     } FLEXCAN_TIMER_32B_tag;
20678   
20679     typedef union {                      /* RXGMASK - Rx Global Mask Register */
20680       vuint32_t R;
20681   
20682   #ifdef USE_FIELD_ALIASES_FLEXCAN
20683   
20684       struct {
20685         vuint32_t MI:32;                 /* deprecated field -- do not use */
20686       } B;
20687   
20688   #endif
20689   
20690     } FLEXCAN_RXGMASK_32B_tag;
20691   
20692     typedef union {                      /* RX14MASK - Rx 14 Mask Register */
20693       vuint32_t R;
20694   
20695   #ifdef USE_FIELD_ALIASES_FLEXCAN
20696   
20697       struct {
20698         vuint32_t MI:32;                 /* deprecated field -- do not use */
20699       } B;
20700   
20701   #endif
20702   
20703     } FLEXCAN_RX14MASK_32B_tag;
20704   
20705     typedef union {                      /* RX15MASK - Rx 15 Mask Register */
20706       vuint32_t R;
20707   
20708   #ifdef USE_FIELD_ALIASES_FLEXCAN
20709   
20710       struct {
20711         vuint32_t MI:32;                 /* deprecated field -- do not use */
20712       } B;
20713   
20714   #endif
20715   
20716     } FLEXCAN_RX15MASK_32B_tag;
20717   
20718     typedef union {                      /* ECR - Error Counter Register */
20719       vuint32_t R;
20720       struct {
20721        vuint32_t:
20722         16;
20723   
20724   #ifndef USE_FIELD_ALIASES_FLEXCAN
20725   
20726         vuint32_t RX_ERR_COUNTER:8;      /* Rx Error Counter */
20727   
20728   #else
20729   
20730         vuint32_t RXECNT:8;              /* deprecated name - please avoid */
20731   
20732   #endif
20733   
20734   #ifndef USE_FIELD_ALIASES_FLEXCAN
20735   
20736         vuint32_t TX_ERR_COUNTER:8;      /* Tx Error Counter */
20737   
20738   #else
20739   
20740         vuint32_t TXECNT:8;              /* deprecated name - please avoid */
20741   
20742   #endif
20743   
20744       } B;
20745     } FLEXCAN_ECR_32B_tag;
20746   
20747     typedef union {                      /* ESR - Error and Status Register */
20748       vuint32_t R;
20749       struct {
20750        vuint32_t:
20751         14;
20752   
20753   #ifndef USE_FIELD_ALIASES_FLEXCAN
20754   
20755         vuint32_t TWRN_INT:1;            /* Tx Warning Interrupt Flag */
20756   
20757   #else
20758   
20759         vuint32_t TWRNINT:1;             /* deprecated name - please avoid */
20760   
20761   #endif
20762   
20763   #ifndef USE_FIELD_ALIASES_FLEXCAN
20764   
20765         vuint32_t RWRN_INT:1;            /* Rx Warning Interrupt Flag */
20766   
20767   #else
20768   
20769         vuint32_t RWRNINT:1;             /* deprecated name - please avoid */
20770   
20771   #endif
20772   
20773   #ifndef USE_FIELD_ALIASES_FLEXCAN
20774   
20775         vuint32_t BIT1_ERR:1;            /* Bit 1 Error */
20776   
20777   #else
20778   
20779         vuint32_t BIT1ERR:1;             /* deprecated name - please avoid */
20780   
20781   #endif
20782   
20783   #ifndef USE_FIELD_ALIASES_FLEXCAN
20784   
20785         vuint32_t BIT0_ERR:1;            /* Bit 0 Error */
20786   
20787   #else
20788   
20789         vuint32_t BIT0ERR:1;             /* deprecated name - please avoid */
20790   
20791   #endif
20792   
20793   #ifndef USE_FIELD_ALIASES_FLEXCAN
20794   
20795         vuint32_t ACK_ERR:1;             /* Acknowledge Error */
20796   
20797   #else
20798   
20799         vuint32_t ACKERR:1;              /* deprecated name - please avoid */
20800   
20801   #endif
20802   
20803   #ifndef USE_FIELD_ALIASES_FLEXCAN
20804   
20805         vuint32_t CRC_ERR:1;             /* Cyclic Redundancy Check Error */
20806   
20807   #else
20808   
20809         vuint32_t CRCERR:1;              /* deprecated name - please avoid */
20810   
20811   #endif
20812   
20813   #ifndef USE_FIELD_ALIASES_FLEXCAN
20814   
20815         vuint32_t FRM_ERR:1;             /* Form Error */
20816   
20817   #else
20818   
20819         vuint32_t FRMERR:1;              /* deprecated name - please avoid */
20820   
20821   #endif
20822   
20823   #ifndef USE_FIELD_ALIASES_FLEXCAN
20824   
20825         vuint32_t STF_ERR:1;             /* Stuffing Error */
20826   
20827   #else
20828   
20829         vuint32_t STFERR:1;              /* deprecated name - please avoid */
20830   
20831   #endif
20832   
20833   #ifndef USE_FIELD_ALIASES_FLEXCAN
20834   
20835         vuint32_t TX_WRN:1;              /* Tx Error Counter */
20836   
20837   #else
20838   
20839         vuint32_t TXWRN:1;               /* deprecated name - please avoid */
20840   
20841   #endif
20842   
20843   #ifndef USE_FIELD_ALIASES_FLEXCAN
20844   
20845         vuint32_t RX_WRN:1;              /* Rx Error Counter */
20846   
20847   #else
20848   
20849         vuint32_t RXWRN:1;               /* deprecated name - please avoid */
20850   
20851   #endif
20852   
20853         vuint32_t IDLE:1;                /* CAN bus Idle State */
20854         vuint32_t TXRX:1;                /* Current Flexcan Status */
20855   
20856   #ifndef USE_FIELD_ALIASES_FLEXCAN
20857   
20858         vuint32_t FLT_CONF:2;            /* Fault Confinement State */
20859   
20860   #else
20861   
20862         vuint32_t FLTCONF:2;             /* deprecated name - please avoid */
20863   
20864   #endif
20865   
20866        vuint32_t:
20867         1;
20868   
20869   #ifndef USE_FIELD_ALIASES_FLEXCAN
20870   
20871         vuint32_t BOFF_INT:1;            /* Bus Off Interrupt */
20872   
20873   #else
20874   
20875         vuint32_t BOFFINT:1;             /* deprecated name - please avoid */
20876   
20877   #endif
20878   
20879   #ifndef USE_FIELD_ALIASES_FLEXCAN
20880   
20881         vuint32_t ERR_INT:1;             /* Error Interrupt */
20882   
20883   #else
20884   
20885         vuint32_t ERRINT:1;              /* deprecated name - please avoid */
20886   
20887   #endif
20888   
20889   #ifndef USE_FIELD_ALIASES_FLEXCAN
20890   
20891         vuint32_t WAK_INT:1;             /* Wake-Up Interrupt */
20892   
20893   #else
20894   
20895         vuint32_t WAKINT:1;              /* deprecated name - please avoid */
20896   
20897   #endif
20898   
20899       } B;
20900     } FLEXCAN_ESR_32B_tag;
20901   
20902     typedef union {                      /* IMASK2 - Interrupt Masks 2 Register */
20903       vuint32_t R;
20904       struct {
20905         vuint32_t BUF63M:1;              /* Buffer MB Mask 63 Bit */
20906         vuint32_t BUF62M:1;              /* Buffer MB Mask 62 Bit */
20907         vuint32_t BUF61M:1;              /* Buffer MB Mask 61 Bit */
20908         vuint32_t BUF60M:1;              /* Buffer MB Mask 60 Bit */
20909         vuint32_t BUF59M:1;              /* Buffer MB Mask 59 Bit */
20910         vuint32_t BUF58M:1;              /* Buffer MB Mask 58 Bit */
20911         vuint32_t BUF57M:1;              /* Buffer MB Mask 57 Bit */
20912         vuint32_t BUF56M:1;              /* Buffer MB Mask 56 Bit */
20913         vuint32_t BUF55M:1;              /* Buffer MB Mask 55 Bit */
20914         vuint32_t BUF54M:1;              /* Buffer MB Mask 54 Bit */
20915         vuint32_t BUF53M:1;              /* Buffer MB Mask 53 Bit */
20916         vuint32_t BUF52M:1;              /* Buffer MB Mask 52 Bit */
20917         vuint32_t BUF51M:1;              /* Buffer MB Mask 51 Bit */
20918         vuint32_t BUF50M:1;              /* Buffer MB Mask 50 Bit */
20919         vuint32_t BUF49M:1;              /* Buffer MB Mask 49 Bit */
20920         vuint32_t BUF48M:1;              /* Buffer MB Mask 48 Bit */
20921         vuint32_t BUF47M:1;              /* Buffer MB Mask 47 Bit */
20922         vuint32_t BUF46M:1;              /* Buffer MB Mask 46 Bit */
20923         vuint32_t BUF45M:1;              /* Buffer MB Mask 45 Bit */
20924         vuint32_t BUF44M:1;              /* Buffer MB Mask 44 Bit */
20925         vuint32_t BUF43M:1;              /* Buffer MB Mask 43 Bit */
20926         vuint32_t BUF42M:1;              /* Buffer MB Mask 42 Bit */
20927         vuint32_t BUF41M:1;              /* Buffer MB Mask 41 Bit */
20928         vuint32_t BUF40M:1;              /* Buffer MB Mask 40 Bit */
20929         vuint32_t BUF39M:1;              /* Buffer MB Mask 39 Bit */
20930         vuint32_t BUF38M:1;              /* Buffer MB Mask 38 Bit */
20931         vuint32_t BUF37M:1;              /* Buffer MB Mask 37 Bit */
20932         vuint32_t BUF36M:1;              /* Buffer MB Mask 36 Bit */
20933         vuint32_t BUF35M:1;              /* Buffer MB Mask 35 Bit */
20934         vuint32_t BUF34M:1;              /* Buffer MB Mask 34 Bit */
20935         vuint32_t BUF33M:1;              /* Buffer MB Mask 33 Bit */
20936         vuint32_t BUF32M:1;              /* Buffer MB Mask 32 Bit */
20937       } B;
20938     } FLEXCAN_IMASK2_32B_tag;
20939   
20940     typedef union {                      /* IMASK1 - Interrupt Masks 1 Register */
20941       vuint32_t R;
20942       struct {
20943         vuint32_t BUF31M:1;              /* Buffer MB Mask 31 Bit */
20944         vuint32_t BUF30M:1;              /* Buffer MB Mask 30 Bit */
20945         vuint32_t BUF29M:1;              /* Buffer MB Mask 29 Bit */
20946         vuint32_t BUF28M:1;              /* Buffer MB Mask 28 Bit */
20947         vuint32_t BUF27M:1;              /* Buffer MB Mask 27 Bit */
20948         vuint32_t BUF26M:1;              /* Buffer MB Mask 26 Bit */
20949         vuint32_t BUF25M:1;              /* Buffer MB Mask 25 Bit */
20950         vuint32_t BUF24M:1;              /* Buffer MB Mask 24 Bit */
20951         vuint32_t BUF23M:1;              /* Buffer MB Mask 23 Bit */
20952         vuint32_t BUF22M:1;              /* Buffer MB Mask 22 Bit */
20953         vuint32_t BUF21M:1;              /* Buffer MB Mask 21 Bit */
20954         vuint32_t BUF20M:1;              /* Buffer MB Mask 20 Bit */
20955         vuint32_t BUF19M:1;              /* Buffer MB Mask 19 Bit */
20956         vuint32_t BUF18M:1;              /* Buffer MB Mask 18 Bit */
20957         vuint32_t BUF17M:1;              /* Buffer MB Mask 17 Bit */
20958         vuint32_t BUF16M:1;              /* Buffer MB Mask 16 Bit */
20959         vuint32_t BUF15M:1;              /* Buffer MB Mask 15 Bit */
20960         vuint32_t BUF14M:1;              /* Buffer MB Mask 14 Bit */
20961         vuint32_t BUF13M:1;              /* Buffer MB Mask 13 Bit */
20962         vuint32_t BUF12M:1;              /* Buffer MB Mask 12 Bit */
20963         vuint32_t BUF11M:1;              /* Buffer MB Mask 11 Bit */
20964         vuint32_t BUF10M:1;              /* Buffer MB Mask 10 Bit */
20965   
20966   #ifndef USE_FIELD_ALIASES_FLEXCAN
20967   
20968         vuint32_t BUF9M:1;               /* Buffer MB Mask 9 Bit */
20969   
20970   #else
20971   
20972         vuint32_t BUF09M:1;              /* deprecated name - please avoid */
20973   
20974   #endif
20975   
20976   #ifndef USE_FIELD_ALIASES_FLEXCAN
20977   
20978         vuint32_t BUF8M:1;               /* Buffer MB Mask 8 Bit */
20979   
20980   #else
20981   
20982         vuint32_t BUF08M:1;              /* deprecated name - please avoid */
20983   
20984   #endif
20985   
20986   #ifndef USE_FIELD_ALIASES_FLEXCAN
20987   
20988         vuint32_t BUF7M:1;               /* Buffer MB Mask 7 Bit */
20989   
20990   #else
20991   
20992         vuint32_t BUF07M:1;              /* deprecated name - please avoid */
20993   
20994   #endif
20995   
20996   #ifndef USE_FIELD_ALIASES_FLEXCAN
20997   
20998         vuint32_t BUF6M:1;               /* Buffer MB Mask 6 Bit */
20999   
21000   #else
21001   
21002         vuint32_t BUF06M:1;              /* deprecated name - please avoid */
21003   
21004   #endif
21005   
21006   #ifndef USE_FIELD_ALIASES_FLEXCAN
21007   
21008         vuint32_t BUF5M:1;               /* Buffer MB Mask 5 Bit */
21009   
21010   #else
21011   
21012         vuint32_t BUF05M:1;              /* deprecated name - please avoid */
21013   
21014   #endif
21015   
21016   #ifndef USE_FIELD_ALIASES_FLEXCAN
21017   
21018         vuint32_t BUF4M:1;               /* Buffer MB Mask 4 Bit */
21019   
21020   #else
21021   
21022         vuint32_t BUF04M:1;              /* deprecated name - please avoid */
21023   
21024   #endif
21025   
21026   #ifndef USE_FIELD_ALIASES_FLEXCAN
21027   
21028         vuint32_t BUF3M:1;               /* Buffer MB Mask 3 Bit */
21029   
21030   #else
21031   
21032         vuint32_t BUF03M:1;              /* deprecated name - please avoid */
21033   
21034   #endif
21035   
21036   #ifndef USE_FIELD_ALIASES_FLEXCAN
21037   
21038         vuint32_t BUF2M:1;               /* Buffer MB Mask 2 Bit */
21039   
21040   #else
21041   
21042         vuint32_t BUF02M:1;              /* deprecated name - please avoid */
21043   
21044   #endif
21045   
21046   #ifndef USE_FIELD_ALIASES_FLEXCAN
21047   
21048         vuint32_t BUF1M:1;               /* Buffer MB Mask 1 Bit */
21049   
21050   #else
21051   
21052         vuint32_t BUF01M:1;              /* deprecated name - please avoid */
21053   
21054   #endif
21055   
21056   #ifndef USE_FIELD_ALIASES_FLEXCAN
21057   
21058         vuint32_t BUF0M:1;               /* Buffer MB Mask 0 Bit */
21059   
21060   #else
21061   
21062         vuint32_t BUF00M:1;              /* deprecated name - please avoid */
21063   
21064   #endif
21065   
21066       } B;
21067     } FLEXCAN_IMASK1_32B_tag;
21068   
21069     typedef union {                      /* IFLAG2 - Interrupt Flags 2 Register */
21070       vuint32_t R;
21071       struct {
21072         vuint32_t BUF63I:1;              /* Buffer MB Interrupt 63 Bit */
21073         vuint32_t BUF62I:1;              /* Buffer MB Interrupt 62 Bit */
21074         vuint32_t BUF61I:1;              /* Buffer MB Interrupt 61 Bit */
21075         vuint32_t BUF60I:1;              /* Buffer MB Interrupt 60 Bit */
21076         vuint32_t BUF59I:1;              /* Buffer MB Interrupt 59 Bit */
21077         vuint32_t BUF58I:1;              /* Buffer MB Interrupt 58 Bit */
21078         vuint32_t BUF57I:1;              /* Buffer MB Interrupt 57 Bit */
21079         vuint32_t BUF56I:1;              /* Buffer MB Interrupt 56 Bit */
21080         vuint32_t BUF55I:1;              /* Buffer MB Interrupt 55 Bit */
21081         vuint32_t BUF54I:1;              /* Buffer MB Interrupt 54 Bit */
21082         vuint32_t BUF53I:1;              /* Buffer MB Interrupt 53 Bit */
21083         vuint32_t BUF52I:1;              /* Buffer MB Interrupt 52 Bit */
21084         vuint32_t BUF51I:1;              /* Buffer MB Interrupt 51 Bit */
21085         vuint32_t BUF50I:1;              /* Buffer MB Interrupt 50 Bit */
21086         vuint32_t BUF49I:1;              /* Buffer MB Interrupt 49 Bit */
21087         vuint32_t BUF48I:1;              /* Buffer MB Interrupt 48 Bit */
21088         vuint32_t BUF47I:1;              /* Buffer MB Interrupt 47 Bit */
21089         vuint32_t BUF46I:1;              /* Buffer MB Interrupt 46 Bit */
21090         vuint32_t BUF45I:1;              /* Buffer MB Interrupt 45 Bit */
21091         vuint32_t BUF44I:1;              /* Buffer MB Interrupt 44 Bit */
21092         vuint32_t BUF43I:1;              /* Buffer MB Interrupt 43 Bit */
21093         vuint32_t BUF42I:1;              /* Buffer MB Interrupt 42 Bit */
21094         vuint32_t BUF41I:1;              /* Buffer MB Interrupt 41 Bit */
21095         vuint32_t BUF40I:1;              /* Buffer MB Interrupt 40 Bit */
21096         vuint32_t BUF39I:1;              /* Buffer MB Interrupt 39 Bit */
21097         vuint32_t BUF38I:1;              /* Buffer MB Interrupt 38 Bit */
21098         vuint32_t BUF37I:1;              /* Buffer MB Interrupt 37 Bit */
21099         vuint32_t BUF36I:1;              /* Buffer MB Interrupt 36 Bit */
21100         vuint32_t BUF35I:1;              /* Buffer MB Interrupt 35 Bit */
21101         vuint32_t BUF34I:1;              /* Buffer MB Interrupt 34 Bit */
21102         vuint32_t BUF33I:1;              /* Buffer MB Interrupt 33 Bit */
21103         vuint32_t BUF32I:1;              /* Buffer MB Interrupt 32 Bit */
21104       } B;
21105     } FLEXCAN_IFLAG2_32B_tag;
21106   
21107     typedef union {                      /* IFLAG1 - Interrupt Flags 1 Register */
21108       vuint32_t R;
21109       struct {
21110         vuint32_t BUF31I:1;              /* Buffer MB Interrupt 31 Bit */
21111         vuint32_t BUF30I:1;              /* Buffer MB Interrupt 30 Bit */
21112         vuint32_t BUF29I:1;              /* Buffer MB Interrupt 29 Bit */
21113         vuint32_t BUF28I:1;              /* Buffer MB Interrupt 28 Bit */
21114         vuint32_t BUF27I:1;              /* Buffer MB Interrupt 27 Bit */
21115         vuint32_t BUF26I:1;              /* Buffer MB Interrupt 26 Bit */
21116         vuint32_t BUF25I:1;              /* Buffer MB Interrupt 25 Bit */
21117         vuint32_t BUF24I:1;              /* Buffer MB Interrupt 24 Bit */
21118         vuint32_t BUF23I:1;              /* Buffer MB Interrupt 23 Bit */
21119         vuint32_t BUF22I:1;              /* Buffer MB Interrupt 22 Bit */
21120         vuint32_t BUF21I:1;              /* Buffer MB Interrupt 21 Bit */
21121         vuint32_t BUF20I:1;              /* Buffer MB Interrupt 20 Bit */
21122         vuint32_t BUF19I:1;              /* Buffer MB Interrupt 19 Bit */
21123         vuint32_t BUF18I:1;              /* Buffer MB Interrupt 18 Bit */
21124         vuint32_t BUF17I:1;              /* Buffer MB Interrupt 17 Bit */
21125         vuint32_t BUF16I:1;              /* Buffer MB Interrupt 16 Bit */
21126         vuint32_t BUF15I:1;              /* Buffer MB Interrupt 15 Bit */
21127         vuint32_t BUF14I:1;              /* Buffer MB Interrupt 14 Bit */
21128         vuint32_t BUF13I:1;              /* Buffer MB Interrupt 13 Bit */
21129         vuint32_t BUF12I:1;              /* Buffer MB Interrupt 12 Bit */
21130         vuint32_t BUF11I:1;              /* Buffer MB Interrupt 11 Bit */
21131         vuint32_t BUF10I:1;              /* Buffer MB Interrupt 10 Bit */
21132   
21133   #ifndef USE_FIELD_ALIASES_FLEXCAN
21134   
21135         vuint32_t BUF9I:1;               /* Buffer MB Interrupt 9 Bit */
21136   
21137   #else
21138   
21139         vuint32_t BUF09I:1;              /* deprecated name - please avoid */
21140   
21141   #endif
21142   
21143   #ifndef USE_FIELD_ALIASES_FLEXCAN
21144   
21145         vuint32_t BUF8I:1;               /* Buffer MB Interrupt 8 Bit */
21146   
21147   #else
21148   
21149         vuint32_t BUF08I:1;              /* deprecated name - please avoid */
21150   
21151   #endif
21152   
21153   #ifndef USE_FIELD_ALIASES_FLEXCAN
21154   
21155         vuint32_t BUF7I:1;               /* Buffer MB Interrupt 7 Bit */
21156   
21157   #else
21158   
21159         vuint32_t BUF07I:1;              /* deprecated name - please avoid */
21160   
21161   #endif
21162   
21163   #ifndef USE_FIELD_ALIASES_FLEXCAN
21164   
21165         vuint32_t BUF6I:1;               /* Buffer MB Interrupt 6 Bit */
21166   
21167   #else
21168   
21169         vuint32_t BUF06I:1;              /* deprecated name - please avoid */
21170   
21171   #endif
21172   
21173   #ifndef USE_FIELD_ALIASES_FLEXCAN
21174   
21175         vuint32_t BUF5I:1;               /* Buffer MB Interrupt 5 Bit */
21176   
21177   #else
21178   
21179         vuint32_t BUF05I:1;              /* deprecated name - please avoid */
21180   
21181   #endif
21182   
21183   #ifndef USE_FIELD_ALIASES_FLEXCAN
21184   
21185         vuint32_t BUF4I:1;               /* Buffer MB Interrupt 4 Bit */
21186   
21187   #else
21188   
21189         vuint32_t BUF04I:1;              /* deprecated name - please avoid */
21190   
21191   #endif
21192   
21193   #ifndef USE_FIELD_ALIASES_FLEXCAN
21194   
21195         vuint32_t BUF3I:1;               /* Buffer MB Interrupt 3 Bit */
21196   
21197   #else
21198   
21199         vuint32_t BUF03I:1;              /* deprecated name - please avoid */
21200   
21201   #endif
21202   
21203   #ifndef USE_FIELD_ALIASES_FLEXCAN
21204   
21205         vuint32_t BUF2I:1;               /* Buffer MB Interrupt 2 Bit */
21206   
21207   #else
21208   
21209         vuint32_t BUF02I:1;              /* deprecated name - please avoid */
21210   
21211   #endif
21212   
21213   #ifndef USE_FIELD_ALIASES_FLEXCAN
21214   
21215         vuint32_t BUF1I:1;               /* Buffer MB Interrupt 1 Bit */
21216   
21217   #else
21218   
21219         vuint32_t BUF01I:1;              /* deprecated name - please avoid */
21220   
21221   #endif
21222   
21223   #ifndef USE_FIELD_ALIASES_FLEXCAN
21224   
21225         vuint32_t BUF0I:1;               /* Buffer MB Interrupt 0 Bit */
21226   
21227   #else
21228   
21229         vuint32_t BUF00I:1;              /* deprecated name - please avoid */
21230   
21231   #endif
21232   
21233       } B;
21234     } FLEXCAN_IFLAG1_32B_tag;
21235   
21236     /* Register layout for all registers MSG_CS ... */
21237     typedef union {                      /* Message Buffer Control and Status */
21238       vuint32_t R;
21239       struct {
21240        vuint32_t:
21241         4;
21242         vuint32_t CODE:4;                /* Message Buffer Code */
21243        vuint32_t:
21244         1;
21245         vuint32_t SRR:1;                 /* Substitute Remote Request */
21246         vuint32_t IDE:1;                 /* ID Extended Bit */
21247         vuint32_t RTR:1;                 /* Remote Transmission Request */
21248         vuint32_t LENGTH:4;              /* Length of Data in Bytes */
21249         vuint32_t TIMESTAMP:16;          /* Free-Running Counter Time Stamp */
21250       } B;
21251     } FLEXCAN_MSG_CS_32B_tag;
21252   
21253     /* Register layout for all registers MSG_ID ... */
21254     typedef union {                      /* Message Buffer Identifier Field */
21255       vuint32_t R;
21256       struct {
21257         vuint32_t PRIO:3;                /* Local Priority */
21258   
21259   #if 0
21260   
21261         /* MJR Edited */
21262         vuint32_t ID:29;                 /* Frame Identifier */
21263   
21264   #else
21265   
21266         vuint32_t STD_ID:11;
21267         vuint32_t EXT_ID:18;
21268   
21269   #endif
21270   
21271       } B;
21272     } FLEXCAN_MSG_ID_32B_tag;
21273   
21274     /* Register layout for all registers MSG_BYTE0_3 ... */
21275     typedef union {                      /* Message Buffer Data Register */
21276       vuint32_t R;
21277       vuint8_t BYTE[4];                  /* individual bytes can be accessed */
21278       vuint32_t WORD;                    /* individual words can be accessed */
21279     } FLEXCAN_MSG_DATA_32B_tag;
21280   
21281     /* Register layout for all registers MSG_BYTE4_7 matches MSG_DATA */
21282   #if 1
21283   
21284     /* MJR Edited */
21285     typedef union {
21286       vuint8_t B[8];                     /* Data buffer in Bytes (8 bits) */
21287       vuint16_t H[4];                    /* Data buffer in Half-words (16 bits) */
21288       vuint32_t W[2];                    /* Data buffer in words (32 bits) */
21289       vuint32_t R[2];                    /* Data buffer in words (32 bits) */
21290     } FLEXCAN_MSG_DATA2_32B_tag;
21291   
21292   #endif
21293   
21294     /* Register layout for all registers RXIMR ... */
21295     typedef union {                      /* FLEXCAN_RXIMR0 - FLEXCAN_RXIMR63 - RX Individual Mask Registers */
21296       vuint32_t R;
21297   
21298   #ifdef USE_FIELD_ALIASES_FLEXCAN
21299   
21300       struct {
21301         vuint32_t MI:32;                 /* deprecated field -- do not use */
21302       } B;
21303   
21304   #endif
21305   
21306     } FLEXCAN_RXIMR_32B_tag;
21307   
21308     typedef struct FLEXCAN_MB_struct_tag {
21309       union {
21310         /* Message Buffer Control and Status */
21311         FLEXCAN_MSG_CS_32B_tag MSG_CS;   /* relative offset: 0x0000 */
21312         FLEXCAN_MSG_CS_32B_tag CS;       /* deprecated - please avoid */
21313       };
21314   
21315       union {
21316         /* Message Buffer Identifier Field */
21317         FLEXCAN_MSG_ID_32B_tag MSG_ID;   /* relative offset: 0x0004 */
21318         FLEXCAN_MSG_ID_32B_tag ID;       /* deprecated - please avoid */
21319       };
21320   
21321       union {
21322   
21323   #if 0
21324   
21325         /* MJR Edited */
21326         FLEXCAN_W_32B_tag W[2];          /* relative offset: 0x0008 */
21327         FLEXCAN_H_16B_tag H[4];          /* relative offset: 0x0008 */
21328         FLEXCAN_B_8B_tag B[8];           /* relative offset: 0x0008 */
21329   
21330   #else
21331   
21332         FLEXCAN_MSG_DATA2_32B_tag DATA;  /* relative offset: 0x0008 */
21333   
21334   #endif
21335   
21336         struct {
21337           /* Message Buffer Data Register */
21338           FLEXCAN_MSG_DATA_32B_tag BYTE0_3;/* relative offset: 0x0008 */
21339           FLEXCAN_MSG_DATA_32B_tag BYTE4_7;/* relative offset: 0x000C */
21340         } MSG_DATA;
21341       };
21342     } FLEXCAN_MB_tag;
21343   
21344     typedef struct FLEXCAN_struct_tag {
21345       /* MCR - Module Configuration Register */
21346       FLEXCAN_MCR_32B_tag MCR;           /* offset: 0x0000 size: 32 bit */
21347       union {
21348         /* CTRL -  Control Register */
21349         FLEXCAN_CTRL_32B_tag CTRL;       /* offset: 0x0004 size: 32 bit */
21350         FLEXCAN_CTRL_32B_tag CR;         /* deprecated - please avoid */
21351       };
21352   
21353       /* TIMER - Free Running Timer */
21354       FLEXCAN_TIMER_32B_tag TIMER;       /* offset: 0x0008 size: 32 bit */
21355       int8_t FLEXCAN_reserved_000C[4];
21356   
21357       /* RXGMASK - Rx Global Mask Register */
21358       FLEXCAN_RXGMASK_32B_tag RXGMASK;   /* offset: 0x0010 size: 32 bit */
21359   
21360       /* RX14MASK - Rx 14 Mask Register */
21361       FLEXCAN_RX14MASK_32B_tag RX14MASK; /* offset: 0x0014 size: 32 bit */
21362   
21363       /* RX15MASK - Rx 15 Mask Register */
21364       FLEXCAN_RX15MASK_32B_tag RX15MASK; /* offset: 0x0018 size: 32 bit */
21365   
21366       /* ECR - Error Counter Register */
21367       FLEXCAN_ECR_32B_tag ECR;           /* offset: 0x001C size: 32 bit */
21368   
21369       /* ESR - Error and Status Register */
21370       FLEXCAN_ESR_32B_tag ESR;           /* offset: 0x0020 size: 32 bit */
21371       union {
21372         /* IMASK2 - Interrupt Masks 2 Register */
21373         FLEXCAN_IMASK2_32B_tag IMASK2;   /* offset: 0x0024 size: 32 bit */
21374         FLEXCAN_IMASK2_32B_tag IMRH;     /* deprecated - please avoid */
21375       };
21376   
21377       union {
21378         /* IMASK1 - Interrupt Masks 1 Register */
21379         FLEXCAN_IMASK1_32B_tag IMASK1;   /* offset: 0x0028 size: 32 bit */
21380         FLEXCAN_IMASK1_32B_tag IMRL;     /* deprecated - please avoid */
21381       };
21382   
21383       union {
21384         /* IFLAG2 - Interrupt Flags 2 Register */
21385         FLEXCAN_IFLAG2_32B_tag IFLAG2;   /* offset: 0x002C size: 32 bit */
21386         FLEXCAN_IFLAG2_32B_tag IFRH;     /* deprecated - please avoid */
21387       };
21388   
21389       union {
21390         /* IFLAG1 - Interrupt Flags 1 Register */
21391         FLEXCAN_IFLAG1_32B_tag IFLAG1;   /* offset: 0x0030 size: 32 bit */
21392         FLEXCAN_IFLAG1_32B_tag IFRL;     /* deprecated - please avoid */
21393       };
21394   
21395       int8_t FLEXCAN_reserved_0034[76];
21396       union {
21397         /*  Register set MB */
21398         FLEXCAN_MB_tag MB[64];           /* offset: 0x0080  (0x0010 x 64) */
21399   
21400         /*  Alias name for MB */
21401         FLEXCAN_MB_tag BUF[64];          /* deprecated - please avoid */
21402         struct {
21403           /* Message Buffer Control and Status */
21404           FLEXCAN_MSG_CS_32B_tag MSG0_CS;/* offset: 0x0080 size: 32 bit */
21405   
21406           /* Message Buffer Identifier Field */
21407           FLEXCAN_MSG_ID_32B_tag MSG0_ID;/* offset: 0x0084 size: 32 bit */
21408   
21409           /* Message Buffer Data Register */
21410           FLEXCAN_MSG_DATA_32B_tag MSG0_BYTE0_3;/* offset: 0x0088 size: 32 bit */
21411   
21412           /* Message Buffer Data Register */
21413           FLEXCAN_MSG_DATA_32B_tag MSG0_BYTE4_7;/* offset: 0x008C size: 32 bit */
21414   
21415           /* Message Buffer Control and Status */
21416           FLEXCAN_MSG_CS_32B_tag MSG1_CS;/* offset: 0x0090 size: 32 bit */
21417   
21418           /* Message Buffer Identifier Field */
21419           FLEXCAN_MSG_ID_32B_tag MSG1_ID;/* offset: 0x0094 size: 32 bit */
21420   
21421           /* Message Buffer Data Register */
21422           FLEXCAN_MSG_DATA_32B_tag MSG1_BYTE0_3;/* offset: 0x0098 size: 32 bit */
21423   
21424           /* Message Buffer Data Register */
21425           FLEXCAN_MSG_DATA_32B_tag MSG1_BYTE4_7;/* offset: 0x009C size: 32 bit */
21426   
21427           /* Message Buffer Control and Status */
21428           FLEXCAN_MSG_CS_32B_tag MSG2_CS;/* offset: 0x00A0 size: 32 bit */
21429   
21430           /* Message Buffer Identifier Field */
21431           FLEXCAN_MSG_ID_32B_tag MSG2_ID;/* offset: 0x00A4 size: 32 bit */
21432   
21433           /* Message Buffer Data Register */
21434           FLEXCAN_MSG_DATA_32B_tag MSG2_BYTE0_3;/* offset: 0x00A8 size: 32 bit */
21435   
21436           /* Message Buffer Data Register */
21437           FLEXCAN_MSG_DATA_32B_tag MSG2_BYTE4_7;/* offset: 0x00AC size: 32 bit */
21438   
21439           /* Message Buffer Control and Status */
21440           FLEXCAN_MSG_CS_32B_tag MSG3_CS;/* offset: 0x00B0 size: 32 bit */
21441   
21442           /* Message Buffer Identifier Field */
21443           FLEXCAN_MSG_ID_32B_tag MSG3_ID;/* offset: 0x00B4 size: 32 bit */
21444   
21445           /* Message Buffer Data Register */
21446           FLEXCAN_MSG_DATA_32B_tag MSG3_BYTE0_3;/* offset: 0x00B8 size: 32 bit */
21447   
21448           /* Message Buffer Data Register */
21449           FLEXCAN_MSG_DATA_32B_tag MSG3_BYTE4_7;/* offset: 0x00BC size: 32 bit */
21450   
21451           /* Message Buffer Control and Status */
21452           FLEXCAN_MSG_CS_32B_tag MSG4_CS;/* offset: 0x00C0 size: 32 bit */
21453   
21454           /* Message Buffer Identifier Field */
21455           FLEXCAN_MSG_ID_32B_tag MSG4_ID;/* offset: 0x00C4 size: 32 bit */
21456   
21457           /* Message Buffer Data Register */
21458           FLEXCAN_MSG_DATA_32B_tag MSG4_BYTE0_3;/* offset: 0x00C8 size: 32 bit */
21459   
21460           /* Message Buffer Data Register */
21461           FLEXCAN_MSG_DATA_32B_tag MSG4_BYTE4_7;/* offset: 0x00CC size: 32 bit */
21462   
21463           /* Message Buffer Control and Status */
21464           FLEXCAN_MSG_CS_32B_tag MSG5_CS;/* offset: 0x00D0 size: 32 bit */
21465   
21466           /* Message Buffer Identifier Field */
21467           FLEXCAN_MSG_ID_32B_tag MSG5_ID;/* offset: 0x00D4 size: 32 bit */
21468   
21469           /* Message Buffer Data Register */
21470           FLEXCAN_MSG_DATA_32B_tag MSG5_BYTE0_3;/* offset: 0x00D8 size: 32 bit */
21471   
21472           /* Message Buffer Data Register */
21473           FLEXCAN_MSG_DATA_32B_tag MSG5_BYTE4_7;/* offset: 0x00DC size: 32 bit */
21474   
21475           /* Message Buffer Control and Status */
21476           FLEXCAN_MSG_CS_32B_tag MSG6_CS;/* offset: 0x00E0 size: 32 bit */
21477   
21478           /* Message Buffer Identifier Field */
21479           FLEXCAN_MSG_ID_32B_tag MSG6_ID;/* offset: 0x00E4 size: 32 bit */
21480   
21481           /* Message Buffer Data Register */
21482           FLEXCAN_MSG_DATA_32B_tag MSG6_BYTE0_3;/* offset: 0x00E8 size: 32 bit */
21483   
21484           /* Message Buffer Data Register */
21485           FLEXCAN_MSG_DATA_32B_tag MSG6_BYTE4_7;/* offset: 0x00EC size: 32 bit */
21486   
21487           /* Message Buffer Control and Status */
21488           FLEXCAN_MSG_CS_32B_tag MSG7_CS;/* offset: 0x00F0 size: 32 bit */
21489   
21490           /* Message Buffer Identifier Field */
21491           FLEXCAN_MSG_ID_32B_tag MSG7_ID;/* offset: 0x00F4 size: 32 bit */
21492   
21493           /* Message Buffer Data Register */
21494           FLEXCAN_MSG_DATA_32B_tag MSG7_BYTE0_3;/* offset: 0x00F8 size: 32 bit */
21495   
21496           /* Message Buffer Data Register */
21497           FLEXCAN_MSG_DATA_32B_tag MSG7_BYTE4_7;/* offset: 0x00FC size: 32 bit */
21498   
21499           /* Message Buffer Control and Status */
21500           FLEXCAN_MSG_CS_32B_tag MSG8_CS;/* offset: 0x0100 size: 32 bit */
21501   
21502           /* Message Buffer Identifier Field */
21503           FLEXCAN_MSG_ID_32B_tag MSG8_ID;/* offset: 0x0104 size: 32 bit */
21504   
21505           /* Message Buffer Data Register */
21506           FLEXCAN_MSG_DATA_32B_tag MSG8_BYTE0_3;/* offset: 0x0108 size: 32 bit */
21507   
21508           /* Message Buffer Data Register */
21509           FLEXCAN_MSG_DATA_32B_tag MSG8_BYTE4_7;/* offset: 0x010C size: 32 bit */
21510   
21511           /* Message Buffer Control and Status */
21512           FLEXCAN_MSG_CS_32B_tag MSG9_CS;/* offset: 0x0110 size: 32 bit */
21513   
21514           /* Message Buffer Identifier Field */
21515           FLEXCAN_MSG_ID_32B_tag MSG9_ID;/* offset: 0x0114 size: 32 bit */
21516   
21517           /* Message Buffer Data Register */
21518           FLEXCAN_MSG_DATA_32B_tag MSG9_BYTE0_3;/* offset: 0x0118 size: 32 bit */
21519   
21520           /* Message Buffer Data Register */
21521           FLEXCAN_MSG_DATA_32B_tag MSG9_BYTE4_7;/* offset: 0x011C size: 32 bit */
21522   
21523           /* Message Buffer Control and Status */
21524           FLEXCAN_MSG_CS_32B_tag MSG10_CS;/* offset: 0x0120 size: 32 bit */
21525   
21526           /* Message Buffer Identifier Field */
21527           FLEXCAN_MSG_ID_32B_tag MSG10_ID;/* offset: 0x0124 size: 32 bit */
21528   
21529           /* Message Buffer Data Register */
21530           FLEXCAN_MSG_DATA_32B_tag MSG10_BYTE0_3;/* offset: 0x0128 size: 32 bit */
21531   
21532           /* Message Buffer Data Register */
21533           FLEXCAN_MSG_DATA_32B_tag MSG10_BYTE4_7;/* offset: 0x012C size: 32 bit */
21534   
21535           /* Message Buffer Control and Status */
21536           FLEXCAN_MSG_CS_32B_tag MSG11_CS;/* offset: 0x0130 size: 32 bit */
21537   
21538           /* Message Buffer Identifier Field */
21539           FLEXCAN_MSG_ID_32B_tag MSG11_ID;/* offset: 0x0134 size: 32 bit */
21540   
21541           /* Message Buffer Data Register */
21542           FLEXCAN_MSG_DATA_32B_tag MSG11_BYTE0_3;/* offset: 0x0138 size: 32 bit */
21543   
21544           /* Message Buffer Data Register */
21545           FLEXCAN_MSG_DATA_32B_tag MSG11_BYTE4_7;/* offset: 0x013C size: 32 bit */
21546   
21547           /* Message Buffer Control and Status */
21548           FLEXCAN_MSG_CS_32B_tag MSG12_CS;/* offset: 0x0140 size: 32 bit */
21549   
21550           /* Message Buffer Identifier Field */
21551           FLEXCAN_MSG_ID_32B_tag MSG12_ID;/* offset: 0x0144 size: 32 bit */
21552   
21553           /* Message Buffer Data Register */
21554           FLEXCAN_MSG_DATA_32B_tag MSG12_BYTE0_3;/* offset: 0x0148 size: 32 bit */
21555   
21556           /* Message Buffer Data Register */
21557           FLEXCAN_MSG_DATA_32B_tag MSG12_BYTE4_7;/* offset: 0x014C size: 32 bit */
21558   
21559           /* Message Buffer Control and Status */
21560           FLEXCAN_MSG_CS_32B_tag MSG13_CS;/* offset: 0x0150 size: 32 bit */
21561   
21562           /* Message Buffer Identifier Field */
21563           FLEXCAN_MSG_ID_32B_tag MSG13_ID;/* offset: 0x0154 size: 32 bit */
21564   
21565           /* Message Buffer Data Register */
21566           FLEXCAN_MSG_DATA_32B_tag MSG13_BYTE0_3;/* offset: 0x0158 size: 32 bit */
21567   
21568           /* Message Buffer Data Register */
21569           FLEXCAN_MSG_DATA_32B_tag MSG13_BYTE4_7;/* offset: 0x015C size: 32 bit */
21570   
21571           /* Message Buffer Control and Status */
21572           FLEXCAN_MSG_CS_32B_tag MSG14_CS;/* offset: 0x0160 size: 32 bit */
21573   
21574           /* Message Buffer Identifier Field */
21575           FLEXCAN_MSG_ID_32B_tag MSG14_ID;/* offset: 0x0164 size: 32 bit */
21576   
21577           /* Message Buffer Data Register */
21578           FLEXCAN_MSG_DATA_32B_tag MSG14_BYTE0_3;/* offset: 0x0168 size: 32 bit */
21579   
21580           /* Message Buffer Data Register */
21581           FLEXCAN_MSG_DATA_32B_tag MSG14_BYTE4_7;/* offset: 0x016C size: 32 bit */
21582   
21583           /* Message Buffer Control and Status */
21584           FLEXCAN_MSG_CS_32B_tag MSG15_CS;/* offset: 0x0170 size: 32 bit */
21585   
21586           /* Message Buffer Identifier Field */
21587           FLEXCAN_MSG_ID_32B_tag MSG15_ID;/* offset: 0x0174 size: 32 bit */
21588   
21589           /* Message Buffer Data Register */
21590           FLEXCAN_MSG_DATA_32B_tag MSG15_BYTE0_3;/* offset: 0x0178 size: 32 bit */
21591   
21592           /* Message Buffer Data Register */
21593           FLEXCAN_MSG_DATA_32B_tag MSG15_BYTE4_7;/* offset: 0x017C size: 32 bit */
21594   
21595           /* Message Buffer Control and Status */
21596           FLEXCAN_MSG_CS_32B_tag MSG16_CS;/* offset: 0x0180 size: 32 bit */
21597   
21598           /* Message Buffer Identifier Field */
21599           FLEXCAN_MSG_ID_32B_tag MSG16_ID;/* offset: 0x0184 size: 32 bit */
21600   
21601           /* Message Buffer Data Register */
21602           FLEXCAN_MSG_DATA_32B_tag MSG16_BYTE0_3;/* offset: 0x0188 size: 32 bit */
21603   
21604           /* Message Buffer Data Register */
21605           FLEXCAN_MSG_DATA_32B_tag MSG16_BYTE4_7;/* offset: 0x018C size: 32 bit */
21606   
21607           /* Message Buffer Control and Status */
21608           FLEXCAN_MSG_CS_32B_tag MSG17_CS;/* offset: 0x0190 size: 32 bit */
21609   
21610           /* Message Buffer Identifier Field */
21611           FLEXCAN_MSG_ID_32B_tag MSG17_ID;/* offset: 0x0194 size: 32 bit */
21612   
21613           /* Message Buffer Data Register */
21614           FLEXCAN_MSG_DATA_32B_tag MSG17_BYTE0_3;/* offset: 0x0198 size: 32 bit */
21615   
21616           /* Message Buffer Data Register */
21617           FLEXCAN_MSG_DATA_32B_tag MSG17_BYTE4_7;/* offset: 0x019C size: 32 bit */
21618   
21619           /* Message Buffer Control and Status */
21620           FLEXCAN_MSG_CS_32B_tag MSG18_CS;/* offset: 0x01A0 size: 32 bit */
21621   
21622           /* Message Buffer Identifier Field */
21623           FLEXCAN_MSG_ID_32B_tag MSG18_ID;/* offset: 0x01A4 size: 32 bit */
21624   
21625           /* Message Buffer Data Register */
21626           FLEXCAN_MSG_DATA_32B_tag MSG18_BYTE0_3;/* offset: 0x01A8 size: 32 bit */
21627   
21628           /* Message Buffer Data Register */
21629           FLEXCAN_MSG_DATA_32B_tag MSG18_BYTE4_7;/* offset: 0x01AC size: 32 bit */
21630   
21631           /* Message Buffer Control and Status */
21632           FLEXCAN_MSG_CS_32B_tag MSG19_CS;/* offset: 0x01B0 size: 32 bit */
21633   
21634           /* Message Buffer Identifier Field */
21635           FLEXCAN_MSG_ID_32B_tag MSG19_ID;/* offset: 0x01B4 size: 32 bit */
21636   
21637           /* Message Buffer Data Register */
21638           FLEXCAN_MSG_DATA_32B_tag MSG19_BYTE0_3;/* offset: 0x01B8 size: 32 bit */
21639   
21640           /* Message Buffer Data Register */
21641           FLEXCAN_MSG_DATA_32B_tag MSG19_BYTE4_7;/* offset: 0x01BC size: 32 bit */
21642   
21643           /* Message Buffer Control and Status */
21644           FLEXCAN_MSG_CS_32B_tag MSG20_CS;/* offset: 0x01C0 size: 32 bit */
21645   
21646           /* Message Buffer Identifier Field */
21647           FLEXCAN_MSG_ID_32B_tag MSG20_ID;/* offset: 0x01C4 size: 32 bit */
21648   
21649           /* Message Buffer Data Register */
21650           FLEXCAN_MSG_DATA_32B_tag MSG20_BYTE0_3;/* offset: 0x01C8 size: 32 bit */
21651   
21652           /* Message Buffer Data Register */
21653           FLEXCAN_MSG_DATA_32B_tag MSG20_BYTE4_7;/* offset: 0x01CC size: 32 bit */
21654   
21655           /* Message Buffer Control and Status */
21656           FLEXCAN_MSG_CS_32B_tag MSG21_CS;/* offset: 0x01D0 size: 32 bit */
21657   
21658           /* Message Buffer Identifier Field */
21659           FLEXCAN_MSG_ID_32B_tag MSG21_ID;/* offset: 0x01D4 size: 32 bit */
21660   
21661           /* Message Buffer Data Register */
21662           FLEXCAN_MSG_DATA_32B_tag MSG21_BYTE0_3;/* offset: 0x01D8 size: 32 bit */
21663   
21664           /* Message Buffer Data Register */
21665           FLEXCAN_MSG_DATA_32B_tag MSG21_BYTE4_7;/* offset: 0x01DC size: 32 bit */
21666   
21667           /* Message Buffer Control and Status */
21668           FLEXCAN_MSG_CS_32B_tag MSG22_CS;/* offset: 0x01E0 size: 32 bit */
21669   
21670           /* Message Buffer Identifier Field */
21671           FLEXCAN_MSG_ID_32B_tag MSG22_ID;/* offset: 0x01E4 size: 32 bit */
21672   
21673           /* Message Buffer Data Register */
21674           FLEXCAN_MSG_DATA_32B_tag MSG22_BYTE0_3;/* offset: 0x01E8 size: 32 bit */
21675   
21676           /* Message Buffer Data Register */
21677           FLEXCAN_MSG_DATA_32B_tag MSG22_BYTE4_7;/* offset: 0x01EC size: 32 bit */
21678   
21679           /* Message Buffer Control and Status */
21680           FLEXCAN_MSG_CS_32B_tag MSG23_CS;/* offset: 0x01F0 size: 32 bit */
21681   
21682           /* Message Buffer Identifier Field */
21683           FLEXCAN_MSG_ID_32B_tag MSG23_ID;/* offset: 0x01F4 size: 32 bit */
21684   
21685           /* Message Buffer Data Register */
21686           FLEXCAN_MSG_DATA_32B_tag MSG23_BYTE0_3;/* offset: 0x01F8 size: 32 bit */
21687   
21688           /* Message Buffer Data Register */
21689           FLEXCAN_MSG_DATA_32B_tag MSG23_BYTE4_7;/* offset: 0x01FC size: 32 bit */
21690   
21691           /* Message Buffer Control and Status */
21692           FLEXCAN_MSG_CS_32B_tag MSG24_CS;/* offset: 0x0200 size: 32 bit */
21693   
21694           /* Message Buffer Identifier Field */
21695           FLEXCAN_MSG_ID_32B_tag MSG24_ID;/* offset: 0x0204 size: 32 bit */
21696   
21697           /* Message Buffer Data Register */
21698           FLEXCAN_MSG_DATA_32B_tag MSG24_BYTE0_3;/* offset: 0x0208 size: 32 bit */
21699   
21700           /* Message Buffer Data Register */
21701           FLEXCAN_MSG_DATA_32B_tag MSG24_BYTE4_7;/* offset: 0x020C size: 32 bit */
21702   
21703           /* Message Buffer Control and Status */
21704           FLEXCAN_MSG_CS_32B_tag MSG25_CS;/* offset: 0x0210 size: 32 bit */
21705   
21706           /* Message Buffer Identifier Field */
21707           FLEXCAN_MSG_ID_32B_tag MSG25_ID;/* offset: 0x0214 size: 32 bit */
21708   
21709           /* Message Buffer Data Register */
21710           FLEXCAN_MSG_DATA_32B_tag MSG25_BYTE0_3;/* offset: 0x0218 size: 32 bit */
21711   
21712           /* Message Buffer Data Register */
21713           FLEXCAN_MSG_DATA_32B_tag MSG25_BYTE4_7;/* offset: 0x021C size: 32 bit */
21714   
21715           /* Message Buffer Control and Status */
21716           FLEXCAN_MSG_CS_32B_tag MSG26_CS;/* offset: 0x0220 size: 32 bit */
21717   
21718           /* Message Buffer Identifier Field */
21719           FLEXCAN_MSG_ID_32B_tag MSG26_ID;/* offset: 0x0224 size: 32 bit */
21720   
21721           /* Message Buffer Data Register */
21722           FLEXCAN_MSG_DATA_32B_tag MSG26_BYTE0_3;/* offset: 0x0228 size: 32 bit */
21723   
21724           /* Message Buffer Data Register */
21725           FLEXCAN_MSG_DATA_32B_tag MSG26_BYTE4_7;/* offset: 0x022C size: 32 bit */
21726   
21727           /* Message Buffer Control and Status */
21728           FLEXCAN_MSG_CS_32B_tag MSG27_CS;/* offset: 0x0230 size: 32 bit */
21729   
21730           /* Message Buffer Identifier Field */
21731           FLEXCAN_MSG_ID_32B_tag MSG27_ID;/* offset: 0x0234 size: 32 bit */
21732   
21733           /* Message Buffer Data Register */
21734           FLEXCAN_MSG_DATA_32B_tag MSG27_BYTE0_3;/* offset: 0x0238 size: 32 bit */
21735   
21736           /* Message Buffer Data Register */
21737           FLEXCAN_MSG_DATA_32B_tag MSG27_BYTE4_7;/* offset: 0x023C size: 32 bit */
21738   
21739           /* Message Buffer Control and Status */
21740           FLEXCAN_MSG_CS_32B_tag MSG28_CS;/* offset: 0x0240 size: 32 bit */
21741   
21742           /* Message Buffer Identifier Field */
21743           FLEXCAN_MSG_ID_32B_tag MSG28_ID;/* offset: 0x0244 size: 32 bit */
21744   
21745           /* Message Buffer Data Register */
21746           FLEXCAN_MSG_DATA_32B_tag MSG28_BYTE0_3;/* offset: 0x0248 size: 32 bit */
21747   
21748           /* Message Buffer Data Register */
21749           FLEXCAN_MSG_DATA_32B_tag MSG28_BYTE4_7;/* offset: 0x024C size: 32 bit */
21750   
21751           /* Message Buffer Control and Status */
21752           FLEXCAN_MSG_CS_32B_tag MSG29_CS;/* offset: 0x0250 size: 32 bit */
21753   
21754           /* Message Buffer Identifier Field */
21755           FLEXCAN_MSG_ID_32B_tag MSG29_ID;/* offset: 0x0254 size: 32 bit */
21756   
21757           /* Message Buffer Data Register */
21758           FLEXCAN_MSG_DATA_32B_tag MSG29_BYTE0_3;/* offset: 0x0258 size: 32 bit */
21759   
21760           /* Message Buffer Data Register */
21761           FLEXCAN_MSG_DATA_32B_tag MSG29_BYTE4_7;/* offset: 0x025C size: 32 bit */
21762   
21763           /* Message Buffer Control and Status */
21764           FLEXCAN_MSG_CS_32B_tag MSG30_CS;/* offset: 0x0260 size: 32 bit */
21765   
21766           /* Message Buffer Identifier Field */
21767           FLEXCAN_MSG_ID_32B_tag MSG30_ID;/* offset: 0x0264 size: 32 bit */
21768   
21769           /* Message Buffer Data Register */
21770           FLEXCAN_MSG_DATA_32B_tag MSG30_BYTE0_3;/* offset: 0x0268 size: 32 bit */
21771   
21772           /* Message Buffer Data Register */
21773           FLEXCAN_MSG_DATA_32B_tag MSG30_BYTE4_7;/* offset: 0x026C size: 32 bit */
21774   
21775           /* Message Buffer Control and Status */
21776           FLEXCAN_MSG_CS_32B_tag MSG31_CS;/* offset: 0x0270 size: 32 bit */
21777   
21778           /* Message Buffer Identifier Field */
21779           FLEXCAN_MSG_ID_32B_tag MSG31_ID;/* offset: 0x0274 size: 32 bit */
21780   
21781           /* Message Buffer Data Register */
21782           FLEXCAN_MSG_DATA_32B_tag MSG31_BYTE0_3;/* offset: 0x0278 size: 32 bit */
21783   
21784           /* Message Buffer Data Register */
21785           FLEXCAN_MSG_DATA_32B_tag MSG31_BYTE4_7;/* offset: 0x027C size: 32 bit */
21786   
21787           /* Message Buffer Control and Status */
21788           FLEXCAN_MSG_CS_32B_tag MSG32_CS;/* offset: 0x0280 size: 32 bit */
21789   
21790           /* Message Buffer Identifier Field */
21791           FLEXCAN_MSG_ID_32B_tag MSG32_ID;/* offset: 0x0284 size: 32 bit */
21792   
21793           /* Message Buffer Data Register */
21794           FLEXCAN_MSG_DATA_32B_tag MSG32_BYTE0_3;/* offset: 0x0288 size: 32 bit */
21795   
21796           /* Message Buffer Data Register */
21797           FLEXCAN_MSG_DATA_32B_tag MSG32_BYTE4_7;/* offset: 0x028C size: 32 bit */
21798   
21799           /* Message Buffer Control and Status */
21800           FLEXCAN_MSG_CS_32B_tag MSG33_CS;/* offset: 0x0290 size: 32 bit */
21801   
21802           /* Message Buffer Identifier Field */
21803           FLEXCAN_MSG_ID_32B_tag MSG33_ID;/* offset: 0x0294 size: 32 bit */
21804   
21805           /* Message Buffer Data Register */
21806           FLEXCAN_MSG_DATA_32B_tag MSG33_BYTE0_3;/* offset: 0x0298 size: 32 bit */
21807   
21808           /* Message Buffer Data Register */
21809           FLEXCAN_MSG_DATA_32B_tag MSG33_BYTE4_7;/* offset: 0x029C size: 32 bit */
21810   
21811           /* Message Buffer Control and Status */
21812           FLEXCAN_MSG_CS_32B_tag MSG34_CS;/* offset: 0x02A0 size: 32 bit */
21813   
21814           /* Message Buffer Identifier Field */
21815           FLEXCAN_MSG_ID_32B_tag MSG34_ID;/* offset: 0x02A4 size: 32 bit */
21816   
21817           /* Message Buffer Data Register */
21818           FLEXCAN_MSG_DATA_32B_tag MSG34_BYTE0_3;/* offset: 0x02A8 size: 32 bit */
21819   
21820           /* Message Buffer Data Register */
21821           FLEXCAN_MSG_DATA_32B_tag MSG34_BYTE4_7;/* offset: 0x02AC size: 32 bit */
21822   
21823           /* Message Buffer Control and Status */
21824           FLEXCAN_MSG_CS_32B_tag MSG35_CS;/* offset: 0x02B0 size: 32 bit */
21825   
21826           /* Message Buffer Identifier Field */
21827           FLEXCAN_MSG_ID_32B_tag MSG35_ID;/* offset: 0x02B4 size: 32 bit */
21828   
21829           /* Message Buffer Data Register */
21830           FLEXCAN_MSG_DATA_32B_tag MSG35_BYTE0_3;/* offset: 0x02B8 size: 32 bit */
21831   
21832           /* Message Buffer Data Register */
21833           FLEXCAN_MSG_DATA_32B_tag MSG35_BYTE4_7;/* offset: 0x02BC size: 32 bit */
21834   
21835           /* Message Buffer Control and Status */
21836           FLEXCAN_MSG_CS_32B_tag MSG36_CS;/* offset: 0x02C0 size: 32 bit */
21837   
21838           /* Message Buffer Identifier Field */
21839           FLEXCAN_MSG_ID_32B_tag MSG36_ID;/* offset: 0x02C4 size: 32 bit */
21840   
21841           /* Message Buffer Data Register */
21842           FLEXCAN_MSG_DATA_32B_tag MSG36_BYTE0_3;/* offset: 0x02C8 size: 32 bit */
21843   
21844           /* Message Buffer Data Register */
21845           FLEXCAN_MSG_DATA_32B_tag MSG36_BYTE4_7;/* offset: 0x02CC size: 32 bit */
21846   
21847           /* Message Buffer Control and Status */
21848           FLEXCAN_MSG_CS_32B_tag MSG37_CS;/* offset: 0x02D0 size: 32 bit */
21849   
21850           /* Message Buffer Identifier Field */
21851           FLEXCAN_MSG_ID_32B_tag MSG37_ID;/* offset: 0x02D4 size: 32 bit */
21852   
21853           /* Message Buffer Data Register */
21854           FLEXCAN_MSG_DATA_32B_tag MSG37_BYTE0_3;/* offset: 0x02D8 size: 32 bit */
21855   
21856           /* Message Buffer Data Register */
21857           FLEXCAN_MSG_DATA_32B_tag MSG37_BYTE4_7;/* offset: 0x02DC size: 32 bit */
21858   
21859           /* Message Buffer Control and Status */
21860           FLEXCAN_MSG_CS_32B_tag MSG38_CS;/* offset: 0x02E0 size: 32 bit */
21861   
21862           /* Message Buffer Identifier Field */
21863           FLEXCAN_MSG_ID_32B_tag MSG38_ID;/* offset: 0x02E4 size: 32 bit */
21864   
21865           /* Message Buffer Data Register */
21866           FLEXCAN_MSG_DATA_32B_tag MSG38_BYTE0_3;/* offset: 0x02E8 size: 32 bit */
21867   
21868           /* Message Buffer Data Register */
21869           FLEXCAN_MSG_DATA_32B_tag MSG38_BYTE4_7;/* offset: 0x02EC size: 32 bit */
21870   
21871           /* Message Buffer Control and Status */
21872           FLEXCAN_MSG_CS_32B_tag MSG39_CS;/* offset: 0x02F0 size: 32 bit */
21873   
21874           /* Message Buffer Identifier Field */
21875           FLEXCAN_MSG_ID_32B_tag MSG39_ID;/* offset: 0x02F4 size: 32 bit */
21876   
21877           /* Message Buffer Data Register */
21878           FLEXCAN_MSG_DATA_32B_tag MSG39_BYTE0_3;/* offset: 0x02F8 size: 32 bit */
21879   
21880           /* Message Buffer Data Register */
21881           FLEXCAN_MSG_DATA_32B_tag MSG39_BYTE4_7;/* offset: 0x02FC size: 32 bit */
21882   
21883           /* Message Buffer Control and Status */
21884           FLEXCAN_MSG_CS_32B_tag MSG40_CS;/* offset: 0x0300 size: 32 bit */
21885   
21886           /* Message Buffer Identifier Field */
21887           FLEXCAN_MSG_ID_32B_tag MSG40_ID;/* offset: 0x0304 size: 32 bit */
21888   
21889           /* Message Buffer Data Register */
21890           FLEXCAN_MSG_DATA_32B_tag MSG40_BYTE0_3;/* offset: 0x0308 size: 32 bit */
21891   
21892           /* Message Buffer Data Register */
21893           FLEXCAN_MSG_DATA_32B_tag MSG40_BYTE4_7;/* offset: 0x030C size: 32 bit */
21894   
21895           /* Message Buffer Control and Status */
21896           FLEXCAN_MSG_CS_32B_tag MSG41_CS;/* offset: 0x0310 size: 32 bit */
21897   
21898           /* Message Buffer Identifier Field */
21899           FLEXCAN_MSG_ID_32B_tag MSG41_ID;/* offset: 0x0314 size: 32 bit */
21900   
21901           /* Message Buffer Data Register */
21902           FLEXCAN_MSG_DATA_32B_tag MSG41_BYTE0_3;/* offset: 0x0318 size: 32 bit */
21903   
21904           /* Message Buffer Data Register */
21905           FLEXCAN_MSG_DATA_32B_tag MSG41_BYTE4_7;/* offset: 0x031C size: 32 bit */
21906   
21907           /* Message Buffer Control and Status */
21908           FLEXCAN_MSG_CS_32B_tag MSG42_CS;/* offset: 0x0320 size: 32 bit */
21909   
21910           /* Message Buffer Identifier Field */
21911           FLEXCAN_MSG_ID_32B_tag MSG42_ID;/* offset: 0x0324 size: 32 bit */
21912   
21913           /* Message Buffer Data Register */
21914           FLEXCAN_MSG_DATA_32B_tag MSG42_BYTE0_3;/* offset: 0x0328 size: 32 bit */
21915   
21916           /* Message Buffer Data Register */
21917           FLEXCAN_MSG_DATA_32B_tag MSG42_BYTE4_7;/* offset: 0x032C size: 32 bit */
21918   
21919           /* Message Buffer Control and Status */
21920           FLEXCAN_MSG_CS_32B_tag MSG43_CS;/* offset: 0x0330 size: 32 bit */
21921   
21922           /* Message Buffer Identifier Field */
21923           FLEXCAN_MSG_ID_32B_tag MSG43_ID;/* offset: 0x0334 size: 32 bit */
21924   
21925           /* Message Buffer Data Register */
21926           FLEXCAN_MSG_DATA_32B_tag MSG43_BYTE0_3;/* offset: 0x0338 size: 32 bit */
21927   
21928           /* Message Buffer Data Register */
21929           FLEXCAN_MSG_DATA_32B_tag MSG43_BYTE4_7;/* offset: 0x033C size: 32 bit */
21930   
21931           /* Message Buffer Control and Status */
21932           FLEXCAN_MSG_CS_32B_tag MSG44_CS;/* offset: 0x0340 size: 32 bit */
21933   
21934           /* Message Buffer Identifier Field */
21935           FLEXCAN_MSG_ID_32B_tag MSG44_ID;/* offset: 0x0344 size: 32 bit */
21936   
21937           /* Message Buffer Data Register */
21938           FLEXCAN_MSG_DATA_32B_tag MSG44_BYTE0_3;/* offset: 0x0348 size: 32 bit */
21939   
21940           /* Message Buffer Data Register */
21941           FLEXCAN_MSG_DATA_32B_tag MSG44_BYTE4_7;/* offset: 0x034C size: 32 bit */
21942   
21943           /* Message Buffer Control and Status */
21944           FLEXCAN_MSG_CS_32B_tag MSG45_CS;/* offset: 0x0350 size: 32 bit */
21945   
21946           /* Message Buffer Identifier Field */
21947           FLEXCAN_MSG_ID_32B_tag MSG45_ID;/* offset: 0x0354 size: 32 bit */
21948   
21949           /* Message Buffer Data Register */
21950           FLEXCAN_MSG_DATA_32B_tag MSG45_BYTE0_3;/* offset: 0x0358 size: 32 bit */
21951   
21952           /* Message Buffer Data Register */
21953           FLEXCAN_MSG_DATA_32B_tag MSG45_BYTE4_7;/* offset: 0x035C size: 32 bit */
21954   
21955           /* Message Buffer Control and Status */
21956           FLEXCAN_MSG_CS_32B_tag MSG46_CS;/* offset: 0x0360 size: 32 bit */
21957   
21958           /* Message Buffer Identifier Field */
21959           FLEXCAN_MSG_ID_32B_tag MSG46_ID;/* offset: 0x0364 size: 32 bit */
21960   
21961           /* Message Buffer Data Register */
21962           FLEXCAN_MSG_DATA_32B_tag MSG46_BYTE0_3;/* offset: 0x0368 size: 32 bit */
21963   
21964           /* Message Buffer Data Register */
21965           FLEXCAN_MSG_DATA_32B_tag MSG46_BYTE4_7;/* offset: 0x036C size: 32 bit */
21966   
21967           /* Message Buffer Control and Status */
21968           FLEXCAN_MSG_CS_32B_tag MSG47_CS;/* offset: 0x0370 size: 32 bit */
21969   
21970           /* Message Buffer Identifier Field */
21971           FLEXCAN_MSG_ID_32B_tag MSG47_ID;/* offset: 0x0374 size: 32 bit */
21972   
21973           /* Message Buffer Data Register */
21974           FLEXCAN_MSG_DATA_32B_tag MSG47_BYTE0_3;/* offset: 0x0378 size: 32 bit */
21975   
21976           /* Message Buffer Data Register */
21977           FLEXCAN_MSG_DATA_32B_tag MSG47_BYTE4_7;/* offset: 0x037C size: 32 bit */
21978   
21979           /* Message Buffer Control and Status */
21980           FLEXCAN_MSG_CS_32B_tag MSG48_CS;/* offset: 0x0380 size: 32 bit */
21981   
21982           /* Message Buffer Identifier Field */
21983           FLEXCAN_MSG_ID_32B_tag MSG48_ID;/* offset: 0x0384 size: 32 bit */
21984   
21985           /* Message Buffer Data Register */
21986           FLEXCAN_MSG_DATA_32B_tag MSG48_BYTE0_3;/* offset: 0x0388 size: 32 bit */
21987   
21988           /* Message Buffer Data Register */
21989           FLEXCAN_MSG_DATA_32B_tag MSG48_BYTE4_7;/* offset: 0x038C size: 32 bit */
21990   
21991           /* Message Buffer Control and Status */
21992           FLEXCAN_MSG_CS_32B_tag MSG49_CS;/* offset: 0x0390 size: 32 bit */
21993   
21994           /* Message Buffer Identifier Field */
21995           FLEXCAN_MSG_ID_32B_tag MSG49_ID;/* offset: 0x0394 size: 32 bit */
21996   
21997           /* Message Buffer Data Register */
21998           FLEXCAN_MSG_DATA_32B_tag MSG49_BYTE0_3;/* offset: 0x0398 size: 32 bit */
21999   
22000           /* Message Buffer Data Register */
22001           FLEXCAN_MSG_DATA_32B_tag MSG49_BYTE4_7;/* offset: 0x039C size: 32 bit */
22002   
22003           /* Message Buffer Control and Status */
22004           FLEXCAN_MSG_CS_32B_tag MSG50_CS;/* offset: 0x03A0 size: 32 bit */
22005   
22006           /* Message Buffer Identifier Field */
22007           FLEXCAN_MSG_ID_32B_tag MSG50_ID;/* offset: 0x03A4 size: 32 bit */
22008   
22009           /* Message Buffer Data Register */
22010           FLEXCAN_MSG_DATA_32B_tag MSG50_BYTE0_3;/* offset: 0x03A8 size: 32 bit */
22011   
22012           /* Message Buffer Data Register */
22013           FLEXCAN_MSG_DATA_32B_tag MSG50_BYTE4_7;/* offset: 0x03AC size: 32 bit */
22014   
22015           /* Message Buffer Control and Status */
22016           FLEXCAN_MSG_CS_32B_tag MSG51_CS;/* offset: 0x03B0 size: 32 bit */
22017   
22018           /* Message Buffer Identifier Field */
22019           FLEXCAN_MSG_ID_32B_tag MSG51_ID;/* offset: 0x03B4 size: 32 bit */
22020   
22021           /* Message Buffer Data Register */
22022           FLEXCAN_MSG_DATA_32B_tag MSG51_BYTE0_3;/* offset: 0x03B8 size: 32 bit */
22023   
22024           /* Message Buffer Data Register */
22025           FLEXCAN_MSG_DATA_32B_tag MSG51_BYTE4_7;/* offset: 0x03BC size: 32 bit */
22026   
22027           /* Message Buffer Control and Status */
22028           FLEXCAN_MSG_CS_32B_tag MSG52_CS;/* offset: 0x03C0 size: 32 bit */
22029   
22030           /* Message Buffer Identifier Field */
22031           FLEXCAN_MSG_ID_32B_tag MSG52_ID;/* offset: 0x03C4 size: 32 bit */
22032   
22033           /* Message Buffer Data Register */
22034           FLEXCAN_MSG_DATA_32B_tag MSG52_BYTE0_3;/* offset: 0x03C8 size: 32 bit */
22035   
22036           /* Message Buffer Data Register */
22037           FLEXCAN_MSG_DATA_32B_tag MSG52_BYTE4_7;/* offset: 0x03CC size: 32 bit */
22038   
22039           /* Message Buffer Control and Status */
22040           FLEXCAN_MSG_CS_32B_tag MSG53_CS;/* offset: 0x03D0 size: 32 bit */
22041   
22042           /* Message Buffer Identifier Field */
22043           FLEXCAN_MSG_ID_32B_tag MSG53_ID;/* offset: 0x03D4 size: 32 bit */
22044   
22045           /* Message Buffer Data Register */
22046           FLEXCAN_MSG_DATA_32B_tag MSG53_BYTE0_3;/* offset: 0x03D8 size: 32 bit */
22047   
22048           /* Message Buffer Data Register */
22049           FLEXCAN_MSG_DATA_32B_tag MSG53_BYTE4_7;/* offset: 0x03DC size: 32 bit */
22050   
22051           /* Message Buffer Control and Status */
22052           FLEXCAN_MSG_CS_32B_tag MSG54_CS;/* offset: 0x03E0 size: 32 bit */
22053   
22054           /* Message Buffer Identifier Field */
22055           FLEXCAN_MSG_ID_32B_tag MSG54_ID;/* offset: 0x03E4 size: 32 bit */
22056   
22057           /* Message Buffer Data Register */
22058           FLEXCAN_MSG_DATA_32B_tag MSG54_BYTE0_3;/* offset: 0x03E8 size: 32 bit */
22059   
22060           /* Message Buffer Data Register */
22061           FLEXCAN_MSG_DATA_32B_tag MSG54_BYTE4_7;/* offset: 0x03EC size: 32 bit */
22062   
22063           /* Message Buffer Control and Status */
22064           FLEXCAN_MSG_CS_32B_tag MSG55_CS;/* offset: 0x03F0 size: 32 bit */
22065   
22066           /* Message Buffer Identifier Field */
22067           FLEXCAN_MSG_ID_32B_tag MSG55_ID;/* offset: 0x03F4 size: 32 bit */
22068   
22069           /* Message Buffer Data Register */
22070           FLEXCAN_MSG_DATA_32B_tag MSG55_BYTE0_3;/* offset: 0x03F8 size: 32 bit */
22071   
22072           /* Message Buffer Data Register */
22073           FLEXCAN_MSG_DATA_32B_tag MSG55_BYTE4_7;/* offset: 0x03FC size: 32 bit */
22074   
22075           /* Message Buffer Control and Status */
22076           FLEXCAN_MSG_CS_32B_tag MSG56_CS;/* offset: 0x0400 size: 32 bit */
22077   
22078           /* Message Buffer Identifier Field */
22079           FLEXCAN_MSG_ID_32B_tag MSG56_ID;/* offset: 0x0404 size: 32 bit */
22080   
22081           /* Message Buffer Data Register */
22082           FLEXCAN_MSG_DATA_32B_tag MSG56_BYTE0_3;/* offset: 0x0408 size: 32 bit */
22083   
22084           /* Message Buffer Data Register */
22085           FLEXCAN_MSG_DATA_32B_tag MSG56_BYTE4_7;/* offset: 0x040C size: 32 bit */
22086   
22087           /* Message Buffer Control and Status */
22088           FLEXCAN_MSG_CS_32B_tag MSG57_CS;/* offset: 0x0410 size: 32 bit */
22089   
22090           /* Message Buffer Identifier Field */
22091           FLEXCAN_MSG_ID_32B_tag MSG57_ID;/* offset: 0x0414 size: 32 bit */
22092   
22093           /* Message Buffer Data Register */
22094           FLEXCAN_MSG_DATA_32B_tag MSG57_BYTE0_3;/* offset: 0x0418 size: 32 bit */
22095   
22096           /* Message Buffer Data Register */
22097           FLEXCAN_MSG_DATA_32B_tag MSG57_BYTE4_7;/* offset: 0x041C size: 32 bit */
22098   
22099           /* Message Buffer Control and Status */
22100           FLEXCAN_MSG_CS_32B_tag MSG58_CS;/* offset: 0x0420 size: 32 bit */
22101   
22102           /* Message Buffer Identifier Field */
22103           FLEXCAN_MSG_ID_32B_tag MSG58_ID;/* offset: 0x0424 size: 32 bit */
22104   
22105           /* Message Buffer Data Register */
22106           FLEXCAN_MSG_DATA_32B_tag MSG58_BYTE0_3;/* offset: 0x0428 size: 32 bit */
22107   
22108           /* Message Buffer Data Register */
22109           FLEXCAN_MSG_DATA_32B_tag MSG58_BYTE4_7;/* offset: 0x042C size: 32 bit */
22110   
22111           /* Message Buffer Control and Status */
22112           FLEXCAN_MSG_CS_32B_tag MSG59_CS;/* offset: 0x0430 size: 32 bit */
22113   
22114           /* Message Buffer Identifier Field */
22115           FLEXCAN_MSG_ID_32B_tag MSG59_ID;/* offset: 0x0434 size: 32 bit */
22116   
22117           /* Message Buffer Data Register */
22118           FLEXCAN_MSG_DATA_32B_tag MSG59_BYTE0_3;/* offset: 0x0438 size: 32 bit */
22119   
22120           /* Message Buffer Data Register */
22121           FLEXCAN_MSG_DATA_32B_tag MSG59_BYTE4_7;/* offset: 0x043C size: 32 bit */
22122   
22123           /* Message Buffer Control and Status */
22124           FLEXCAN_MSG_CS_32B_tag MSG60_CS;/* offset: 0x0440 size: 32 bit */
22125   
22126           /* Message Buffer Identifier Field */
22127           FLEXCAN_MSG_ID_32B_tag MSG60_ID;/* offset: 0x0444 size: 32 bit */
22128   
22129           /* Message Buffer Data Register */
22130           FLEXCAN_MSG_DATA_32B_tag MSG60_BYTE0_3;/* offset: 0x0448 size: 32 bit */
22131   
22132           /* Message Buffer Data Register */
22133           FLEXCAN_MSG_DATA_32B_tag MSG60_BYTE4_7;/* offset: 0x044C size: 32 bit */
22134   
22135           /* Message Buffer Control and Status */
22136           FLEXCAN_MSG_CS_32B_tag MSG61_CS;/* offset: 0x0450 size: 32 bit */
22137   
22138           /* Message Buffer Identifier Field */
22139           FLEXCAN_MSG_ID_32B_tag MSG61_ID;/* offset: 0x0454 size: 32 bit */
22140   
22141           /* Message Buffer Data Register */
22142           FLEXCAN_MSG_DATA_32B_tag MSG61_BYTE0_3;/* offset: 0x0458 size: 32 bit */
22143   
22144           /* Message Buffer Data Register */
22145           FLEXCAN_MSG_DATA_32B_tag MSG61_BYTE4_7;/* offset: 0x045C size: 32 bit */
22146   
22147           /* Message Buffer Control and Status */
22148           FLEXCAN_MSG_CS_32B_tag MSG62_CS;/* offset: 0x0460 size: 32 bit */
22149   
22150           /* Message Buffer Identifier Field */
22151           FLEXCAN_MSG_ID_32B_tag MSG62_ID;/* offset: 0x0464 size: 32 bit */
22152   
22153           /* Message Buffer Data Register */
22154           FLEXCAN_MSG_DATA_32B_tag MSG62_BYTE0_3;/* offset: 0x0468 size: 32 bit */
22155   
22156           /* Message Buffer Data Register */
22157           FLEXCAN_MSG_DATA_32B_tag MSG62_BYTE4_7;/* offset: 0x046C size: 32 bit */
22158   
22159           /* Message Buffer Control and Status */
22160           FLEXCAN_MSG_CS_32B_tag MSG63_CS;/* offset: 0x0470 size: 32 bit */
22161   
22162           /* Message Buffer Identifier Field */
22163           FLEXCAN_MSG_ID_32B_tag MSG63_ID;/* offset: 0x0474 size: 32 bit */
22164   
22165           /* Message Buffer Data Register */
22166           FLEXCAN_MSG_DATA_32B_tag MSG63_BYTE0_3;/* offset: 0x0478 size: 32 bit */
22167   
22168           /* Message Buffer Data Register */
22169           FLEXCAN_MSG_DATA_32B_tag MSG63_BYTE4_7;/* offset: 0x047C size: 32 bit */
22170         };
22171       };
22172   
22173       int8_t FLEXCAN_reserved_0480[1024];
22174       union {
22175         /* FLEXCAN_RXIMR0 - FLEXCAN_RXIMR63 - RX Individual Mask Registers */
22176         FLEXCAN_RXIMR_32B_tag RXIMR[64]; /* offset: 0x0880  (0x0004 x 64) */
22177         struct {
22178           /* FLEXCAN_RXIMR0 - FLEXCAN_RXIMR63 - RX Individual Mask Registers */
22179           FLEXCAN_RXIMR_32B_tag RXIMR0;  /* offset: 0x0880 size: 32 bit */
22180           FLEXCAN_RXIMR_32B_tag RXIMR1;  /* offset: 0x0884 size: 32 bit */
22181           FLEXCAN_RXIMR_32B_tag RXIMR2;  /* offset: 0x0888 size: 32 bit */
22182           FLEXCAN_RXIMR_32B_tag RXIMR3;  /* offset: 0x088C size: 32 bit */
22183           FLEXCAN_RXIMR_32B_tag RXIMR4;  /* offset: 0x0890 size: 32 bit */
22184           FLEXCAN_RXIMR_32B_tag RXIMR5;  /* offset: 0x0894 size: 32 bit */
22185           FLEXCAN_RXIMR_32B_tag RXIMR6;  /* offset: 0x0898 size: 32 bit */
22186           FLEXCAN_RXIMR_32B_tag RXIMR7;  /* offset: 0x089C size: 32 bit */
22187           FLEXCAN_RXIMR_32B_tag RXIMR8;  /* offset: 0x08A0 size: 32 bit */
22188           FLEXCAN_RXIMR_32B_tag RXIMR9;  /* offset: 0x08A4 size: 32 bit */
22189           FLEXCAN_RXIMR_32B_tag RXIMR10; /* offset: 0x08A8 size: 32 bit */
22190           FLEXCAN_RXIMR_32B_tag RXIMR11; /* offset: 0x08AC size: 32 bit */
22191           FLEXCAN_RXIMR_32B_tag RXIMR12; /* offset: 0x08B0 size: 32 bit */
22192           FLEXCAN_RXIMR_32B_tag RXIMR13; /* offset: 0x08B4 size: 32 bit */
22193           FLEXCAN_RXIMR_32B_tag RXIMR14; /* offset: 0x08B8 size: 32 bit */
22194           FLEXCAN_RXIMR_32B_tag RXIMR15; /* offset: 0x08BC size: 32 bit */
22195           FLEXCAN_RXIMR_32B_tag RXIMR16; /* offset: 0x08C0 size: 32 bit */
22196           FLEXCAN_RXIMR_32B_tag RXIMR17; /* offset: 0x08C4 size: 32 bit */
22197           FLEXCAN_RXIMR_32B_tag RXIMR18; /* offset: 0x08C8 size: 32 bit */
22198           FLEXCAN_RXIMR_32B_tag RXIMR19; /* offset: 0x08CC size: 32 bit */
22199           FLEXCAN_RXIMR_32B_tag RXIMR20; /* offset: 0x08D0 size: 32 bit */
22200           FLEXCAN_RXIMR_32B_tag RXIMR21; /* offset: 0x08D4 size: 32 bit */
22201           FLEXCAN_RXIMR_32B_tag RXIMR22; /* offset: 0x08D8 size: 32 bit */
22202           FLEXCAN_RXIMR_32B_tag RXIMR23; /* offset: 0x08DC size: 32 bit */
22203           FLEXCAN_RXIMR_32B_tag RXIMR24; /* offset: 0x08E0 size: 32 bit */
22204           FLEXCAN_RXIMR_32B_tag RXIMR25; /* offset: 0x08E4 size: 32 bit */
22205           FLEXCAN_RXIMR_32B_tag RXIMR26; /* offset: 0x08E8 size: 32 bit */
22206           FLEXCAN_RXIMR_32B_tag RXIMR27; /* offset: 0x08EC size: 32 bit */
22207           FLEXCAN_RXIMR_32B_tag RXIMR28; /* offset: 0x08F0 size: 32 bit */
22208           FLEXCAN_RXIMR_32B_tag RXIMR29; /* offset: 0x08F4 size: 32 bit */
22209           FLEXCAN_RXIMR_32B_tag RXIMR30; /* offset: 0x08F8 size: 32 bit */
22210           FLEXCAN_RXIMR_32B_tag RXIMR31; /* offset: 0x08FC size: 32 bit */
22211           FLEXCAN_RXIMR_32B_tag RXIMR32; /* offset: 0x0900 size: 32 bit */
22212           FLEXCAN_RXIMR_32B_tag RXIMR33; /* offset: 0x0904 size: 32 bit */
22213           FLEXCAN_RXIMR_32B_tag RXIMR34; /* offset: 0x0908 size: 32 bit */
22214           FLEXCAN_RXIMR_32B_tag RXIMR35; /* offset: 0x090C size: 32 bit */
22215           FLEXCAN_RXIMR_32B_tag RXIMR36; /* offset: 0x0910 size: 32 bit */
22216           FLEXCAN_RXIMR_32B_tag RXIMR37; /* offset: 0x0914 size: 32 bit */
22217           FLEXCAN_RXIMR_32B_tag RXIMR38; /* offset: 0x0918 size: 32 bit */
22218           FLEXCAN_RXIMR_32B_tag RXIMR39; /* offset: 0x091C size: 32 bit */
22219           FLEXCAN_RXIMR_32B_tag RXIMR40; /* offset: 0x0920 size: 32 bit */
22220           FLEXCAN_RXIMR_32B_tag RXIMR41; /* offset: 0x0924 size: 32 bit */
22221           FLEXCAN_RXIMR_32B_tag RXIMR42; /* offset: 0x0928 size: 32 bit */
22222           FLEXCAN_RXIMR_32B_tag RXIMR43; /* offset: 0x092C size: 32 bit */
22223           FLEXCAN_RXIMR_32B_tag RXIMR44; /* offset: 0x0930 size: 32 bit */
22224           FLEXCAN_RXIMR_32B_tag RXIMR45; /* offset: 0x0934 size: 32 bit */
22225           FLEXCAN_RXIMR_32B_tag RXIMR46; /* offset: 0x0938 size: 32 bit */
22226           FLEXCAN_RXIMR_32B_tag RXIMR47; /* offset: 0x093C size: 32 bit */
22227           FLEXCAN_RXIMR_32B_tag RXIMR48; /* offset: 0x0940 size: 32 bit */
22228           FLEXCAN_RXIMR_32B_tag RXIMR49; /* offset: 0x0944 size: 32 bit */
22229           FLEXCAN_RXIMR_32B_tag RXIMR50; /* offset: 0x0948 size: 32 bit */
22230           FLEXCAN_RXIMR_32B_tag RXIMR51; /* offset: 0x094C size: 32 bit */
22231           FLEXCAN_RXIMR_32B_tag RXIMR52; /* offset: 0x0950 size: 32 bit */
22232           FLEXCAN_RXIMR_32B_tag RXIMR53; /* offset: 0x0954 size: 32 bit */
22233           FLEXCAN_RXIMR_32B_tag RXIMR54; /* offset: 0x0958 size: 32 bit */
22234           FLEXCAN_RXIMR_32B_tag RXIMR55; /* offset: 0x095C size: 32 bit */
22235           FLEXCAN_RXIMR_32B_tag RXIMR56; /* offset: 0x0960 size: 32 bit */
22236           FLEXCAN_RXIMR_32B_tag RXIMR57; /* offset: 0x0964 size: 32 bit */
22237           FLEXCAN_RXIMR_32B_tag RXIMR58; /* offset: 0x0968 size: 32 bit */
22238           FLEXCAN_RXIMR_32B_tag RXIMR59; /* offset: 0x096C size: 32 bit */
22239           FLEXCAN_RXIMR_32B_tag RXIMR60; /* offset: 0x0970 size: 32 bit */
22240           FLEXCAN_RXIMR_32B_tag RXIMR61; /* offset: 0x0974 size: 32 bit */
22241           FLEXCAN_RXIMR_32B_tag RXIMR62; /* offset: 0x0978 size: 32 bit */
22242           FLEXCAN_RXIMR_32B_tag RXIMR63; /* offset: 0x097C size: 32 bit */
22243         };
22244       };
22245   
22246       int8_t FLEXCAN_reserved_0980[13952];
22247     } FLEXCAN_tag;
22248   
22249   #define FLEXCAN_A                      (*(volatile FLEXCAN_tag *) 0xFFFC0000UL)
22250   #define FLEXCAN_B                      (*(volatile FLEXCAN_tag *) 0xFFFC4000UL)
22251   
22252     /****************************************************************/
22253     /*                                                              */
22254     /* Module: DMA_CH_MUX  */
22255     /*                                                              */
22256     /****************************************************************/
22257   
22258     /* Register layout for all registers CHCONFIG ... */
22259     typedef union {                      /* CHCONFIG[0-15] - Channel Configuration Registers */
22260       vuint8_t R;
22261       struct {
22262         vuint8_t ENBL:1;                 /* DMA Channel Enable */
22263         vuint8_t TRIG:1;                 /* DMA Channel Trigger Enable */
22264         vuint8_t SOURCE:6;               /* DMA Channel Source */
22265       } B;
22266     } DMA_CH_MUX_CHCONFIG_8B_tag;
22267   
22268     typedef struct DMA_CH_MUX_struct_tag {
22269       union {
22270         /* CHCONFIG[0-15] - Channel Configuration Registers */
22271         DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG[16];/* offset: 0x0000  (0x0001 x 16) */
22272         struct {
22273           /* CHCONFIG[0-15] - Channel Configuration Registers */
22274           DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG0;/* offset: 0x0000 size: 8 bit */
22275           DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG1;/* offset: 0x0001 size: 8 bit */
22276           DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG2;/* offset: 0x0002 size: 8 bit */
22277           DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG3;/* offset: 0x0003 size: 8 bit */
22278           DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG4;/* offset: 0x0004 size: 8 bit */
22279           DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG5;/* offset: 0x0005 size: 8 bit */
22280           DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG6;/* offset: 0x0006 size: 8 bit */
22281           DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG7;/* offset: 0x0007 size: 8 bit */
22282           DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG8;/* offset: 0x0008 size: 8 bit */
22283           DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG9;/* offset: 0x0009 size: 8 bit */
22284           DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG10;/* offset: 0x000A size: 8 bit */
22285           DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG11;/* offset: 0x000B size: 8 bit */
22286           DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG12;/* offset: 0x000C size: 8 bit */
22287           DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG13;/* offset: 0x000D size: 8 bit */
22288           DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG14;/* offset: 0x000E size: 8 bit */
22289           DMA_CH_MUX_CHCONFIG_8B_tag CHCONFIG15;/* offset: 0x000F size: 8 bit */
22290         };
22291       };
22292   
22293       int8_t DMA_CH_MUX_reserved_0010[16368];
22294     } DMA_CH_MUX_tag;
22295   
22296   #define DMA_CH_MUX                     (*(volatile DMA_CH_MUX_tag *) 0xFFFDC000UL)
22297   
22298     /****************************************************************/
22299     /*                                                              */
22300     /* Module: FR  */
22301     /*                                                              */
22302     /****************************************************************/
22303     typedef union {                      /* Module Version Number */
22304       vuint16_t R;
22305       struct {
22306         vuint16_t CHIVER:8;              /* VERSION NUMBER OF CHI */
22307         vuint16_t PEVER:8;               /* VERSION NUMBER OF PE */
22308       } B;
22309     } FR_MVR_16B_tag;
22310   
22311     typedef union {                      /* Module Configuration Register */
22312       vuint16_t R;
22313       struct {
22314         vuint16_t MEN:1;                 /* Module Enable */
22315         vuint16_t SBFF:1;                /* System Bus Failure Freeze */
22316   
22317   #ifndef USE_FIELD_ALIASES_FR
22318   
22319         vuint16_t SCM:1;                 /* single channel device mode */
22320   
22321   #else
22322   
22323         vuint16_t SCMD:1;                /* deprecated name - please avoid */
22324   
22325   #endif
22326   
22327         vuint16_t CHB:1;                 /* Channel B enable */
22328         vuint16_t CHA:1;                 /* channel A enable */
22329         vuint16_t SFFE:1;                /* Sync. frame filter Enable */
22330         vuint16_t ECCE:1;                /* ECC Functionlity Enable */
22331         vuint16_t TMODER:1;              /* Functional Test mode */
22332         vuint16_t FUM:1;                 /* FIFO Update Mode */
22333         vuint16_t FAM:1;                 /* FIFO Address Mode */
22334        vuint16_t:
22335         1;
22336         vuint16_t CLKSEL:1;              /* Protocol Engine clock source select */
22337         vuint16_t BITRATE:3;             /* Bus bit rate */
22338        vuint16_t:
22339         1;
22340       } B;
22341     } FR_MCR_16B_tag;
22342   
22343     typedef union {                      /* SYSTEM MEMORY BASE ADD HIGH REG */
22344       vuint16_t R;
22345       struct {
22346         vuint16_t SMBA_31_16:16;         /* SYS_MEM_BASE_ADDR[31:16] */
22347       } B;
22348     } FR_SYMBADHR_16B_tag;
22349   
22350     typedef union {                      /* SYSTEM MEMORY BASE ADD LOW  REG */
22351       vuint16_t R;
22352       struct {
22353         vuint16_t SMBA_15_4:12;          /* SYS_MEM_BASE_ADDR[15:4] */
22354        vuint16_t:
22355         4;
22356       } B;
22357     } FR_SYMBADLR_16B_tag;
22358   
22359     typedef union {                      /* STROBE SIGNAL CONTROL REGISTER */
22360       vuint16_t R;
22361       struct {
22362         vuint16_t WMD:1;                 /* DEFINES WRITE MODE OF REG */
22363        vuint16_t:
22364         3;
22365         vuint16_t SEL:4;                 /* STROBE SIGNSL SELECT */
22366        vuint16_t:
22367         3;
22368         vuint16_t ENB:1;                 /* STROBE SIGNAL ENABLE */
22369        vuint16_t:
22370         2;
22371         vuint16_t STBPSEL:2;             /* STROBE PORT SELECT */
22372       } B;
22373     } FR_STBSCR_16B_tag;
22374   
22375     typedef union {                      /* MESSAGE BUFFER DATA SIZE REGISTER */
22376       vuint16_t R;
22377       struct {
22378        vuint16_t:
22379         1;
22380         vuint16_t MBSEG2DS:7;            /* MESSAGE BUFFER SEGMENT 2 DATA SIZE */
22381        vuint16_t:
22382         1;
22383         vuint16_t MBSEG1DS:7;            /* MESSAGE BUFFER SEGMENT 1 DATA SIZE */
22384       } B;
22385     } FR_MBDSR_16B_tag;
22386   
22387     typedef union {                      /* MESS. BUFFER SEG. SIZE & UTILISATION REG */
22388       vuint16_t R;
22389       struct {
22390        vuint16_t:
22391         2;
22392         vuint16_t LAST_MB_SEG1:6;        /* LAST MESS BUFFER IN SEG 1 */
22393        vuint16_t:
22394         2;
22395         vuint16_t LAST_MB_UTIL:6;        /* LAST MESSAGE BUFFER UTILISED */
22396       } B;
22397     } FR_MBSSUTR_16B_tag;
22398   
22399     typedef union {                      /* PE DRAM ACCESS REGISTER */
22400       vuint16_t R;
22401       struct {
22402         vuint16_t INST:4;                /* PE DRAM ACCESS INSTRUCTION */
22403         vuint16_t ADDR:11;               /* PE DRAM ACCESS ADDRESS */
22404         vuint16_t DAD:1;                 /* PE DRAM ACCESS DONE */
22405       } B;
22406     } FR_PEDRAR_16B_tag;
22407   
22408     typedef union {                      /* PE DRAM DATA REGISTER */
22409       vuint16_t R;
22410       struct {
22411         vuint16_t DATA:16;               /* DATA TO BE READ OR WRITTEN */
22412       } B;
22413     } FR_PEDRDR_16B_tag;
22414   
22415     typedef union {                      /* PROTOCOL OPERATION CONTROL REG */
22416       vuint16_t R;
22417       struct {
22418         vuint16_t WME:1;                 /* WRITE MODE EXTERNAL CORRECTION */
22419        vuint16_t:
22420         3;
22421         vuint16_t EOC_AP:2;              /* EXTERNAL OFFSET CORRECTION APPLICATION */
22422         vuint16_t ERC_AP:2;              /* EXTERNAL RATE CORRECTION APPLICATION */
22423         vuint16_t BSY:1;                 /* PROTOCOL CONTROL COMMAND WRITE BUSY */
22424        vuint16_t:
22425         3;
22426         vuint16_t POCCMD:4;              /* PROTOCOL CONTROL COMMAND */
22427       } B;
22428     } FR_POCR_16B_tag;
22429   
22430     typedef union {                      /* GLOBAL INTERRUPT FLAG & ENABLE REG */
22431       vuint16_t R;
22432       struct {
22433         vuint16_t MIF:1;                 /* MODULE INTERRUPT FLAG */
22434         vuint16_t PRIF:1;                /* PROTOCOL INTERRUPT FLAG */
22435         vuint16_t CHIF:1;                /* CHI INTERRUPT FLAG */
22436   
22437   #ifndef USE_FIELD_ALIASES_FR
22438   
22439         vuint16_t WUPIF:1;               /* WAKEUP INTERRUPT FLAG */
22440   
22441   #else
22442   
22443         vuint16_t WKUPIF:1;              /* deprecated name - please avoid */
22444   
22445   #endif
22446   
22447   #ifndef USE_FIELD_ALIASES_FR
22448   
22449         vuint16_t FAFBIF:1;              /* RECEIVE FIFO CHANNEL B ALMOST FULL INTERRUPT FLAG */
22450   
22451   #else
22452   
22453         vuint16_t FNEBIF:1;              /* deprecated name - please avoid */
22454   
22455   #endif
22456   
22457   #ifndef USE_FIELD_ALIASES_FR
22458   
22459         vuint16_t FAFAIF:1;              /* RECEIVE FIFO CHANNEL A ALMOST FULL INTERRUPT FLAG */
22460   
22461   #else
22462   
22463         vuint16_t FNEAIF:1;              /* deprecated name - please avoid */
22464   
22465   #endif
22466   
22467         vuint16_t RBIF:1;                /* RECEIVE MESSAGE BUFFER INTERRUPT FLAG */
22468         vuint16_t TBIF:1;                /* TRANSMIT BUFFER INTERRUPT FLAG */
22469         vuint16_t MIE:1;                 /* MODULE INTERRUPT ENABLE */
22470         vuint16_t PRIE:1;                /* PROTOCOL INTERRUPT ENABLE */
22471         vuint16_t CHIE:1;                /* CHI INTERRUPT ENABLE */
22472   
22473   #ifndef USE_FIELD_ALIASES_FR
22474   
22475         vuint16_t WUPIE:1;               /* WAKEUP INTERRUPT ENABLE */
22476   
22477   #else
22478   
22479         vuint16_t WKUPIE:1;              /* deprecated name - please avoid */
22480   
22481   #endif
22482   
22483         vuint16_t FNEBIE:1;              /* RECEIVE FIFO CHANNEL B NOT EMPTY INTERRUPT ENABLE */
22484         vuint16_t FNEAIE:1;              /* RECEIVE FIFO CHANNEL A NOT EMPTY INTERRUPT ENABLE */
22485         vuint16_t RBIE:1;                /* RECEIVE BUFFER INTERRUPT ENABLE */
22486         vuint16_t TBIE:1;                /* TRANSMIT BUFFER INTERRUPT ENABLE */
22487       } B;
22488     } FR_GIFER_16B_tag;
22489   
22490     typedef union {                      /* PROTOCOL INTERRUPT FLAG REGISTER 0 */
22491       vuint16_t R;
22492       struct {
22493   
22494   #ifndef USE_FIELD_ALIASES_FR
22495   
22496         vuint16_t FATL_IF:1;             /* FATAL PROTOCOL ERROR INTERRUPT FLAG */
22497   
22498   #else
22499   
22500         vuint16_t FATLIF:1;              /* deprecated name - please avoid */
22501   
22502   #endif
22503   
22504   #ifndef USE_FIELD_ALIASES_FR
22505   
22506         vuint16_t INTL_IF:1;             /* INTERNAL PROTOCOL ERROR INTERRUPT FLAG */
22507   
22508   #else
22509   
22510         vuint16_t INTLIF:1;              /* deprecated name - please avoid */
22511   
22512   #endif
22513   
22514   #ifndef USE_FIELD_ALIASES_FR
22515   
22516         vuint16_t ILCF_IF:1;             /* ILLEGAL PROTOCOL CONFIGURATION INTERRUPT FLAG */
22517   
22518   #else
22519   
22520         vuint16_t ILCFIF:1;              /* deprecated name - please avoid */
22521   
22522   #endif
22523   
22524   #ifndef USE_FIELD_ALIASES_FR
22525   
22526         vuint16_t CSA_IF:1;              /* COLDSTART ABORT INTERRUPT FLAG */
22527   
22528   #else
22529   
22530         vuint16_t CSAIF:1;               /* deprecated name - please avoid */
22531   
22532   #endif
22533   
22534   #ifndef USE_FIELD_ALIASES_FR
22535   
22536         vuint16_t MRC_IF:1;              /* MISSING RATE CORRECTION INTERRUPT FLAG */
22537   
22538   #else
22539   
22540         vuint16_t MRCIF:1;               /* deprecated name - please avoid */
22541   
22542   #endif
22543   
22544   #ifndef USE_FIELD_ALIASES_FR
22545   
22546         vuint16_t MOC_IF:1;              /* MISSING OFFSET CORRECTION INTERRUPT FLAG */
22547   
22548   #else
22549   
22550         vuint16_t MOCIF:1;               /* deprecated name - please avoid */
22551   
22552   #endif
22553   
22554   #ifndef USE_FIELD_ALIASES_FR
22555   
22556         vuint16_t CCL_IF:1;              /* CLOCK CORRECTION LIMIT REACHED INTERRUPT FLAG */
22557   
22558   #else
22559   
22560         vuint16_t CCLIF:1;               /* deprecated name - please avoid */
22561   
22562   #endif
22563   
22564   #ifndef USE_FIELD_ALIASES_FR
22565   
22566         vuint16_t MXS_IF:1;              /* MAX SYNC FRAMES DETECTED INTERRUPT FLAG */
22567   
22568   #else
22569   
22570         vuint16_t MXSIF:1;               /* deprecated name - please avoid */
22571   
22572   #endif
22573   
22574   #ifndef USE_FIELD_ALIASES_FR
22575   
22576         vuint16_t MTX_IF:1;              /* MEDIA ACCESS TEST SYMBOL RECEIVED INTERRUPT FLAG */
22577   
22578   #else
22579   
22580         vuint16_t MTXIF:1;               /* deprecated name - please avoid */
22581   
22582   #endif
22583   
22584   #ifndef USE_FIELD_ALIASES_FR
22585   
22586         vuint16_t LTXB_IF:1;             /* pLATESTTX VIOLATION ON CHANNEL B INTERRUPT FLAG */
22587   
22588   #else
22589   
22590         vuint16_t LTXBIF:1;              /* deprecated name - please avoid */
22591   
22592   #endif
22593   
22594   #ifndef USE_FIELD_ALIASES_FR
22595   
22596         vuint16_t LTXA_IF:1;             /* pLATESTTX VIOLATION ON CHANNEL A INTERRUPT FLAG */
22597   
22598   #else
22599   
22600         vuint16_t LTXAIF:1;              /* deprecated name - please avoid */
22601   
22602   #endif
22603   
22604   #ifndef USE_FIELD_ALIASES_FR
22605   
22606         vuint16_t TBVB_IF:1;             /* TRANSMISSION ACROSS BOUNDARY ON CHANNEL B INTERRUPT FLAG */
22607   
22608   #else
22609   
22610         vuint16_t TBVBIF:1;              /* deprecated name - please avoid */
22611   
22612   #endif
22613   
22614   #ifndef USE_FIELD_ALIASES_FR
22615   
22616         vuint16_t TBVA_IF:1;             /* TRANSMISSION ACROSS BOUNDARY ON CHANNEL A INTERRUPT FLAG */
22617   
22618   #else
22619   
22620         vuint16_t TBVAIF:1;              /* deprecated name - please avoid */
22621   
22622   #endif
22623   
22624   #ifndef USE_FIELD_ALIASES_FR
22625   
22626         vuint16_t TI2_IF:1;              /* TIMER 2 EXPIRED INTERRUPT FLAG */
22627   
22628   #else
22629   
22630         vuint16_t TI2IF:1;               /* deprecated name - please avoid */
22631   
22632   #endif
22633   
22634   #ifndef USE_FIELD_ALIASES_FR
22635   
22636         vuint16_t TI1_IF:1;              /* TIMER 1 EXPIRED INTERRUPT FLAG */
22637   
22638   #else
22639   
22640         vuint16_t TI1IF:1;               /* deprecated name - please avoid */
22641   
22642   #endif
22643   
22644   #ifndef USE_FIELD_ALIASES_FR
22645   
22646         vuint16_t CYS_IF:1;              /* CYCLE START INTERRUPT FLAG */
22647   
22648   #else
22649   
22650         vuint16_t CYSIF:1;               /* deprecated name - please avoid */
22651   
22652   #endif
22653   
22654       } B;
22655     } FR_PIFR0_16B_tag;
22656   
22657     typedef union {                      /* PROTOCOL INTERRUPT FLAG REGISTER 1 */
22658       vuint16_t R;
22659       struct {
22660   
22661   #ifndef USE_FIELD_ALIASES_FR
22662   
22663         vuint16_t EMC_IF:1;              /* ERROR MODE CHANGED INTERRUPT FLAG */
22664   
22665   #else
22666   
22667         vuint16_t EMCIF:1;               /* deprecated name - please avoid */
22668   
22669   #endif
22670   
22671   #ifndef USE_FIELD_ALIASES_FR
22672   
22673         vuint16_t IPC_IF:1;              /* ILLEGAL PROTOCOL CONTROL COMMAND INTERRUPT FLAG */
22674   
22675   #else
22676   
22677         vuint16_t IPCIF:1;               /* deprecated name - please avoid */
22678   
22679   #endif
22680   
22681   #ifndef USE_FIELD_ALIASES_FR
22682   
22683         vuint16_t PECF_IF:1;             /* PROTOCOL ENGINE COMMUNICATION FAILURE INTERRUPT FLAG */
22684   
22685   #else
22686   
22687         vuint16_t PECFIF:1;              /* deprecated name - please avoid */
22688   
22689   #endif
22690   
22691   #ifndef USE_FIELD_ALIASES_FR
22692   
22693         vuint16_t PSC_IF:1;              /* PROTOCOL STATE CHANGED INTERRUPT FLAG */
22694   
22695   #else
22696   
22697         vuint16_t PSCIF:1;               /* deprecated name - please avoid */
22698   
22699   #endif
22700   
22701   #ifndef USE_FIELD_ALIASES_FR
22702   
22703         vuint16_t SSI3_IF:1;             /* SLOT STATUS COUNTER 3 INCREMENTED INTERRUPT FLAG */
22704   
22705   #else
22706   
22707         vuint16_t SSI3IF:1;              /* deprecated name - please avoid */
22708   
22709   #endif
22710   
22711   #ifndef USE_FIELD_ALIASES_FR
22712   
22713         vuint16_t SSI2_IF:1;             /* SLOT STATUS COUNTER 2 INCREMENTED INTERRUPT FLAG */
22714   
22715   #else
22716   
22717         vuint16_t SSI2IF:1;              /* deprecated name - please avoid */
22718   
22719   #endif
22720   
22721   #ifndef USE_FIELD_ALIASES_FR
22722   
22723         vuint16_t SSI1_IF:1;             /* SLOT STATUS COUNTER 1 INCREMENTED INTERRUPT FLAG */
22724   
22725   #else
22726   
22727         vuint16_t SSI1IF:1;              /* deprecated name - please avoid */
22728   
22729   #endif
22730   
22731   #ifndef USE_FIELD_ALIASES_FR
22732   
22733         vuint16_t SSI0_IF:1;             /* SLOT STATUS COUNTER 0 INCREMENTED INTERRUPT FLAG */
22734   
22735   #else
22736   
22737         vuint16_t SSI0IF:1;              /* deprecated name - please avoid */
22738   
22739   #endif
22740   
22741        vuint16_t:
22742         2;
22743   
22744   #ifndef USE_FIELD_ALIASES_FR
22745   
22746         vuint16_t EVT_IF:1;              /* EVEN CYCLE TABLE WRITTEN INTERRUPT FLAG */
22747   
22748   #else
22749   
22750         vuint16_t EVTIF:1;               /* deprecated name - please avoid */
22751   
22752   #endif
22753   
22754   #ifndef USE_FIELD_ALIASES_FR
22755   
22756         vuint16_t ODT_IF:1;              /* ODD CYCLE TABLE WRITTEN INTERRUPT FLAG */
22757   
22758   #else
22759   
22760         vuint16_t ODTIF:1;               /* deprecated name - please avoid */
22761   
22762   #endif
22763   
22764        vuint16_t:
22765         4;
22766       } B;
22767     } FR_PIFR1_16B_tag;
22768   
22769     typedef union {                      /* PROTOCOL INTERRUPT ENABLE REGISTER 0 */
22770       vuint16_t R;
22771       struct {
22772   
22773   #ifndef USE_FIELD_ALIASES_FR
22774   
22775         vuint16_t FATL_IE:1;             /* FATAL PROTOCOL ERROR INTERRUPT ENABLE */
22776   
22777   #else
22778   
22779         vuint16_t FATLIE:1;              /* deprecated name - please avoid */
22780   
22781   #endif
22782   
22783   #ifndef USE_FIELD_ALIASES_FR
22784   
22785         vuint16_t INTL_IE:1;             /* INTERNAL PROTOCOL ERROR INTERRUPT ENABLE */
22786   
22787   #else
22788   
22789         vuint16_t INTLIE:1;              /* deprecated name - please avoid */
22790   
22791   #endif
22792   
22793   #ifndef USE_FIELD_ALIASES_FR
22794   
22795         vuint16_t ILCF_IE:1;             /* ILLEGAL PROTOCOL CONFIGURATION INTERRUPT ENABLE */
22796   
22797   #else
22798   
22799         vuint16_t ILCFIE:1;              /* deprecated name - please avoid */
22800   
22801   #endif
22802   
22803   #ifndef USE_FIELD_ALIASES_FR
22804   
22805         vuint16_t CSA_IE:1;              /* COLDSTART ABORT INTERRUPT ENABLE */
22806   
22807   #else
22808   
22809         vuint16_t CSAIE:1;               /* deprecated name - please avoid */
22810   
22811   #endif
22812   
22813   #ifndef USE_FIELD_ALIASES_FR
22814   
22815         vuint16_t MRC_IE:1;              /* MISSING RATE CORRECTION INTERRUPT ENABLE */
22816   
22817   #else
22818   
22819         vuint16_t MRCIE:1;               /* deprecated name - please avoid */
22820   
22821   #endif
22822   
22823   #ifndef USE_FIELD_ALIASES_FR
22824   
22825         vuint16_t MOC_IE:1;              /* MISSING OFFSET CORRECTION INTERRUPT ENABLE */
22826   
22827   #else
22828   
22829         vuint16_t MOCIE:1;               /* deprecated name - please avoid */
22830   
22831   #endif
22832   
22833   #ifndef USE_FIELD_ALIASES_FR
22834   
22835         vuint16_t CCL_IE:1;              /* CLOCK CORRECTION LIMIT REACHED */
22836   
22837   #else
22838   
22839         vuint16_t CCLIE:1;               /* deprecated name - please avoid */
22840   
22841   #endif
22842   
22843   #ifndef USE_FIELD_ALIASES_FR
22844   
22845         vuint16_t MXS_IE:1;              /* MAX SYNC FRAMES DETECTED INTERRUPT ENABLE */
22846   
22847   #else
22848   
22849         vuint16_t MXSIE:1;               /* deprecated name - please avoid */
22850   
22851   #endif
22852   
22853   #ifndef USE_FIELD_ALIASES_FR
22854   
22855         vuint16_t MTX_IE:1;              /* MEDIA ACCESS TEST SYMBOL RECEIVED INTERRUPT ENABLE */
22856   
22857   #else
22858   
22859         vuint16_t MTXIE:1;               /* deprecated name - please avoid */
22860   
22861   #endif
22862   
22863   #ifndef USE_FIELD_ALIASES_FR
22864   
22865         vuint16_t LTXB_IE:1;             /* pLATESTTX VIOLATION ON CHANNEL B INTERRUPT ENABLE */
22866   
22867   #else
22868   
22869         vuint16_t LTXBIE:1;              /* deprecated name - please avoid */
22870   
22871   #endif
22872   
22873   #ifndef USE_FIELD_ALIASES_FR
22874   
22875         vuint16_t LTXA_IE:1;             /* pLATESTTX VIOLATION ON CHANNEL A INTERRUPT ENABLE */
22876   
22877   #else
22878   
22879         vuint16_t LTXAIE:1;              /* deprecated name - please avoid */
22880   
22881   #endif
22882   
22883   #ifndef USE_FIELD_ALIASES_FR
22884   
22885         vuint16_t TBVB_IE:1;             /* TRANSMISSION ACROSS BOUNDARY ON CHANNEL B INTERRUPT ENABLE */
22886   
22887   #else
22888   
22889         vuint16_t TBVBIE:1;              /* deprecated name - please avoid */
22890   
22891   #endif
22892   
22893   #ifndef USE_FIELD_ALIASES_FR
22894   
22895         vuint16_t TBVA_IE:1;             /* TRANSMISSION ACROSS BOUNDARY ON CHANNEL A INTERRUPT ENABLE */
22896   
22897   #else
22898   
22899         vuint16_t TBVAIE:1;              /* deprecated name - please avoid */
22900   
22901   #endif
22902   
22903   #ifndef USE_FIELD_ALIASES_FR
22904   
22905         vuint16_t TI2_IE:1;              /* TIMER 2 EXPIRED INTERRUPT ENABLE */
22906   
22907   #else
22908   
22909         vuint16_t TI2IE:1;               /* deprecated name - please avoid */
22910   
22911   #endif
22912   
22913   #ifndef USE_FIELD_ALIASES_FR
22914   
22915         vuint16_t TI1_IE:1;              /* TIMER 1 EXPIRED INTERRUPT ENABLE */
22916   
22917   #else
22918   
22919         vuint16_t TI1IE:1;               /* deprecated name - please avoid */
22920   
22921   #endif
22922   
22923   #ifndef USE_FIELD_ALIASES_FR
22924   
22925         vuint16_t CYS_IE:1;              /* CYCLE START INTERRUPT ENABLE */
22926   
22927   #else
22928   
22929         vuint16_t CYSIE:1;               /* deprecated name - please avoid */
22930   
22931   #endif
22932   
22933       } B;
22934     } FR_PIER0_16B_tag;
22935   
22936     typedef union {                      /* PROTOCOL INTERRUPT ENABLE REGISTER 1 */
22937       vuint16_t R;
22938       struct {
22939   
22940   #ifndef USE_FIELD_ALIASES_FR
22941   
22942         vuint16_t EMC_IE:1;              /* ERROR MODE CHANGED INTERRUPT Enable */
22943   
22944   #else
22945   
22946         vuint16_t EMCIE:1;               /* deprecated name - please avoid */
22947   
22948   #endif
22949   
22950   #ifndef USE_FIELD_ALIASES_FR
22951   
22952         vuint16_t IPC_IE:1;              /* ILLEGAL PROTOCOL CONTROL COMMAND INTERRUPT Enable */
22953   
22954   #else
22955   
22956         vuint16_t IPCIE:1;               /* deprecated name - please avoid */
22957   
22958   #endif
22959   
22960   #ifndef USE_FIELD_ALIASES_FR
22961   
22962         vuint16_t PECF_IE:1;             /* PROTOCOL ENGINE COMMUNICATION FAILURE INTERRUPT Enable */
22963   
22964   #else
22965   
22966         vuint16_t PECFIE:1;              /* deprecated name - please avoid */
22967   
22968   #endif
22969   
22970   #ifndef USE_FIELD_ALIASES_FR
22971   
22972         vuint16_t PSC_IE:1;              /* PROTOCOL STATE CHANGED INTERRUPT Enable */
22973   
22974   #else
22975   
22976         vuint16_t PSCIE:1;               /* deprecated name - please avoid */
22977   
22978   #endif
22979   
22980   #ifndef USE_FIELD_ALIASES_FR
22981   
22982         /* MJR Edited */
22983         vuint16_t SSI_3_0_IE:4;          /* SLOT STATUS COUNTER INCREMENTED INTERRUPT Enable */
22984   
22985   #else
22986   
22987         vuint16_t SSI3IE:1;
22988         vuint16_t SSI2IE:1;
22989         vuint16_t SSI1IE:1;
22990         vuint16_t SSI0IE:1;
22991   
22992   #endif
22993   
22994        vuint16_t:
22995         2;
22996   
22997   #ifndef USE_FIELD_ALIASES_FR
22998   
22999         vuint16_t EVT_IE:1;              /* EVEN CYCLE TABLE WRITTEN INTERRUPT Enable */
23000   
23001   #else
23002   
23003         vuint16_t EVTIE:1;               /* deprecated name - please avoid */
23004   
23005   #endif
23006   
23007   #ifndef USE_FIELD_ALIASES_FR
23008   
23009         vuint16_t ODT_IE:1;              /* ODD CYCLE TABLE WRITTEN INTERRUPT Enable */
23010   
23011   #else
23012   
23013         vuint16_t ODTIE:1;               /* deprecated name - please avoid */
23014   
23015   #endif
23016   
23017        vuint16_t:
23018         4;
23019       } B;
23020     } FR_PIER1_16B_tag;
23021   
23022     typedef union {                      /* CHI ERROR FLAG REGISTER */
23023       vuint16_t R;
23024       struct {
23025   
23026   #ifndef USE_FIELD_ALIASES_FR
23027   
23028         vuint16_t FRLB_EF:1;             /* FRAME LOST CHANNEL B ERROR FLAG */
23029   
23030   #else
23031   
23032         vuint16_t FRLBEF:1;              /* deprecated name - please avoid */
23033   
23034   #endif
23035   
23036   #ifndef USE_FIELD_ALIASES_FR
23037   
23038         vuint16_t FRLA_EF:1;             /* FRAME LOST CHANNEL A ERROR FLAG */
23039   
23040   #else
23041   
23042         vuint16_t FRLAEF:1;              /* deprecated name - please avoid */
23043   
23044   #endif
23045   
23046   #ifndef USE_FIELD_ALIASES_FR
23047   
23048         vuint16_t PCMI_EF:1;             /* PROTOCOL COMMAND IGNORED ERROR FLAG */
23049   
23050   #else
23051   
23052         vuint16_t PCMIEF:1;              /* deprecated name - please avoid */
23053   
23054   #endif
23055   
23056   #ifndef USE_FIELD_ALIASES_FR
23057   
23058         vuint16_t FOVB_EF:1;             /* RECEIVE FIFO OVERRUN CHANNEL B ERROR FLAG */
23059   
23060   #else
23061   
23062         vuint16_t FOVBEF:1;              /* deprecated name - please avoid */
23063   
23064   #endif
23065   
23066   #ifndef USE_FIELD_ALIASES_FR
23067   
23068         vuint16_t FOVA_EF:1;             /* RECEIVE FIFO OVERRUN CHANNEL A ERROR FLAG */
23069   
23070   #else
23071   
23072         vuint16_t FOVAEF:1;              /* deprecated name - please avoid */
23073   
23074   #endif
23075   
23076   #ifndef USE_FIELD_ALIASES_FR
23077   
23078         vuint16_t MBS_EF:1;              /* MESSAGE BUFFER SEARCH ERROR FLAG */
23079   
23080   #else
23081   
23082         vuint16_t MSBEF:1;               /* deprecated name - please avoid */
23083   
23084   #endif
23085   
23086   #ifndef USE_FIELD_ALIASES_FR
23087   
23088         vuint16_t MBU_EF:1;              /* MESSAGE BUFFER UTILIZATION ERROR FLAG */
23089   
23090   #else
23091   
23092         vuint16_t MBUEF:1;               /* deprecated name - please avoid */
23093   
23094   #endif
23095   
23096   #ifndef USE_FIELD_ALIASES_FR
23097   
23098         vuint16_t LCK_EF:1;              /* LOCK ERROR FLAG */
23099   
23100   #else
23101   
23102         vuint16_t LCKEF:1;               /* deprecated name - please avoid */
23103   
23104   #endif
23105   
23106   #ifndef USE_FIELD_ALIASES_FR
23107   
23108         vuint16_t DBL_EF:1;              /* DOUBLE TRANSMIT MESSAGE BUFFER LOCK ERROR FLAG */
23109   
23110   #else
23111   
23112         vuint16_t DBLEF:1;               /* deprecated name - please avoid */
23113   
23114   #endif
23115   
23116   #ifndef USE_FIELD_ALIASES_FR
23117   
23118         vuint16_t SBCF_EF:1;             /* SYSTEM BUS COMMUNICATION FAILURE ERROR FLAG */
23119   
23120   #else
23121   
23122         vuint16_t SBCFEF:1;              /* deprecated name - please avoid */
23123   
23124   #endif
23125   
23126   #ifndef USE_FIELD_ALIASES_FR
23127   
23128         vuint16_t FID_EF:1;              /* FRAME ID ERROR FLAG */
23129   
23130   #else
23131   
23132         vuint16_t FIDEF:1;               /* deprecated name - please avoid */
23133   
23134   #endif
23135   
23136   #ifndef USE_FIELD_ALIASES_FR
23137   
23138         vuint16_t DPL_EF:1;              /* DYNAMIC PAYLOAD LENGTH ERROR FLAG */
23139   
23140   #else
23141   
23142         vuint16_t DPLEF:1;               /* deprecated name - please avoid */
23143   
23144   #endif
23145   
23146   #ifndef USE_FIELD_ALIASES_FR
23147   
23148         vuint16_t SPL_EF:1;              /* STATIC PAYLOAD LENGTH ERROR FLAG */
23149   
23150   #else
23151   
23152         vuint16_t SPLEF:1;               /* deprecated name - please avoid */
23153   
23154   #endif
23155   
23156   #ifndef USE_FIELD_ALIASES_FR
23157   
23158         vuint16_t NML_EF:1;              /* NETWORK MANAGEMENT LENGTH ERROR FLAG */
23159   
23160   #else
23161   
23162         vuint16_t NMLEF:1;               /* deprecated name - please avoid */
23163   
23164   #endif
23165   
23166   #ifndef USE_FIELD_ALIASES_FR
23167   
23168         vuint16_t NMF_EF:1;              /* NETWORK MANAGEMENT FRAME ERROR FLAG */
23169   
23170   #else
23171   
23172         vuint16_t NMFEF:1;               /* deprecated name - please avoid */
23173   
23174   #endif
23175   
23176   #ifndef USE_FIELD_ALIASES_FR
23177   
23178         vuint16_t ILSA_EF:1;             /* ILLEGAL SYSTEM MEMORY ACCESS ERROR FLAG */
23179   
23180   #else
23181   
23182         vuint16_t ILSAEF:1;              /* deprecated name - please avoid */
23183   
23184   #endif
23185   
23186       } B;
23187     } FR_CHIERFR_16B_tag;
23188   
23189     typedef union {                      /* Message Buffer Interrupt Vector Register */
23190       vuint16_t R;
23191       struct {
23192        vuint16_t:
23193         2;
23194         vuint16_t TBIVEC:6;              /* Transmit Buffer Interrupt Vector */
23195        vuint16_t:
23196         2;
23197         vuint16_t RBIVEC:6;              /* Receive Buffer Interrupt Vector */
23198       } B;
23199     } FR_MBIVEC_16B_tag;
23200   
23201     typedef union {                      /* Channel A Status Error Counter Register */
23202       vuint16_t R;
23203       struct {
23204         vuint16_t STATUS_ERR_CNT:16;     /* Channel Status Error Counter */
23205       } B;
23206     } FR_CASERCR_16B_tag;
23207   
23208     typedef union {                      /* Channel B Status Error Counter Register */
23209       vuint16_t R;
23210       struct {
23211         vuint16_t STATUS_ERR_CNT:16;     /* Channel Status Error Counter */
23212       } B;
23213     } FR_CBSERCR_16B_tag;
23214   
23215     typedef union {                      /* Protocol Status Register 0 */
23216       vuint16_t R;
23217       struct {
23218         vuint16_t ERRMODE:2;             /* Error Mode */
23219         vuint16_t SLOTMODE:2;            /* Slot Mode */
23220        vuint16_t:
23221         1;
23222         vuint16_t PROTSTATE:3;           /* Protocol State */
23223   
23224   #ifndef USE_FIELD_ALIASES_FR
23225   
23226         vuint16_t STARTUPSTATE:4;        /* Startup State */
23227   
23228   #else
23229   
23230         vuint16_t SUBSTATE:4;            /* deprecated name - please avoid */
23231   
23232   #endif
23233   
23234         vuint16_t WAKEUPSTATE:4;         /* Wakeup Status */
23235       } B;
23236     } FR_PSR0_16B_tag;
23237   
23238     typedef union {                      /* Protocol Status Register 1 */
23239       vuint16_t R;
23240       struct {
23241         vuint16_t CSAA:1;                /* Coldstart Attempt Aborted Flag */
23242         vuint16_t CSP:1;                 /* Leading Coldstart Path */
23243        vuint16_t:
23244         1;
23245         vuint16_t REMCSAT:5;             /* Remaining Coldstart Attempts */
23246         vuint16_t CPN:1;                 /* Leading Coldstart Path Noise */
23247         vuint16_t HHR:1;                 /* Host Halt Request Pending */
23248         vuint16_t FRZ:1;                 /* Freeze Occurred */
23249         vuint16_t APTAC:5;               /* Allow Passive to Active Counter */
23250       } B;
23251     } FR_PSR1_16B_tag;
23252   
23253     typedef union {                      /* Protocol Status Register 2 */
23254       vuint16_t R;
23255       struct {
23256         vuint16_t NBVB:1;                /* NIT Boundary Violation on Channel B */
23257         vuint16_t NSEB:1;                /* NIT Syntax Error on Channel B */
23258         vuint16_t STCB:1;                /* Symbol Window Transmit Conflict on Channel B */
23259   
23260   #ifndef USE_FIELD_ALIASES_FR
23261   
23262         vuint16_t SSVB:1;                /* Symbol Window Boundary Violation on Channel B */
23263   
23264   #else
23265   
23266         vuint16_t SBVB:1;                /* deprecated name - please avoid */
23267   
23268   #endif
23269   
23270         vuint16_t SSEB:1;                /* Symbol Window Syntax Error on Channel B */
23271         vuint16_t MTB:1;                 /* Media Access Test Symbol MTS Received on Channel B */
23272         vuint16_t NBVA:1;                /* NIT Boundary Violation on Channel A */
23273         vuint16_t NSEA:1;                /* NIT Syntax Error on Channel A */
23274         vuint16_t STCA:1;                /* Symbol Window Transmit Conflict on Channel A */
23275         vuint16_t SBVA:1;                /* Symbol Window Boundary Violation on Channel A */
23276         vuint16_t SSEA:1;                /* Symbol Window Syntax Error on Channel A */
23277         vuint16_t MTA:1;                 /* Media Access Test Symbol MTS Received on Channel A */
23278         vuint16_t CLKCORRFAILCNT:4;      /* Clock Correction Failed Counter */
23279       } B;
23280     } FR_PSR2_16B_tag;
23281   
23282     typedef union {                      /* Protocol Status Register 3 */
23283       vuint16_t R;
23284       struct {
23285        vuint16_t:
23286         2;
23287         vuint16_t WUB:1;                 /* Wakeup Symbol Received on Channel B */
23288         vuint16_t ABVB:1;                /* Aggregated Boundary Violation on Channel B */
23289         vuint16_t AACB:1;                /* Aggregated Additional Communication on Channel B */
23290         vuint16_t ACEB:1;                /* Aggregated Content Error on Channel B */
23291         vuint16_t ASEB:1;                /* Aggregated Syntax Error on Channel B */
23292         vuint16_t AVFB:1;                /* Aggregated Valid Frame on Channel B */
23293        vuint16_t:
23294         2;
23295         vuint16_t WUA:1;                 /* Wakeup Symbol Received on Channel A */
23296         vuint16_t ABVA:1;                /* Aggregated Boundary Violation on Channel A */
23297         vuint16_t AACA:1;                /* Aggregated Additional Communication on Channel A */
23298         vuint16_t ACEA:1;                /* Aggregated Content Error on Channel A */
23299         vuint16_t ASEA:1;                /* Aggregated Syntax Error on Channel A */
23300         vuint16_t AVFA:1;                /* Aggregated Valid Frame on Channel A */
23301       } B;
23302     } FR_PSR3_16B_tag;
23303   
23304     typedef union {                      /* Macrotick Counter Register */
23305       vuint16_t R;
23306       struct {
23307        vuint16_t:
23308         2;
23309         vuint16_t MTCT:14;               /* Macrotick Counter */
23310       } B;
23311     } FR_MTCTR_16B_tag;
23312   
23313     typedef union {                      /* Cycle Counter Register */
23314       vuint16_t R;
23315       struct {
23316        vuint16_t:
23317         10;
23318         vuint16_t CYCCNT:6;              /* Cycle Counter */
23319       } B;
23320     } FR_CYCTR_16B_tag;
23321   
23322     typedef union {                      /* Slot Counter Channel A Register */
23323       vuint16_t R;
23324       struct {
23325        vuint16_t:
23326         5;
23327         vuint16_t SLOTCNTA:11;           /* Slot Counter Value for Channel A */
23328       } B;
23329     } FR_SLTCTAR_16B_tag;
23330   
23331     typedef union {                      /* Slot Counter Channel B Register */
23332       vuint16_t R;
23333       struct {
23334        vuint16_t:
23335         5;
23336         vuint16_t SLOTCNTB:11;           /* Slot Counter Value for Channel B */
23337       } B;
23338     } FR_SLTCTBR_16B_tag;
23339   
23340     typedef union {                      /* Rate Correction Value Register */
23341       vuint16_t R;
23342       struct {
23343         vuint16_t RATECORR:16;           /* Rate Correction Value */
23344       } B;
23345     } FR_RTCORVR_16B_tag;
23346   
23347     typedef union {                      /* Offset Correction Value Register */
23348       vuint16_t R;
23349       struct {
23350        vuint16_t:
23351         6;
23352         vuint16_t OFFSETCORR:10;         /* Offset Correction Value */
23353       } B;
23354     } FR_OFCORVR_16B_tag;
23355   
23356     typedef union {                      /* Combined Interrupt Flag Register */
23357       vuint16_t R;
23358       struct {
23359        vuint16_t:
23360         8;
23361   
23362   #ifndef USE_FIELD_ALIASES_FR
23363   
23364         vuint16_t MIF:1;                 /* Module Interrupt Flag */
23365   
23366   #else
23367   
23368         vuint16_t MIFR:1;                /* deprecated name - please avoid */
23369   
23370   #endif
23371   
23372   #ifndef USE_FIELD_ALIASES_FR
23373   
23374         vuint16_t PRIF:1;                /* Protocol Interrupt Flag */
23375   
23376   #else
23377   
23378         vuint16_t PRIFR:1;               /* deprecated name - please avoid */
23379   
23380   #endif
23381   
23382   #ifndef USE_FIELD_ALIASES_FR
23383   
23384         vuint16_t CHIF:1;                /* CHI Interrupt Flag */
23385   
23386   #else
23387   
23388         vuint16_t CHIFR:1;               /* deprecated name - please avoid */
23389   
23390   #endif
23391   
23392   #ifndef USE_FIELD_ALIASES_FR
23393   
23394         vuint16_t WUPIF:1;               /* Wakeup Interrupt Flag */
23395   
23396   #else
23397   
23398         vuint16_t WUPIFR:1;              /* deprecated name - please avoid */
23399   
23400   #endif
23401   
23402   #ifndef USE_FIELD_ALIASES_FR
23403   
23404         vuint16_t FAFBIF:1;              /* Receive FIFO channel B Almost Full Interrupt Flag */
23405   
23406   #else
23407   
23408         vuint16_t FNEBIFR:1;             /* deprecated name - please avoid */
23409   
23410   #endif
23411   
23412   #ifndef USE_FIELD_ALIASES_FR
23413   
23414         vuint16_t FAFAIF:1;              /* Receive FIFO channel A Almost Full Interrupt Flag */
23415   
23416   #else
23417   
23418         vuint16_t FNEAIFR:1;             /* deprecated name - please avoid */
23419   
23420   #endif
23421   
23422   #ifndef USE_FIELD_ALIASES_FR
23423   
23424         vuint16_t RBIF:1;                /* Receive Message Buffer Interrupt Flag */
23425   
23426   #else
23427   
23428         vuint16_t RBIFR:1;               /* deprecated name - please avoid */
23429   
23430   #endif
23431   
23432   #ifndef USE_FIELD_ALIASES_FR
23433   
23434         vuint16_t TBIF:1;                /* Transmit Message Buffer Interrupt Flag */
23435   
23436   #else
23437   
23438         vuint16_t TBIFR:1;               /* deprecated name - please avoid */
23439   
23440   #endif
23441   
23442       } B;
23443     } FR_CIFR_16B_tag;
23444   
23445     typedef union {                      /* System Memory Access Time-Out Register */
23446       vuint16_t R;
23447       struct {
23448        vuint16_t:
23449         8;
23450         vuint16_t TIMEOUT:8;             /* Time-Out */
23451       } B;
23452     } FR_SYMATOR_16B_tag;
23453   
23454     typedef union {                      /* Sync Frame Counter Register */
23455       vuint16_t R;
23456       struct {
23457         vuint16_t SFEVB:4;               /* Sync Frames Channel B, even cycle */
23458         vuint16_t SFEVA:4;               /* Sync Frames Channel A, even cycle */
23459         vuint16_t SFODB:4;               /* Sync Frames Channel B, odd cycle */
23460         vuint16_t SFODA:4;               /* Sync Frames Channel A, odd cycle */
23461       } B;
23462     } FR_SFCNTR_16B_tag;
23463   
23464     typedef union {                      /* Sync Frame Table Offset Register */
23465       vuint16_t R;
23466       struct {
23467         vuint16_t SFT_OFFSET_15_1:15;    /* Sync Frame Table Offset */
23468        vuint16_t:
23469         1;
23470       } B;
23471     } FR_SFTOR_16B_tag;
23472   
23473     typedef union {                      /* Sync Frame Table Configuration, Control, Status Register */
23474       vuint16_t R;
23475       struct {
23476         vuint16_t ELKT:1;                /* Even Cycle Tables Lock/Unlock Trigger */
23477         vuint16_t OLKT:1;                /* Odd Cycle Tables Lock/Unlock Trigger */
23478         vuint16_t CYCNUM:6;              /* Cycle Number */
23479         vuint16_t ELKS:1;                /* Even Cycle Tables Lock Status */
23480         vuint16_t OLKS:1;                /* Odd Cycle Tables Lock Status */
23481         vuint16_t EVAL:1;                /* Even Cycle Tables Valid */
23482         vuint16_t OVAL:1;                /* Odd Cycle Tables Valid */
23483        vuint16_t:
23484         1;
23485         vuint16_t OPT:1;                 /* One Pair Trigger */
23486         vuint16_t SDVEN:1;               /* Sync Frame Deviation Table Enable */
23487   
23488   #ifndef USE_FIELD_ALIASES_FR
23489   
23490         vuint16_t SIVEN:1;               /* Sync Frame ID Table Enable */
23491   
23492   #else
23493   
23494         vuint16_t SIDEN:1;               /* deprecated name - please avoid */
23495   
23496   #endif
23497   
23498       } B;
23499     } FR_SFTCCSR_16B_tag;
23500   
23501     typedef union {                      /* Sync Frame ID Rejection Filter */
23502       vuint16_t R;
23503       struct {
23504        vuint16_t:
23505         6;
23506         vuint16_t SYNFRID:10;            /* Sync Frame Rejection ID */
23507       } B;
23508     } FR_SFIDRFR_16B_tag;
23509   
23510     typedef union {                      /* Sync Frame ID Acceptance Filter Value Register */
23511       vuint16_t R;
23512       struct {
23513        vuint16_t:
23514         6;
23515         vuint16_t FVAL:10;               /* Filter Value */
23516       } B;
23517     } FR_SFIDAFVR_16B_tag;
23518   
23519     typedef union {                      /* Sync Frame ID Acceptance Filter Mask Register */
23520       vuint16_t R;
23521       struct {
23522        vuint16_t:
23523         6;
23524         vuint16_t FMSK:10;               /* Filter Mask */
23525       } B;
23526     } FR_SFIDAFMR_16B_tag;
23527   
23528     typedef union {                      /* Network Management Vector Register0 */
23529       vuint16_t R;
23530       struct {
23531         vuint16_t NMVP_15_8:8;           /* Network Management Vector Part */
23532         vuint16_t NMVP_7_0:8;            /* Network Management Vector Part */
23533       } B;
23534     } FR_NMVR0_16B_tag;
23535   
23536     typedef union {                      /* Network Management Vector Register1 */
23537       vuint16_t R;
23538       struct {
23539         vuint16_t NMVP_15_8:8;           /* Network Management Vector Part */
23540         vuint16_t NMVP_7_0:8;            /* Network Management Vector Part */
23541       } B;
23542     } FR_NMVR1_16B_tag;
23543   
23544     typedef union {                      /* Network Management Vector Register2 */
23545       vuint16_t R;
23546       struct {
23547         vuint16_t NMVP_15_8:8;           /* Network Management Vector Part */
23548         vuint16_t NMVP_7_0:8;            /* Network Management Vector Part */
23549       } B;
23550     } FR_NMVR2_16B_tag;
23551   
23552     typedef union {                      /* Network Management Vector Register3 */
23553       vuint16_t R;
23554       struct {
23555         vuint16_t NMVP_15_8:8;           /* Network Management Vector Part */
23556         vuint16_t NMVP_7_0:8;            /* Network Management Vector Part */
23557       } B;
23558     } FR_NMVR3_16B_tag;
23559   
23560     typedef union {                      /* Network Management Vector Register4 */
23561       vuint16_t R;
23562       struct {
23563         vuint16_t NMVP_15_8:8;           /* Network Management Vector Part */
23564         vuint16_t NMVP_7_0:8;            /* Network Management Vector Part */
23565       } B;
23566     } FR_NMVR4_16B_tag;
23567   
23568     typedef union {                      /* Network Management Vector Register5 */
23569       vuint16_t R;
23570       struct {
23571         vuint16_t NMVP_15_8:8;           /* Network Management Vector Part */
23572         vuint16_t NMVP_7_0:8;            /* Network Management Vector Part */
23573       } B;
23574     } FR_NMVR5_16B_tag;
23575   
23576     typedef union {                      /* Network Management Vector Length Register */
23577       vuint16_t R;
23578       struct {
23579        vuint16_t:
23580         12;
23581         vuint16_t NMVL:4;                /* Network Management Vector Length */
23582       } B;
23583     } FR_NMVLR_16B_tag;
23584   
23585     typedef union {                      /* Timer Configuration and Control Register */
23586       vuint16_t R;
23587       struct {
23588        vuint16_t:
23589         2;
23590   
23591   #ifndef USE_FIELD_ALIASES_FR
23592   
23593         vuint16_t T2_CFG:1;              /* Timer T2 Configuration */
23594   
23595   #else
23596   
23597         vuint16_t T2CFG:1;               /* deprecated name - please avoid */
23598   
23599   #endif
23600   
23601   #ifndef USE_FIELD_ALIASES_FR
23602   
23603         vuint16_t T2_REP:1;              /* Timer T2 Repetitive Mode */
23604   
23605   #else
23606   
23607         vuint16_t T2REP:1;               /* deprecated name - please avoid */
23608   
23609   #endif
23610   
23611        vuint16_t:
23612         1;
23613         vuint16_t T2SP:1;                /* Timer T2 Stop */
23614         vuint16_t T2TR:1;                /* Timer T2 Trigger */
23615         vuint16_t T2ST:1;                /* Timer T2 State */
23616        vuint16_t:
23617         3;
23618   
23619   #ifndef USE_FIELD_ALIASES_FR
23620   
23621         vuint16_t T1_REP:1;              /* Timer T1 Repetitive Mode */
23622   
23623   #else
23624   
23625         vuint16_t T1REP:1;               /* deprecated name - please avoid */
23626   
23627   #endif
23628   
23629        vuint16_t:
23630         1;
23631         vuint16_t T1SP:1;                /* Timer T1 Stop */
23632         vuint16_t T1TR:1;                /* Timer T1 Trigger */
23633         vuint16_t T1ST:1;                /* Timer T1 State */
23634       } B;
23635     } FR_TICCR_16B_tag;
23636   
23637     typedef union {                      /* Timer 1 Cycle Set Register */
23638       vuint16_t R;
23639       struct {
23640        vuint16_t:
23641         2;
23642   
23643   #ifndef USE_FIELD_ALIASES_FR
23644   
23645         vuint16_t T1_CYC_VAL:6;          /* Timer T1 Cycle Filter Value */
23646   
23647   #else
23648   
23649         vuint16_t TI1CYCVAL:6;           /* deprecated name - please avoid */
23650   
23651   #endif
23652   
23653        vuint16_t:
23654         2;
23655   
23656   #ifndef USE_FIELD_ALIASES_FR
23657   
23658         vuint16_t T1_CYC_MSK:6;          /* Timer T1 Cycle Filter Mask */
23659   
23660   #else
23661   
23662         vuint16_t TI1CYCMSK:6;           /* deprecated name - please avoid */
23663   
23664   #endif
23665   
23666       } B;
23667     } FR_TI1CYSR_16B_tag;
23668   
23669     typedef union {                      /* Timer 1 Macrotick Offset Register */
23670       vuint16_t R;
23671       struct {
23672        vuint16_t:
23673         2;
23674         vuint16_t T1_MTOFFSET:14;        /* Timer 1 Macrotick Offset */
23675       } B;
23676     } FR_TI1MTOR_16B_tag;
23677   
23678     typedef union {                      /* Timer 2 Configuration Register 0 */
23679       vuint16_t R;
23680       struct {
23681        vuint16_t:
23682         2;
23683         vuint16_t T2_CYC_VAL:6;          /* Timer T2 Cycle Filter Value */
23684        vuint16_t:
23685         2;
23686         vuint16_t T2_CYC_MSK:6;          /* Timer T2 Cycle Filter Mask */
23687       } B;
23688     } FR_TI2CR0_16B_tag;
23689   
23690     typedef union {                      /* Timer 2 Configuration Register 1 */
23691       vuint16_t R;
23692       struct {
23693         vuint16_t T2_MTCNT:16;           /* Timer T2 Macrotick Offset */
23694       } B;
23695     } FR_TI2CR1_16B_tag;
23696   
23697     typedef union {                      /* Slot Status Selection Register */
23698       vuint16_t R;
23699       struct {
23700         vuint16_t WMD:1;                 /* Write Mode */
23701        vuint16_t:
23702         1;
23703         vuint16_t SEL:2;                 /* Selector */
23704        vuint16_t:
23705         1;
23706         vuint16_t SLOTNUMBER:11;         /* Slot Number */
23707       } B;
23708     } FR_SSSR_16B_tag;
23709   
23710     typedef union {                      /* Slot Status Counter Condition Register */
23711       vuint16_t R;
23712       struct {
23713         vuint16_t WMD:1;                 /* Write Mode */
23714        vuint16_t:
23715         1;
23716         vuint16_t SEL:2;                 /* Selector */
23717        vuint16_t:
23718         1;
23719         vuint16_t CNTCFG:2;              /* Counter Configuration */
23720         vuint16_t MCY:1;                 /* Multi Cycle Selection */
23721         vuint16_t VFR:1;                 /* Valid Frame Restriction */
23722         vuint16_t SYF:1;                 /* Sync Frame Restriction */
23723         vuint16_t NUF:1;                 /* Null Frame Restriction */
23724         vuint16_t SUF:1;                 /* Startup Frame Restriction */
23725         vuint16_t STATUSMASK:4;          /* Slot Status Mask */
23726       } B;
23727     } FR_SSCCR_16B_tag;
23728   
23729     typedef union {                      /* Slot Status Register */
23730       vuint16_t R;
23731       struct {
23732         vuint16_t VFB:1;                 /* Valid Frame on Channel B */
23733         vuint16_t SYB:1;                 /* Sync Frame Indicator Channel B */
23734         vuint16_t NFB:1;                 /* Null Frame Indicator Channel B */
23735         vuint16_t SUB:1;                 /* Startup Frame Indicator Channel B */
23736         vuint16_t SEB:1;                 /* Syntax Error on Channel B */
23737         vuint16_t CEB:1;                 /* Content Error on Channel B */
23738         vuint16_t BVB:1;                 /* Boundary Violation on Channel B */
23739         vuint16_t TCB:1;                 /* Transmission Conflict on Channel B */
23740         vuint16_t VFA:1;                 /* Valid Frame on Channel A */
23741         vuint16_t SYA:1;                 /* Sync Frame Indicator Channel A */
23742         vuint16_t NFA:1;                 /* Null Frame Indicator Channel A */
23743         vuint16_t SUA:1;                 /* Startup Frame Indicator Channel A */
23744         vuint16_t SEA:1;                 /* Syntax Error on Channel A */
23745         vuint16_t CEA:1;                 /* Content Error on Channel A */
23746         vuint16_t BVA:1;                 /* Boundary Violation on Channel A */
23747         vuint16_t TCA:1;                 /* Transmission Conflict on Channel A */
23748       } B;
23749     } FR_SSR_16B_tag;
23750   
23751     typedef union {                      /* Slot Status Counter Register0 */
23752       vuint16_t R;
23753       struct {
23754         vuint16_t SLOTSTSTUSCNT:16;      /* Slot Status Counter */
23755       } B;
23756     } FR_SSCR0_16B_tag;
23757   
23758     typedef union {                      /* Slot Status Counter Register1 */
23759       vuint16_t R;
23760       struct {
23761         vuint16_t SLOTSTSTUSCNT:16;      /* Slot Status Counter */
23762       } B;
23763     } FR_SSCR1_16B_tag;
23764   
23765     typedef union {                      /* Slot Status Counter Register2 */
23766       vuint16_t R;
23767       struct {
23768         vuint16_t SLOTSTSTUSCNT:16;      /* Slot Status Counter */
23769       } B;
23770     } FR_SSCR2_16B_tag;
23771   
23772     typedef union {                      /* Slot Status Counter Register3 */
23773       vuint16_t R;
23774       struct {
23775         vuint16_t SLOTSTSTUSCNT:16;      /* Slot Status Counter */
23776       } B;
23777     } FR_SSCR3_16B_tag;
23778   
23779     typedef union {                      /* MTS A Configuration Register */
23780       vuint16_t R;
23781       struct {
23782         vuint16_t MTE:1;                 /* Media Access Test Symbol Transmission Enable */
23783        vuint16_t:
23784         1;
23785         vuint16_t CYCCNTMSK:6;           /* Cycle Counter Mask */
23786        vuint16_t:
23787         2;
23788         vuint16_t CYCCNTVAL:6;           /* Cycle Counter Value */
23789       } B;
23790     } FR_MTSACFR_16B_tag;
23791   
23792     typedef union {                      /* MTS B Configuration Register */
23793       vuint16_t R;
23794       struct {
23795         vuint16_t MTE:1;                 /* Media Access Test Symbol Transmission Enable */
23796        vuint16_t:
23797         1;
23798         vuint16_t CYCCNTMSK:6;           /* Cycle Counter Mask */
23799        vuint16_t:
23800         2;
23801         vuint16_t CYCCNTVAL:6;           /* Cycle Counter Value */
23802       } B;
23803     } FR_MTSBCFR_16B_tag;
23804   
23805     typedef union {                      /* Receive Shadow Buffer Index Register */
23806       vuint16_t R;
23807       struct {
23808         vuint16_t WMD:1;                 /* Write Mode */
23809        vuint16_t:
23810         1;
23811         vuint16_t SEL:2;                 /* Selector */
23812        vuint16_t:
23813         5;
23814         vuint16_t RSBIDX:7;              /* Receive Shadow Buffer Index */
23815       } B;
23816     } FR_RSBIR_16B_tag;
23817   
23818     typedef union {                      /* Receive FIFO Watermark and Selection Register */
23819       vuint16_t R;
23820       struct {
23821         vuint16_t WM:8;                  /* Watermark Value */
23822        vuint16_t:
23823         7;
23824         vuint16_t SEL:1;                 /* Select */
23825       } B;
23826     } FR_RFWMSR_16B_tag;
23827   
23828     typedef union {                      /* Receive FIFO Start Index Register */
23829       vuint16_t R;
23830       struct {
23831        vuint16_t:
23832         6;
23833         vuint16_t SIDX:10;               /* Start Index */
23834       } B;
23835     } FR_RF_RFSIR_16B_tag;
23836   
23837     typedef union {                      /* Receive FIFO Depth and Size Register */
23838       vuint16_t R;
23839       struct {
23840   
23841   #ifndef USE_FIELD_ALIASES_FR
23842   
23843         vuint16_t FIFO_DEPTH:8;          /* FIFO Depth */
23844   
23845   #else
23846   
23847         vuint16_t FIFODEPTH:8;           /* deprecated name - please avoid */
23848   
23849   #endif
23850   
23851        vuint16_t:
23852         1;
23853   
23854   #ifndef USE_FIELD_ALIASES_FR
23855   
23856         vuint16_t ENTRY_SIZE:7;          /* Entry Size */
23857   
23858   #else
23859   
23860         vuint16_t ENTRYSIZE:7;           /* deprecated name - please avoid */
23861   
23862   #endif
23863   
23864       } B;
23865     } FR_RFDSR_16B_tag;
23866   
23867     typedef union {                      /* Receive FIFO A Read Index Register */
23868       vuint16_t R;
23869       struct {
23870        vuint16_t:
23871         6;
23872         vuint16_t RDIDX:10;              /* Read Index */
23873       } B;
23874     } FR_RFARIR_16B_tag;
23875   
23876     typedef union {                      /* Receive FIFO B Read Index Register */
23877       vuint16_t R;
23878       struct {
23879        vuint16_t:
23880         6;
23881         vuint16_t RDIDX:10;              /* Read Index */
23882       } B;
23883     } FR_RFBRIR_16B_tag;
23884   
23885     typedef union {                      /* Receive FIFO Message ID Acceptance Filter Value Register */
23886       vuint16_t R;
23887       struct {
23888         vuint16_t MIDAFVAL:16;           /* Message ID Acceptance Filter Value */
23889       } B;
23890     } FR_RFMIDAFVR_16B_tag;
23891   
23892     typedef union {                      /* Receive FIFO Message ID Acceptance Filter Mask Register */
23893       vuint16_t R;
23894       struct {
23895         vuint16_t MIDAFMSK:16;           /* Message ID Acceptance Filter Mask */
23896       } B;
23897     } FR_RFMIDAFMR_16B_tag;
23898   
23899     typedef union {                      /* Receive FIFO Frame ID Rejection Filter Value Register */
23900       vuint16_t R;
23901       struct {
23902        vuint16_t:
23903         5;
23904         vuint16_t FIDRFVAL:11;           /* Frame ID Rejection Filter Value */
23905       } B;
23906     } FR_RFFIDRFVR_16B_tag;
23907   
23908     typedef union {                      /* Receive FIFO Frame ID Rejection Filter Mask Register */
23909       vuint16_t R;
23910       struct {
23911        vuint16_t:
23912         5;
23913         vuint16_t FIDRFMSK:11;           /* Frame ID Rejection Filter Mask */
23914       } B;
23915     } FR_RFFIDRFMR_16B_tag;
23916   
23917     typedef union {                      /* Receive FIFO Range Filter Configuration Register */
23918       vuint16_t R;
23919       struct {
23920         vuint16_t WMD:1;                 /* Write Mode */
23921         vuint16_t IBD:1;                 /* Interval Boundary */
23922         vuint16_t SEL:2;                 /* Filter Selector */
23923        vuint16_t:
23924         1;
23925         vuint16_t SID:11;                /* Slot ID */
23926       } B;
23927     } FR_RFRFCFR_16B_tag;
23928   
23929     typedef union {                      /* Receive FIFO Range Filter Control Register */
23930       vuint16_t R;
23931       struct {
23932        vuint16_t:
23933         4;
23934         vuint16_t F3MD:1;                /* Range Filter 3 Mode */
23935         vuint16_t F2MD:1;                /* Range Filter 2 Mode */
23936         vuint16_t F1MD:1;                /* Range Filter 1 Mode */
23937         vuint16_t F0MD:1;                /* Range Filter 0 Mode */
23938        vuint16_t:
23939         4;
23940         vuint16_t F3EN:1;                /* Range Filter 3 Enable */
23941         vuint16_t F2EN:1;                /* Range Filter 2 Enable */
23942         vuint16_t F1EN:1;                /* Range Filter 1 Enable */
23943         vuint16_t F0EN:1;                /* Range Filter 0 Enable */
23944       } B;
23945     } FR_RFRFCTR_16B_tag;
23946   
23947     typedef union {                      /* Last Dynamic Transmit Slot Channel A Register */
23948       vuint16_t R;
23949       struct {
23950        vuint16_t:
23951         5;
23952         vuint16_t LASTDYNTXSLOTA:11;     /* Last Dynamic Transmission Slot Channel A */
23953       } B;
23954     } FR_LDTXSLAR_16B_tag;
23955   
23956     typedef union {                      /* Last Dynamic Transmit Slot Channel B Register */
23957       vuint16_t R;
23958       struct {
23959        vuint16_t:
23960         5;
23961         vuint16_t LASTDYNTXSLOTB:11;     /* Last Dynamic Transmission Slot Channel B */
23962       } B;
23963     } FR_LDTXSLBR_16B_tag;
23964   
23965     typedef union {                      /* Protocol Configuration Register 0 */
23966       vuint16_t R;
23967       struct {
23968         vuint16_t ACTION_POINT_OFFSET:6; /* gdActionPointOffset - 1 */
23969         vuint16_t STATIC_SLOT_LENGTH:10; /* gdStaticSlot */
23970       } B;
23971     } FR_PCR0_16B_tag;
23972   
23973     typedef union {                      /* Protocol Configuration Register 1 */
23974       vuint16_t R;
23975       struct {
23976        vuint16_t:
23977         2;
23978         vuint16_t MACRO_AFTER_FIRST_STATIC_SLOT:14;/* gMacroPerCycle - gdStaticSlot */
23979       } B;
23980     } FR_PCR1_16B_tag;
23981   
23982     typedef union {                      /* Protocol Configuration Register 2 */
23983       vuint16_t R;
23984       struct {
23985         vuint16_t MINISLOT_AFTER_ACTION_POINT:6;/* gdMinislot - gdMinislotActionPointOffset - 1 */
23986         vuint16_t NUMBER_OF_STATIC_SLOTS:10;/* gNumberOfStaticSlots */
23987       } B;
23988     } FR_PCR2_16B_tag;
23989   
23990     typedef union {                      /* Protocol Configuration Register 3 */
23991       vuint16_t R;
23992       struct {
23993         vuint16_t WAKEUP_SYMBOL_RX_LOW:6;/* gdWakeupSymbolRxLow */
23994   
23995   #ifndef USE_FIELD_ALIASES_FR
23996   
23997         vuint16_t MINISLOT_ACTION_POINT_OFFSET_4_0:5;/* gdMinislotActionPointOffset - 1 */
23998   
23999   #else
24000   
24001         vuint16_t MINISLOT_ACTION_POINT_OFFSET:5;/* deprecated name - please avoid */
24002   
24003   #endif
24004   
24005         vuint16_t COLDSTART_ATTEMPTS:5;  /* gColdstartAttempts */
24006       } B;
24007     } FR_PCR3_16B_tag;
24008   
24009     typedef union {                      /* Protocol Configuration Register 4 */
24010       vuint16_t R;
24011       struct {
24012         vuint16_t CAS_RX_LOW_MAX:7;      /* gdCASRxLowMax - 1 */
24013         vuint16_t WAKEUP_SYMBOL_RX_WINDOW:9;/* gdWakeupSymbolRxWindow */
24014       } B;
24015     } FR_PCR4_16B_tag;
24016   
24017     typedef union {                      /* Protocol Configuration Register 5 */
24018       vuint16_t R;
24019       struct {
24020         vuint16_t TSS_TRANSMITTER:4;     /* gdTSSTransmitter */
24021         vuint16_t WAKEUP_SYMBOL_TX_LOW:6;/* gdWakeupSymbolTxLow */
24022         vuint16_t WAKEUP_SYMBOL_RX_IDLE:6;/* gdWakeupSymbolRxIdle */
24023       } B;
24024     } FR_PCR5_16B_tag;
24025   
24026     typedef union {                      /* Protocol Configuration Register 6 */
24027       vuint16_t R;
24028       struct {
24029        vuint16_t:
24030         1;
24031         vuint16_t SYMBOL_WINDOW_AFTER_ACTION_POINT:8;/* gdSymbolWindow - gdActionPointOffset - 1 */
24032         vuint16_t MACRO_INITIAL_OFFSET_A:7;/* pMacroInitialOffset[A] */
24033       } B;
24034     } FR_PCR6_16B_tag;
24035   
24036     typedef union {                      /* Protocol Configuration Register 7 */
24037       vuint16_t R;
24038       struct {
24039         vuint16_t DECODING_CORRECTION_B:9;/* pDecodingCorrection + pDelayCompensation[B] + 2 */
24040         vuint16_t MICRO_PER_MACRO_NOM_HALF:7;/* round(pMicroPerMacroNom / 2) */
24041       } B;
24042     } FR_PCR7_16B_tag;
24043   
24044     typedef union {                      /* Protocol Configuration Register 8 */
24045       vuint16_t R;
24046       struct {
24047         vuint16_t MAX_WITHOUT_CLOCK_CORRECTION_FATAL:4;/* gMaxWithoutClockCorrectionFatal */
24048         vuint16_t MAX_WITHOUT_CLOCK_CORRECTION_PASSIVE:4;/* gMaxWithoutClockCorrectionPassive */
24049         vuint16_t WAKEUP_SYMBOL_TX_IDLE:8;/* gdWakeupSymbolTxIdle */
24050       } B;
24051     } FR_PCR8_16B_tag;
24052   
24053     typedef union {                      /* Protocol Configuration Register 9 */
24054       vuint16_t R;
24055       struct {
24056         vuint16_t MINISLOT_EXISTS:1;     /* gNumberOfMinislots!=0 */
24057         vuint16_t SYMBOL_WINDOW_EXISTS:1;/* gdSymbolWindow!=0 */
24058         vuint16_t OFFSET_CORRECTION_OUT:14;/* pOffsetCorrectionOut */
24059       } B;
24060     } FR_PCR9_16B_tag;
24061   
24062     typedef union {                      /* Protocol Configuration Register 10 */
24063       vuint16_t R;
24064       struct {
24065         vuint16_t SINGLE_SLOT_ENABLED:1; /* pSingleSlotEnabled */
24066         vuint16_t WAKEUP_CHANNEL:1;      /* pWakeupChannel */
24067         vuint16_t MACRO_PER_CYCLE:14;    /* pMicroPerCycle */
24068       } B;
24069     } FR_PCR10_16B_tag;
24070   
24071     typedef union {                      /* Protocol Configuration Register 11 */
24072       vuint16_t R;
24073       struct {
24074         vuint16_t KEY_SLOT_USED_FOR_STARTUP:1;/* pKeySlotUsedForStartup */
24075         vuint16_t KEY_SLOT_USED_FOR_SYNC:1;/* pKeySlotUsedForSync */
24076         vuint16_t OFFSET_CORRECTION_START:14;/* gOffsetCorrectionStart */
24077       } B;
24078     } FR_PCR11_16B_tag;
24079   
24080     typedef union {                      /* Protocol Configuration Register 12 */
24081       vuint16_t R;
24082       struct {
24083         vuint16_t ALLOW_PASSIVE_TO_ACTIVE:5;/* pAllowPassiveToActive */
24084         vuint16_t KEY_SLOT_HEADER_CRC:11;/* header CRC for key slot */
24085       } B;
24086     } FR_PCR12_16B_tag;
24087   
24088     typedef union {                      /* Protocol Configuration Register 13 */
24089       vuint16_t R;
24090       struct {
24091         vuint16_t FIRST_MINISLOT_ACTION_POINT_OFFSET:6;/* max(gdActionPointOffset,gdMinislotActionPointOffset) - 1 */
24092         vuint16_t STATIC_SLOT_AFTER_ACTION_POINT:10;/* gdStaticSlot - gdActionPointOffset - 1 */
24093       } B;
24094     } FR_PCR13_16B_tag;
24095   
24096     typedef union {                      /* Protocol Configuration Register 14 */
24097       vuint16_t R;
24098       struct {
24099         vuint16_t RATE_CORRECTION_OUT:11;/* pRateCorrectionOut */
24100   
24101   #ifndef USE_FIELD_ALIASES_FR
24102   
24103         vuint16_t LISTEN_TIMEOUT_20_16:5;/* pdListenTimeout - 1 */
24104   
24105   #else
24106   
24107         vuint16_t LISTEN_TIMEOUT_H:5;    /* deprecated name - please avoid */
24108   
24109   #endif
24110   
24111       } B;
24112     } FR_PCR14_16B_tag;
24113   
24114     typedef union {                      /* Protocol Configuration Register 15 */
24115       vuint16_t R;
24116       struct {
24117   
24118   #ifndef USE_FIELD_ALIASES_FR
24119   
24120         vuint16_t LISTEN_TIMEOUT_15_0:16;/* pdListenTimeout - 1 */
24121   
24122   #else
24123   
24124         vuint16_t LISTEN_TIMEOUT_L:16;   /* deprecated name - please avoid */
24125   
24126   #endif
24127   
24128       } B;
24129     } FR_PCR15_16B_tag;
24130   
24131     typedef union {                      /* Protocol Configuration Register 16 */
24132       vuint16_t R;
24133       struct {
24134         vuint16_t MACRO_INITIAL_OFFSET_B:7;/* pMacroInitialOffset[B] */
24135   
24136   #ifndef USE_FIELD_ALIASES_FR
24137   
24138         vuint16_t NOISE_LISTEN_TIMEOUT_24_16:9;/* (gListenNoise * pdListenTimeout) - 1 */
24139   
24140   #else
24141   
24142         vuint16_t NOISE_LISTEN_TIMEOUT_H:9;/* deprecated name - please avoid */
24143   
24144   #endif
24145   
24146       } B;
24147     } FR_PCR16_16B_tag;
24148   
24149     typedef union {                      /* Protocol Configuration Register 17 */
24150       vuint16_t R;
24151       struct {
24152   
24153   #ifndef USE_FIELD_ALIASES_FR
24154   
24155         vuint16_t NOISE_LISTEN_TIMEOUT_15_0:16;/* (gListenNoise * pdListenTimeout) - 1 */
24156   
24157   #else
24158   
24159         vuint16_t NOISE_LISTEN_TIMEOUT_L:16;/* deprecated name - please avoid */
24160   
24161   #endif
24162   
24163       } B;
24164     } FR_PCR17_16B_tag;
24165   
24166     typedef union {                      /* Protocol Configuration Register 18 */
24167       vuint16_t R;
24168       struct {
24169         vuint16_t WAKEUP_PATTERN:6;      /* pWakeupPattern */
24170         vuint16_t KEY_SLOT_ID:10;        /* pKeySlotId */
24171       } B;
24172     } FR_PCR18_16B_tag;
24173   
24174     typedef union {                      /* Protocol Configuration Register 19 */
24175       vuint16_t R;
24176       struct {
24177         vuint16_t DECODING_CORRECTION_A:9;/* pDecodingCorrection + pDelayCompensation[A] + 2 */
24178         vuint16_t PAYLOAD_LENGTH_STATIC:7;/* gPayloadLengthStatic */
24179       } B;
24180     } FR_PCR19_16B_tag;
24181   
24182     typedef union {                      /* Protocol Configuration Register 20 */
24183       vuint16_t R;
24184       struct {
24185         vuint16_t MICRO_INITIAL_OFFSET_B:8;/* pMicroInitialOffset[B] */
24186         vuint16_t MICRO_INITIAL_OFFSET_A:8;/* pMicroInitialOffset[A] */
24187       } B;
24188     } FR_PCR20_16B_tag;
24189   
24190     typedef union {                      /* Protocol Configuration Register 21 */
24191       vuint16_t R;
24192       struct {
24193         vuint16_t EXTERN_RATE_CORRECTION:3;/* pExternRateCorrection */
24194         vuint16_t LATEST_TX:13;          /* gNumberOfMinislots - pLatestTx */
24195       } B;
24196     } FR_PCR21_16B_tag;
24197   
24198     typedef union {                      /* Protocol Configuration Register 22 */
24199       vuint16_t R;
24200       struct {
24201         vuint16_t R:1;                   /* Reserved bit */
24202   
24203   #ifndef USE_FIELD_ALIASES_FR
24204   
24205         vuint16_t COMP_ACCEPTED_STARRUP_RANGE_A:11;/* pdAcceptedStartupRange - pDelayCompensationChA */
24206   
24207   #else
24208   
24209         vuint16_t COMP_ACCEPTED_STARTUP_RANGE_A:11;/* deprecated name - please avoid */
24210   
24211   #endif
24212   
24213   #ifndef USE_FIELD_ALIASES_FR
24214   
24215         vuint16_t MICRO_PER_CYCLE_19_16:4;/* gMicroPerCycle */
24216   
24217   #else
24218   
24219         vuint16_t MICRO_PER_CYCLE_H:4;   /* deprecated name - please avoid */
24220   
24221   #endif
24222   
24223       } B;
24224     } FR_PCR22_16B_tag;
24225   
24226     typedef union {                      /* Protocol Configuration Register 23 */
24227       vuint16_t R;
24228       struct {
24229   
24230   #ifndef USE_FIELD_ALIASES_FR
24231   
24232         vuint16_t MICRO_PER_CYCLE_15_0:16;/* pMicroPerCycle */
24233   
24234   #else
24235   
24236         vuint16_t micro_per_cycle_l:16;  /* deprecated name - please avoid */
24237   
24238   #endif
24239   
24240       } B;
24241     } FR_PCR23_16B_tag;
24242   
24243     typedef union {                      /* Protocol Configuration Register 24 */
24244       vuint16_t R;
24245       struct {
24246         vuint16_t CLUSTER_DRIFT_DAMPING:5;/* pClusterDriftDamping */
24247         vuint16_t MAX_PAYLOAD_LENGTH_DYNAMIC:7;/* pPayloadLengthDynMax */
24248   
24249   #ifndef USE_FIELD_ALIASES_FR
24250   
24251         vuint16_t MICRO_PER_CYCLE_MIN_19_16:4;/* pMicroPerCycle - pdMaxDrift */
24252   
24253   #else
24254   
24255         vuint16_t MICRO_PER_CYCLE_MIN_H:4;/* deprecated name - please avoid */
24256   
24257   #endif
24258   
24259       } B;
24260     } FR_PCR24_16B_tag;
24261   
24262     typedef union {                      /* Protocol Configuration Register 25 */
24263       vuint16_t R;
24264       struct {
24265   
24266   #ifndef USE_FIELD_ALIASES_FR
24267   
24268         vuint16_t MICRO_PER_CYCLE_MIN_15_0:16;/* pMicroPerCycle - pdMaxDrift */
24269   
24270   #else
24271   
24272         vuint16_t MICRO_PER_CYCLE_MIN_L:16;/* deprecated name - please avoid */
24273   
24274   #endif
24275   
24276       } B;
24277     } FR_PCR25_16B_tag;
24278   
24279     typedef union {                      /* Protocol Configuration Register 26 */
24280       vuint16_t R;
24281       struct {
24282         vuint16_t ALLOW_HALT_DUE_TO_CLOCK:1;/* pAllowHaltDueToClock */
24283         vuint16_t COMP_ACCEPTED_STARTUP_RANGE_B:11;/* pdAcceptedStartupRange - pDelayCompensationChB */
24284   
24285   #ifndef USE_FIELD_ALIASES_FR
24286   
24287         vuint16_t MICRO_PER_CYCLE_MAX_19_16:4;/* pMicroPerCycle + pdMaxDrift */
24288   
24289   #else
24290   
24291         vuint16_t MICRO_PER_CYCLE_MAX_H:4;/* deprecated name - please avoid */
24292   
24293   #endif
24294   
24295       } B;
24296     } FR_PCR26_16B_tag;
24297   
24298     typedef union {                      /* Protocol Configuration Register 27 */
24299       vuint16_t R;
24300       struct {
24301   
24302   #ifndef USE_FIELD_ALIASES_FR
24303   
24304         vuint16_t MICRO_PER_CYCLE_MAX_15_0:16;/* pMicroPerCycle + pdMaxDrift */
24305   
24306   #else
24307   
24308         vuint16_t MICRO_PER_CYCLE_MAX_L:16;/* deprecated name - please avoid */
24309   
24310   #endif
24311   
24312       } B;
24313     } FR_PCR27_16B_tag;
24314   
24315     typedef union {                      /* Protocol Configuration Register 28 */
24316       vuint16_t R;
24317       struct {
24318         vuint16_t DYNAMIC_SLOT_IDLE_PHASE:2;/* gdDynamicSlotIdlePhase */
24319         vuint16_t MACRO_AFTER_OFFSET_CORRECTION:14;/* gMacroPerCycle - gOffsetCorrectionStart */
24320       } B;
24321     } FR_PCR28_16B_tag;
24322   
24323     typedef union {                      /* Protocol Configuration Register 29 */
24324       vuint16_t R;
24325       struct {
24326         vuint16_t EXTERN_OFFSET_CORRECTION:3;/* pExternOffsetCorrection */
24327         vuint16_t MINISLOTS_MAX:13;      /* gNumberOfMinislots - 1 */
24328       } B;
24329     } FR_PCR29_16B_tag;
24330   
24331     typedef union {                      /* Protocol Configuration Register 30 */
24332       vuint16_t R;
24333       struct {
24334        vuint16_t:
24335         12;
24336         vuint16_t SYNC_NODE_MAX:4;       /* gSyncNodeMax */
24337       } B;
24338     } FR_PCR30_16B_tag;
24339   
24340     typedef union {                      /* Receive FIFO System Memory Base Address High Register */
24341       vuint16_t R;
24342       struct {
24343         vuint16_t SMBA_31_16:16;         /* System Memory Base Address */
24344       } B;
24345     } FR_RFSYMBHADR_16B_tag;
24346   
24347     typedef union {                      /* Receive FIFO System Memory Base Address Low Register */
24348       vuint16_t R;
24349       struct {
24350         vuint16_t SMBA_15_4:12;          /* System Memory Base Address */
24351        vuint16_t:
24352         4;
24353       } B;
24354     } FR_RFSYMBLADR_16B_tag;
24355   
24356     typedef union {                      /* Receive FIFO Periodic Timer Register */
24357       vuint16_t R;
24358       struct {
24359        vuint16_t:
24360         2;
24361         vuint16_t PTD:14;                /* Periodic Timer Duration */
24362       } B;
24363     } FR_RFPTR_16B_tag;
24364   
24365     typedef union {                      /* Receive FIFO Fill Level and Pop Count Register */
24366       vuint16_t R;
24367       struct {
24368         vuint16_t FLPCB:8;               /* Fill Level and Pop Count Channel B */
24369         vuint16_t FLPCA:8;               /* Fill Level and Pop Count Channel A */
24370       } B;
24371     } FR_RFFLPCR_16B_tag;
24372   
24373     typedef union {                      /* ECC Error Interrupt Flag and Enable Register */
24374       vuint16_t R;
24375       struct {
24376         vuint16_t LRNE_OF:1;             /* LRAM Non-Corrected Error Overflow Flag */
24377         vuint16_t LRCE_OF:1;             /* LRAM Corrected Error Overflow Flag */
24378         vuint16_t DRNE_OF:1;             /* DRAM Non-Corrected Error Overflow Flag */
24379         vuint16_t DRCE_OF:1;             /* DRAM Corrected Error Overflow Flag */
24380         vuint16_t LRNE_IF:1;             /* LRAM Non-Corrected Error Interrupt Flag */
24381         vuint16_t LRCE_IF:1;             /* LRAM Corrected Error Interrupt Flag */
24382         vuint16_t DRNE_IF:1;             /* DRAM Non-Corrected Error Interrupt Flag */
24383         vuint16_t DRCE_IF:1;             /* DRAM Corrected Error Interrupt Flag */
24384        vuint16_t:
24385         4;
24386         vuint16_t LRNE_IE:1;             /* LRAM Non-Corrected Error Interrupt Enable */
24387         vuint16_t LRCE_IE:1;             /* LRAM Corrected Error Interrupt Enable */
24388         vuint16_t DRNE_IE:1;             /* DRAM Non-Corrected Error Interrupt Enable */
24389         vuint16_t DRCE_IE:1;             /* DRAM Corrected Error Interrupt Enable */
24390       } B;
24391     } FR_EEIFER_16B_tag;
24392   
24393     typedef union {                      /* ECC Error Report and Injection Control Register */
24394       vuint16_t R;
24395       struct {
24396         vuint16_t BSY:1;                 /* Register Update Busy */
24397        vuint16_t:
24398         5;
24399         vuint16_t ERS:2;                 /* Error Report Select */
24400        vuint16_t:
24401         3;
24402         vuint16_t ERM:1;                 /* Error Report Mode */
24403        vuint16_t:
24404         2;
24405         vuint16_t EIM:1;                 /* Error Injection Mode */
24406         vuint16_t EIE:1;                 /* Error Injection Enable */
24407       } B;
24408     } FR_EERICR_16B_tag;
24409   
24410     typedef union {                      /* ECC Error Report Adress Register */
24411       vuint16_t R;
24412       struct {
24413         vuint16_t MID:1;                 /* Memory Identifier */
24414         vuint16_t BANK:3;                /* Memory Bank */
24415         vuint16_t ADDR:12;               /* Memory Address */
24416       } B;
24417     } FR_EERAR_16B_tag;
24418   
24419     typedef union {                      /* ECC Error Report Data Register */
24420       vuint16_t R;
24421       struct {
24422         vuint16_t DATA:16;               /* Data */
24423       } B;
24424     } FR_EERDR_16B_tag;
24425   
24426     typedef union {                      /* ECC Error Report Code Register */
24427       vuint16_t R;
24428       struct {
24429        vuint16_t:
24430         11;
24431         vuint16_t CODE:5;                /* Code */
24432       } B;
24433     } FR_EERCR_16B_tag;
24434   
24435     typedef union {                      /* ECC Error Injection Address Register */
24436       vuint16_t R;
24437       struct {
24438         vuint16_t MID:1;                 /* Memory Identifier */
24439         vuint16_t BANK:3;                /* Memory Bank */
24440         vuint16_t ADDR:12;               /* Memory Address */
24441       } B;
24442     } FR_EEIAR_16B_tag;
24443   
24444     typedef union {                      /* ECC Error Injection Data Register */
24445       vuint16_t R;
24446       struct {
24447         vuint16_t DATA:16;               /* Data */
24448       } B;
24449     } FR_EEIDR_16B_tag;
24450   
24451     typedef union {                      /* ECC Error Injection Code Register */
24452       vuint16_t R;
24453       struct {
24454        vuint16_t:
24455         11;
24456         vuint16_t CODE:5;                /* Code */
24457       } B;
24458     } FR_EEICR_16B_tag;
24459   
24460     /* Register layout for all registers MBCCSR ... */
24461     typedef union {                      /* Message Buffer Configuration Control Status Register */
24462       vuint16_t R;
24463       struct {
24464        vuint16_t:
24465         1;
24466         vuint16_t MCM:1;                 /* Message Buffer Commit Mode */
24467         vuint16_t MBT:1;                 /* Message Buffer Type */
24468         vuint16_t MTD:1;                 /* Message Buffer Transfer Direction */
24469         vuint16_t CMT:1;                 /* Commit for Transmission */
24470         vuint16_t EDT:1;                 /* Enable/Disable Trigger */
24471         vuint16_t LCKT:1;                /* Lock/Unlock Trigger */
24472         vuint16_t MBIE:1;                /* Message Buffer Interrupt Enable */
24473        vuint16_t:
24474         3;
24475         vuint16_t DUP:1;                 /* Data Updated */
24476         vuint16_t DVAL:1;                /* DataValid */
24477         vuint16_t EDS:1;                 /* Enable/Disable Status */
24478         vuint16_t LCKS:1;                /* LockStatus */
24479         vuint16_t MBIF:1;                /* Message Buffer Interrupt Flag */
24480       } B;
24481     } FR_MBCCSR_16B_tag;
24482   
24483     /* Register layout for all registers MBCCFR ... */
24484     typedef union {                      /* Message Buffer Cycle Counter Filter Register */
24485       vuint16_t R;
24486       struct {
24487         vuint16_t MTM:1;                 /* Message Buffer Transmission Mode */
24488   
24489   #ifndef USE_FIELD_ALIASES_FR
24490   
24491         vuint16_t CHA:1;                 /* Channel Assignment */
24492   
24493   #else
24494   
24495         vuint16_t CHNLA:1;               /* deprecated name - please avoid */
24496   
24497   #endif
24498   
24499   #ifndef USE_FIELD_ALIASES_FR
24500   
24501         vuint16_t CHB:1;                 /* Channel Assignment */
24502   
24503   #else
24504   
24505         vuint16_t CHNLB:1;               /* deprecated name - please avoid */
24506   
24507   #endif
24508   
24509         vuint16_t CCFE:1;                /* Cycle Counter Filtering Enable */
24510         vuint16_t CCFMSK:6;              /* Cycle Counter Filtering Mask */
24511         vuint16_t CCFVAL:6;              /* Cycle Counter Filtering Value */
24512       } B;
24513     } FR_MBCCFR_16B_tag;
24514   
24515     /* Register layout for all registers MBFIDR ... */
24516     typedef union {                      /* Message Buffer Frame ID Register */
24517       vuint16_t R;
24518       struct {
24519        vuint16_t:
24520         5;
24521         vuint16_t FID:11;                /* Frame ID */
24522       } B;
24523     } FR_MBFIDR_16B_tag;
24524   
24525     /* Register layout for all registers MBIDXR ... */
24526     typedef union {                      /* Message Buffer Index Register */
24527       vuint16_t R;
24528       struct {
24529        vuint16_t:
24530         9;
24531         vuint16_t MBIDX:7;               /* Message Buffer Index */
24532       } B;
24533     } FR_MBIDXR_16B_tag;
24534   
24535     /* Register layout for generated register(s) NMVR... */
24536     typedef union {                      /*  */
24537       vuint16_t R;
24538     } FR_NMVR_16B_tag;
24539   
24540     /* Register layout for generated register(s) SSCR... */
24541     typedef union {                      /*  */
24542       vuint16_t R;
24543     } FR_SSCR_16B_tag;
24544   
24545     typedef struct FR_MB_struct_tag {
24546       /* Message Buffer Configuration Control Status Register */
24547       FR_MBCCSR_16B_tag MBCCSR;          /* relative offset: 0x0000 */
24548   
24549       /* Message Buffer Cycle Counter Filter Register */
24550       FR_MBCCFR_16B_tag MBCCFR;          /* relative offset: 0x0002 */
24551   
24552       /* Message Buffer Frame ID Register */
24553       FR_MBFIDR_16B_tag MBFIDR;          /* relative offset: 0x0004 */
24554   
24555       /* Message Buffer Index Register */
24556       FR_MBIDXR_16B_tag MBIDXR;          /* relative offset: 0x0006 */
24557     } FR_MB_tag;
24558   
24559     typedef struct FR_struct_tag {
24560       /* Module Version Number */
24561       FR_MVR_16B_tag MVR;                /* offset: 0x0000 size: 16 bit */
24562   
24563       /* Module Configuration Register */
24564       FR_MCR_16B_tag MCR;                /* offset: 0x0002 size: 16 bit */
24565       union {
24566         /* SYSTEM MEMORY BASE ADD HIGH REG */
24567         FR_SYMBADHR_16B_tag SYMBADHR;    /* offset: 0x0004 size: 16 bit */
24568         FR_SYMBADHR_16B_tag SYSBADHR;    /* deprecated - please avoid */
24569       };
24570   
24571       union {
24572         /* SYSTEM MEMORY BASE ADD LOW  REG */
24573         FR_SYMBADLR_16B_tag SYMBADLR;    /* offset: 0x0006 size: 16 bit */
24574         FR_SYMBADLR_16B_tag SYSBADLR;    /* deprecated - please avoid */
24575       };
24576   
24577       /* STROBE SIGNAL CONTROL REGISTER */
24578       FR_STBSCR_16B_tag STBSCR;          /* offset: 0x0008 size: 16 bit */
24579       int8_t FR_reserved_000A[2];
24580   
24581       /* MESSAGE BUFFER DATA SIZE REGISTER */
24582       FR_MBDSR_16B_tag MBDSR;            /* offset: 0x000C size: 16 bit */
24583   
24584       /* MESS. BUFFER SEG. SIZE & UTILISATION REG */
24585       FR_MBSSUTR_16B_tag MBSSUTR;        /* offset: 0x000E size: 16 bit */
24586       union {
24587         /* PE DRAM ACCESS REGISTER */
24588         FR_PEDRAR_16B_tag PEDRAR;        /* offset: 0x0010 size: 16 bit */
24589         FR_PEDRAR_16B_tag PADR;          /* deprecated - please avoid */
24590       };
24591   
24592       union {
24593         /* PE DRAM DATA REGISTER */
24594         FR_PEDRDR_16B_tag PEDRDR;        /* offset: 0x0012 size: 16 bit */
24595         FR_PEDRDR_16B_tag PDAR;          /* deprecated - please avoid */
24596       };
24597   
24598       /* PROTOCOL OPERATION CONTROL REG */
24599       FR_POCR_16B_tag POCR;              /* offset: 0x0014 size: 16 bit */
24600   
24601       /* GLOBAL INTERRUPT FLAG & ENABLE REG */
24602       FR_GIFER_16B_tag GIFER;            /* offset: 0x0016 size: 16 bit */
24603   
24604       /* PROTOCOL INTERRUPT FLAG REGISTER 0 */
24605       FR_PIFR0_16B_tag PIFR0;            /* offset: 0x0018 size: 16 bit */
24606   
24607       /* PROTOCOL INTERRUPT FLAG REGISTER 1 */
24608       FR_PIFR1_16B_tag PIFR1;            /* offset: 0x001A size: 16 bit */
24609   
24610       /* PROTOCOL INTERRUPT ENABLE REGISTER 0 */
24611       FR_PIER0_16B_tag PIER0;            /* offset: 0x001C size: 16 bit */
24612   
24613       /* PROTOCOL INTERRUPT ENABLE REGISTER 1 */
24614       FR_PIER1_16B_tag PIER1;            /* offset: 0x001E size: 16 bit */
24615   
24616       /* CHI ERROR FLAG REGISTER */
24617       FR_CHIERFR_16B_tag CHIERFR;        /* offset: 0x0020 size: 16 bit */
24618   
24619       /* Message Buffer Interrupt Vector Register */
24620       FR_MBIVEC_16B_tag MBIVEC;          /* offset: 0x0022 size: 16 bit */
24621   
24622       /* Channel A Status Error Counter Register */
24623       FR_CASERCR_16B_tag CASERCR;        /* offset: 0x0024 size: 16 bit */
24624   
24625       /* Channel B Status Error Counter Register */
24626       FR_CBSERCR_16B_tag CBSERCR;        /* offset: 0x0026 size: 16 bit */
24627   
24628       /* Protocol Status Register 0 */
24629       FR_PSR0_16B_tag PSR0;              /* offset: 0x0028 size: 16 bit */
24630   
24631       /* Protocol Status Register 1 */
24632       FR_PSR1_16B_tag PSR1;              /* offset: 0x002A size: 16 bit */
24633   
24634       /* Protocol Status Register 2 */
24635       FR_PSR2_16B_tag PSR2;              /* offset: 0x002C size: 16 bit */
24636   
24637       /* Protocol Status Register 3 */
24638       FR_PSR3_16B_tag PSR3;              /* offset: 0x002E size: 16 bit */
24639   
24640       /* Macrotick Counter Register */
24641       FR_MTCTR_16B_tag MTCTR;            /* offset: 0x0030 size: 16 bit */
24642   
24643       /* Cycle Counter Register */
24644       FR_CYCTR_16B_tag CYCTR;            /* offset: 0x0032 size: 16 bit */
24645   
24646       /* Slot Counter Channel A Register */
24647       FR_SLTCTAR_16B_tag SLTCTAR;        /* offset: 0x0034 size: 16 bit */
24648   
24649       /* Slot Counter Channel B Register */
24650       FR_SLTCTBR_16B_tag SLTCTBR;        /* offset: 0x0036 size: 16 bit */
24651   
24652       /* Rate Correction Value Register */
24653       FR_RTCORVR_16B_tag RTCORVR;        /* offset: 0x0038 size: 16 bit */
24654   
24655       /* Offset Correction Value Register */
24656       FR_OFCORVR_16B_tag OFCORVR;        /* offset: 0x003A size: 16 bit */
24657       union {
24658         /* Combined Interrupt Flag Register */
24659         FR_CIFR_16B_tag CIFR;            /* offset: 0x003C size: 16 bit */
24660         FR_CIFR_16B_tag CIFRR;           /* deprecated - please avoid */
24661       };
24662   
24663       /* System Memory Access Time-Out Register */
24664       FR_SYMATOR_16B_tag SYMATOR;        /* offset: 0x003E size: 16 bit */
24665   
24666       /* Sync Frame Counter Register */
24667       FR_SFCNTR_16B_tag SFCNTR;          /* offset: 0x0040 size: 16 bit */
24668   
24669       /* Sync Frame Table Offset Register */
24670       FR_SFTOR_16B_tag SFTOR;            /* offset: 0x0042 size: 16 bit */
24671   
24672       /* Sync Frame Table Configuration, Control, Status Register */
24673       FR_SFTCCSR_16B_tag SFTCCSR;        /* offset: 0x0044 size: 16 bit */
24674   
24675       /* Sync Frame ID Rejection Filter */
24676       FR_SFIDRFR_16B_tag SFIDRFR;        /* offset: 0x0046 size: 16 bit */
24677   
24678       /* Sync Frame ID Acceptance Filter Value Register */
24679       FR_SFIDAFVR_16B_tag SFIDAFVR;      /* offset: 0x0048 size: 16 bit */
24680   
24681       /* Sync Frame ID Acceptance Filter Mask Register */
24682       FR_SFIDAFMR_16B_tag SFIDAFMR;      /* offset: 0x004A size: 16 bit */
24683       union {
24684         FR_NMVR_16B_tag NMVR[6];         /* offset: 0x004C  (0x0002 x 6) */
24685         struct {
24686           /* Network Management Vector Register0 */
24687           FR_NMVR0_16B_tag NMVR0;        /* offset: 0x004C size: 16 bit */
24688   
24689           /* Network Management Vector Register1 */
24690           FR_NMVR1_16B_tag NMVR1;        /* offset: 0x004E size: 16 bit */
24691   
24692           /* Network Management Vector Register2 */
24693           FR_NMVR2_16B_tag NMVR2;        /* offset: 0x0050 size: 16 bit */
24694   
24695           /* Network Management Vector Register3 */
24696           FR_NMVR3_16B_tag NMVR3;        /* offset: 0x0052 size: 16 bit */
24697   
24698           /* Network Management Vector Register4 */
24699           FR_NMVR4_16B_tag NMVR4;        /* offset: 0x0054 size: 16 bit */
24700   
24701           /* Network Management Vector Register5 */
24702           FR_NMVR5_16B_tag NMVR5;        /* offset: 0x0056 size: 16 bit */
24703         };
24704       };
24705   
24706       /* Network Management Vector Length Register */
24707       FR_NMVLR_16B_tag NMVLR;            /* offset: 0x0058 size: 16 bit */
24708   
24709       /* Timer Configuration and Control Register */
24710       FR_TICCR_16B_tag TICCR;            /* offset: 0x005A size: 16 bit */
24711   
24712       /* Timer 1 Cycle Set Register */
24713       FR_TI1CYSR_16B_tag TI1CYSR;        /* offset: 0x005C size: 16 bit */
24714       union {
24715         /* Timer 1 Macrotick Offset Register */
24716         FR_TI1MTOR_16B_tag TI1MTOR;      /* offset: 0x005E size: 16 bit */
24717         FR_TI1MTOR_16B_tag T1MTOR;       /* deprecated - please avoid */
24718       };
24719   
24720       /* Timer 2 Configuration Register 0 */
24721       FR_TI2CR0_16B_tag TI2CR0;          /* offset: 0x0060 size: 16 bit */
24722   
24723       /* Timer 2 Configuration Register 1 */
24724       FR_TI2CR1_16B_tag TI2CR1;          /* offset: 0x0062 size: 16 bit */
24725   
24726       /* Slot Status Selection Register */
24727       FR_SSSR_16B_tag SSSR;              /* offset: 0x0064 size: 16 bit */
24728   
24729       /* Slot Status Counter Condition Register */
24730       FR_SSCCR_16B_tag SSCCR;            /* offset: 0x0066 size: 16 bit */
24731       union {
24732         FR_SSR_16B_tag SSR[8];           /* offset: 0x0068  (0x0002 x 8) */
24733         struct {
24734           /* Slot Status Register */
24735           FR_SSR_16B_tag SSR0;           /* offset: 0x0068 size: 16 bit */
24736   
24737           /* Slot Status Register */
24738           FR_SSR_16B_tag SSR1;           /* offset: 0x006A size: 16 bit */
24739   
24740           /* Slot Status Register */
24741           FR_SSR_16B_tag SSR2;           /* offset: 0x006C size: 16 bit */
24742   
24743           /* Slot Status Register */
24744           FR_SSR_16B_tag SSR3;           /* offset: 0x006E size: 16 bit */
24745   
24746           /* Slot Status Register */
24747           FR_SSR_16B_tag SSR4;           /* offset: 0x0070 size: 16 bit */
24748   
24749           /* Slot Status Register */
24750           FR_SSR_16B_tag SSR5;           /* offset: 0x0072 size: 16 bit */
24751   
24752           /* Slot Status Register */
24753           FR_SSR_16B_tag SSR6;           /* offset: 0x0074 size: 16 bit */
24754   
24755           /* Slot Status Register */
24756           FR_SSR_16B_tag SSR7;           /* offset: 0x0076 size: 16 bit */
24757         };
24758       };
24759   
24760       union {
24761         FR_SSCR_16B_tag SSCR[4];         /* offset: 0x0078  (0x0002 x 4) */
24762         struct {
24763           /* Slot Status Counter Register0 */
24764           FR_SSCR0_16B_tag SSCR0;        /* offset: 0x0078 size: 16 bit */
24765   
24766           /* Slot Status Counter Register1 */
24767           FR_SSCR1_16B_tag SSCR1;        /* offset: 0x007A size: 16 bit */
24768   
24769           /* Slot Status Counter Register2 */
24770           FR_SSCR2_16B_tag SSCR2;        /* offset: 0x007C size: 16 bit */
24771   
24772           /* Slot Status Counter Register3 */
24773           FR_SSCR3_16B_tag SSCR3;        /* offset: 0x007E size: 16 bit */
24774         };
24775       };
24776   
24777       /* MTS A Configuration Register */
24778       FR_MTSACFR_16B_tag MTSACFR;        /* offset: 0x0080 size: 16 bit */
24779   
24780       /* MTS B Configuration Register */
24781       FR_MTSBCFR_16B_tag MTSBCFR;        /* offset: 0x0082 size: 16 bit */
24782   
24783       /* Receive Shadow Buffer Index Register */
24784       FR_RSBIR_16B_tag RSBIR;            /* offset: 0x0084 size: 16 bit */
24785       union {
24786         /* Receive FIFO Watermark and Selection Register */
24787         FR_RFWMSR_16B_tag RFWMSR;        /* offset: 0x0086 size: 16 bit */
24788         FR_RFWMSR_16B_tag RFSR;          /* deprecated - please avoid */
24789       };
24790   
24791       union {
24792         /* Receive FIFO Start Index Register */
24793         FR_RF_RFSIR_16B_tag RF_RFSIR;    /* offset: 0x0088 size: 16 bit */
24794         FR_RF_RFSIR_16B_tag RFSIR;       /* deprecated - please avoid */
24795       };
24796   
24797       /* Receive FIFO Depth and Size Register */
24798       FR_RFDSR_16B_tag RFDSR;            /* offset: 0x008A size: 16 bit */
24799   
24800       /* Receive FIFO A Read Index Register */
24801       FR_RFARIR_16B_tag RFARIR;          /* offset: 0x008C size: 16 bit */
24802   
24803       /* Receive FIFO B Read Index Register */
24804       FR_RFBRIR_16B_tag RFBRIR;          /* offset: 0x008E size: 16 bit */
24805   
24806       /* Receive FIFO Message ID Acceptance Filter Value Register */
24807       FR_RFMIDAFVR_16B_tag RFMIDAFVR;    /* offset: 0x0090 size: 16 bit */
24808       union {
24809         /* Receive FIFO Message ID Acceptance Filter Mask Register */
24810         FR_RFMIDAFMR_16B_tag RFMIDAFMR;  /* offset: 0x0092 size: 16 bit */
24811         FR_RFMIDAFMR_16B_tag RFMIAFMR;   /* deprecated - please avoid */
24812       };
24813   
24814       /* Receive FIFO Frame ID Rejection Filter Value Register */
24815       FR_RFFIDRFVR_16B_tag RFFIDRFVR;    /* offset: 0x0094 size: 16 bit */
24816   
24817       /* Receive FIFO Frame ID Rejection Filter Mask Register */
24818       FR_RFFIDRFMR_16B_tag RFFIDRFMR;    /* offset: 0x0096 size: 16 bit */
24819   
24820       /* Receive FIFO Range Filter Configuration Register */
24821       FR_RFRFCFR_16B_tag RFRFCFR;        /* offset: 0x0098 size: 16 bit */
24822   
24823       /* Receive FIFO Range Filter Control Register */
24824       FR_RFRFCTR_16B_tag RFRFCTR;        /* offset: 0x009A size: 16 bit */
24825   
24826       /* Last Dynamic Transmit Slot Channel A Register */
24827       FR_LDTXSLAR_16B_tag LDTXSLAR;      /* offset: 0x009C size: 16 bit */
24828   
24829       /* Last Dynamic Transmit Slot Channel B Register */
24830       FR_LDTXSLBR_16B_tag LDTXSLBR;      /* offset: 0x009E size: 16 bit */
24831   
24832       /* Protocol Configuration Register 0 */
24833       FR_PCR0_16B_tag PCR0;              /* offset: 0x00A0 size: 16 bit */
24834   
24835       /* Protocol Configuration Register 1 */
24836       FR_PCR1_16B_tag PCR1;              /* offset: 0x00A2 size: 16 bit */
24837   
24838       /* Protocol Configuration Register 2 */
24839       FR_PCR2_16B_tag PCR2;              /* offset: 0x00A4 size: 16 bit */
24840   
24841       /* Protocol Configuration Register 3 */
24842       FR_PCR3_16B_tag PCR3;              /* offset: 0x00A6 size: 16 bit */
24843   
24844       /* Protocol Configuration Register 4 */
24845       FR_PCR4_16B_tag PCR4;              /* offset: 0x00A8 size: 16 bit */
24846   
24847       /* Protocol Configuration Register 5 */
24848       FR_PCR5_16B_tag PCR5;              /* offset: 0x00AA size: 16 bit */
24849   
24850       /* Protocol Configuration Register 6 */
24851       FR_PCR6_16B_tag PCR6;              /* offset: 0x00AC size: 16 bit */
24852   
24853       /* Protocol Configuration Register 7 */
24854       FR_PCR7_16B_tag PCR7;              /* offset: 0x00AE size: 16 bit */
24855   
24856       /* Protocol Configuration Register 8 */
24857       FR_PCR8_16B_tag PCR8;              /* offset: 0x00B0 size: 16 bit */
24858   
24859       /* Protocol Configuration Register 9 */
24860       FR_PCR9_16B_tag PCR9;              /* offset: 0x00B2 size: 16 bit */
24861   
24862       /* Protocol Configuration Register 10 */
24863       FR_PCR10_16B_tag PCR10;            /* offset: 0x00B4 size: 16 bit */
24864   
24865       /* Protocol Configuration Register 11 */
24866       FR_PCR11_16B_tag PCR11;            /* offset: 0x00B6 size: 16 bit */
24867   
24868       /* Protocol Configuration Register 12 */
24869       FR_PCR12_16B_tag PCR12;            /* offset: 0x00B8 size: 16 bit */
24870   
24871       /* Protocol Configuration Register 13 */
24872       FR_PCR13_16B_tag PCR13;            /* offset: 0x00BA size: 16 bit */
24873   
24874       /* Protocol Configuration Register 14 */
24875       FR_PCR14_16B_tag PCR14;            /* offset: 0x00BC size: 16 bit */
24876   
24877       /* Protocol Configuration Register 15 */
24878       FR_PCR15_16B_tag PCR15;            /* offset: 0x00BE size: 16 bit */
24879   
24880       /* Protocol Configuration Register 16 */
24881       FR_PCR16_16B_tag PCR16;            /* offset: 0x00C0 size: 16 bit */
24882   
24883       /* Protocol Configuration Register 17 */
24884       FR_PCR17_16B_tag PCR17;            /* offset: 0x00C2 size: 16 bit */
24885   
24886       /* Protocol Configuration Register 18 */
24887       FR_PCR18_16B_tag PCR18;            /* offset: 0x00C4 size: 16 bit */
24888   
24889       /* Protocol Configuration Register 19 */
24890       FR_PCR19_16B_tag PCR19;            /* offset: 0x00C6 size: 16 bit */
24891   
24892       /* Protocol Configuration Register 20 */
24893       FR_PCR20_16B_tag PCR20;            /* offset: 0x00C8 size: 16 bit */
24894   
24895       /* Protocol Configuration Register 21 */
24896       FR_PCR21_16B_tag PCR21;            /* offset: 0x00CA size: 16 bit */
24897   
24898       /* Protocol Configuration Register 22 */
24899       FR_PCR22_16B_tag PCR22;            /* offset: 0x00CC size: 16 bit */
24900   
24901       /* Protocol Configuration Register 23 */
24902       FR_PCR23_16B_tag PCR23;            /* offset: 0x00CE size: 16 bit */
24903   
24904       /* Protocol Configuration Register 24 */
24905       FR_PCR24_16B_tag PCR24;            /* offset: 0x00D0 size: 16 bit */
24906   
24907       /* Protocol Configuration Register 25 */
24908       FR_PCR25_16B_tag PCR25;            /* offset: 0x00D2 size: 16 bit */
24909   
24910       /* Protocol Configuration Register 26 */
24911       FR_PCR26_16B_tag PCR26;            /* offset: 0x00D4 size: 16 bit */
24912   
24913       /* Protocol Configuration Register 27 */
24914       FR_PCR27_16B_tag PCR27;            /* offset: 0x00D6 size: 16 bit */
24915   
24916       /* Protocol Configuration Register 28 */
24917       FR_PCR28_16B_tag PCR28;            /* offset: 0x00D8 size: 16 bit */
24918   
24919       /* Protocol Configuration Register 29 */
24920       FR_PCR29_16B_tag PCR29;            /* offset: 0x00DA size: 16 bit */
24921   
24922       /* Protocol Configuration Register 30 */
24923       FR_PCR30_16B_tag PCR30;            /* offset: 0x00DC size: 16 bit */
24924       int8_t FR_reserved_00DE[10];
24925   
24926       /* Receive FIFO System Memory Base Address High Register */
24927       FR_RFSYMBHADR_16B_tag RFSYMBHADR;  /* offset: 0x00E8 size: 16 bit */
24928   
24929       /* Receive FIFO System Memory Base Address Low Register */
24930       FR_RFSYMBLADR_16B_tag RFSYMBLADR;  /* offset: 0x00EA size: 16 bit */
24931   
24932       /* Receive FIFO Periodic Timer Register */
24933       FR_RFPTR_16B_tag RFPTR;            /* offset: 0x00EC size: 16 bit */
24934   
24935       /* Receive FIFO Fill Level and Pop Count Register */
24936       FR_RFFLPCR_16B_tag RFFLPCR;        /* offset: 0x00EE size: 16 bit */
24937   
24938       /* ECC Error Interrupt Flag and Enable Register */
24939       FR_EEIFER_16B_tag EEIFER;          /* offset: 0x00F0 size: 16 bit */
24940   
24941       /* ECC Error Report and Injection Control Register */
24942       FR_EERICR_16B_tag EERICR;          /* offset: 0x00F2 size: 16 bit */
24943   
24944       /* ECC Error Report Adress Register */
24945       FR_EERAR_16B_tag EERAR;            /* offset: 0x00F4 size: 16 bit */
24946   
24947       /* ECC Error Report Data Register */
24948       FR_EERDR_16B_tag EERDR;            /* offset: 0x00F6 size: 16 bit */
24949   
24950       /* ECC Error Report Code Register */
24951       FR_EERCR_16B_tag EERCR;            /* offset: 0x00F8 size: 16 bit */
24952   
24953       /* ECC Error Injection Address Register */
24954       FR_EEIAR_16B_tag EEIAR;            /* offset: 0x00FA size: 16 bit */
24955   
24956       /* ECC Error Injection Data Register */
24957       FR_EEIDR_16B_tag EEIDR;            /* offset: 0x00FC size: 16 bit */
24958   
24959       /* ECC Error Injection Code Register */
24960       FR_EEICR_16B_tag EEICR;            /* offset: 0x00FE size: 16 bit */
24961       union {
24962         /*  Register set MB */
24963         FR_MB_tag MB[64];                /* offset: 0x0100  (0x0008 x 64) */
24964   
24965         /*  Alias name for MB */
24966         FR_MB_tag MBCCS[64];             /* deprecated - please avoid */
24967         struct {
24968           /* Message Buffer Configuration Control Status Register */
24969           FR_MBCCSR_16B_tag MBCCSR0;     /* offset: 0x0100 size: 16 bit */
24970   
24971           /* Message Buffer Cycle Counter Filter Register */
24972           FR_MBCCFR_16B_tag MBCCFR0;     /* offset: 0x0102 size: 16 bit */
24973   
24974           /* Message Buffer Frame ID Register */
24975           FR_MBFIDR_16B_tag MBFIDR0;     /* offset: 0x0104 size: 16 bit */
24976   
24977           /* Message Buffer Index Register */
24978           FR_MBIDXR_16B_tag MBIDXR0;     /* offset: 0x0106 size: 16 bit */
24979   
24980           /* Message Buffer Configuration Control Status Register */
24981           FR_MBCCSR_16B_tag MBCCSR1;     /* offset: 0x0108 size: 16 bit */
24982   
24983           /* Message Buffer Cycle Counter Filter Register */
24984           FR_MBCCFR_16B_tag MBCCFR1;     /* offset: 0x010A size: 16 bit */
24985   
24986           /* Message Buffer Frame ID Register */
24987           FR_MBFIDR_16B_tag MBFIDR1;     /* offset: 0x010C size: 16 bit */
24988   
24989           /* Message Buffer Index Register */
24990           FR_MBIDXR_16B_tag MBIDXR1;     /* offset: 0x010E size: 16 bit */
24991   
24992           /* Message Buffer Configuration Control Status Register */
24993           FR_MBCCSR_16B_tag MBCCSR2;     /* offset: 0x0110 size: 16 bit */
24994   
24995           /* Message Buffer Cycle Counter Filter Register */
24996           FR_MBCCFR_16B_tag MBCCFR2;     /* offset: 0x0112 size: 16 bit */
24997   
24998           /* Message Buffer Frame ID Register */
24999           FR_MBFIDR_16B_tag MBFIDR2;     /* offset: 0x0114 size: 16 bit */
25000   
25001           /* Message Buffer Index Register */
25002           FR_MBIDXR_16B_tag MBIDXR2;     /* offset: 0x0116 size: 16 bit */
25003   
25004           /* Message Buffer Configuration Control Status Register */
25005           FR_MBCCSR_16B_tag MBCCSR3;     /* offset: 0x0118 size: 16 bit */
25006   
25007           /* Message Buffer Cycle Counter Filter Register */
25008           FR_MBCCFR_16B_tag MBCCFR3;     /* offset: 0x011A size: 16 bit */
25009   
25010           /* Message Buffer Frame ID Register */
25011           FR_MBFIDR_16B_tag MBFIDR3;     /* offset: 0x011C size: 16 bit */
25012   
25013           /* Message Buffer Index Register */
25014           FR_MBIDXR_16B_tag MBIDXR3;     /* offset: 0x011E size: 16 bit */
25015   
25016           /* Message Buffer Configuration Control Status Register */
25017           FR_MBCCSR_16B_tag MBCCSR4;     /* offset: 0x0120 size: 16 bit */
25018   
25019           /* Message Buffer Cycle Counter Filter Register */
25020           FR_MBCCFR_16B_tag MBCCFR4;     /* offset: 0x0122 size: 16 bit */
25021   
25022           /* Message Buffer Frame ID Register */
25023           FR_MBFIDR_16B_tag MBFIDR4;     /* offset: 0x0124 size: 16 bit */
25024   
25025           /* Message Buffer Index Register */
25026           FR_MBIDXR_16B_tag MBIDXR4;     /* offset: 0x0126 size: 16 bit */
25027   
25028           /* Message Buffer Configuration Control Status Register */
25029           FR_MBCCSR_16B_tag MBCCSR5;     /* offset: 0x0128 size: 16 bit */
25030   
25031           /* Message Buffer Cycle Counter Filter Register */
25032           FR_MBCCFR_16B_tag MBCCFR5;     /* offset: 0x012A size: 16 bit */
25033   
25034           /* Message Buffer Frame ID Register */
25035           FR_MBFIDR_16B_tag MBFIDR5;     /* offset: 0x012C size: 16 bit */
25036   
25037           /* Message Buffer Index Register */
25038           FR_MBIDXR_16B_tag MBIDXR5;     /* offset: 0x012E size: 16 bit */
25039   
25040           /* Message Buffer Configuration Control Status Register */
25041           FR_MBCCSR_16B_tag MBCCSR6;     /* offset: 0x0130 size: 16 bit */
25042   
25043           /* Message Buffer Cycle Counter Filter Register */
25044           FR_MBCCFR_16B_tag MBCCFR6;     /* offset: 0x0132 size: 16 bit */
25045   
25046           /* Message Buffer Frame ID Register */
25047           FR_MBFIDR_16B_tag MBFIDR6;     /* offset: 0x0134 size: 16 bit */
25048   
25049           /* Message Buffer Index Register */
25050           FR_MBIDXR_16B_tag MBIDXR6;     /* offset: 0x0136 size: 16 bit */
25051   
25052           /* Message Buffer Configuration Control Status Register */
25053           FR_MBCCSR_16B_tag MBCCSR7;     /* offset: 0x0138 size: 16 bit */
25054   
25055           /* Message Buffer Cycle Counter Filter Register */
25056           FR_MBCCFR_16B_tag MBCCFR7;     /* offset: 0x013A size: 16 bit */
25057   
25058           /* Message Buffer Frame ID Register */
25059           FR_MBFIDR_16B_tag MBFIDR7;     /* offset: 0x013C size: 16 bit */
25060   
25061           /* Message Buffer Index Register */
25062           FR_MBIDXR_16B_tag MBIDXR7;     /* offset: 0x013E size: 16 bit */
25063   
25064           /* Message Buffer Configuration Control Status Register */
25065           FR_MBCCSR_16B_tag MBCCSR8;     /* offset: 0x0140 size: 16 bit */
25066   
25067           /* Message Buffer Cycle Counter Filter Register */
25068           FR_MBCCFR_16B_tag MBCCFR8;     /* offset: 0x0142 size: 16 bit */
25069   
25070           /* Message Buffer Frame ID Register */
25071           FR_MBFIDR_16B_tag MBFIDR8;     /* offset: 0x0144 size: 16 bit */
25072   
25073           /* Message Buffer Index Register */
25074           FR_MBIDXR_16B_tag MBIDXR8;     /* offset: 0x0146 size: 16 bit */
25075   
25076           /* Message Buffer Configuration Control Status Register */
25077           FR_MBCCSR_16B_tag MBCCSR9;     /* offset: 0x0148 size: 16 bit */
25078   
25079           /* Message Buffer Cycle Counter Filter Register */
25080           FR_MBCCFR_16B_tag MBCCFR9;     /* offset: 0x014A size: 16 bit */
25081   
25082           /* Message Buffer Frame ID Register */
25083           FR_MBFIDR_16B_tag MBFIDR9;     /* offset: 0x014C size: 16 bit */
25084   
25085           /* Message Buffer Index Register */
25086           FR_MBIDXR_16B_tag MBIDXR9;     /* offset: 0x014E size: 16 bit */
25087   
25088           /* Message Buffer Configuration Control Status Register */
25089           FR_MBCCSR_16B_tag MBCCSR10;    /* offset: 0x0150 size: 16 bit */
25090   
25091           /* Message Buffer Cycle Counter Filter Register */
25092           FR_MBCCFR_16B_tag MBCCFR10;    /* offset: 0x0152 size: 16 bit */
25093   
25094           /* Message Buffer Frame ID Register */
25095           FR_MBFIDR_16B_tag MBFIDR10;    /* offset: 0x0154 size: 16 bit */
25096   
25097           /* Message Buffer Index Register */
25098           FR_MBIDXR_16B_tag MBIDXR10;    /* offset: 0x0156 size: 16 bit */
25099   
25100           /* Message Buffer Configuration Control Status Register */
25101           FR_MBCCSR_16B_tag MBCCSR11;    /* offset: 0x0158 size: 16 bit */
25102   
25103           /* Message Buffer Cycle Counter Filter Register */
25104           FR_MBCCFR_16B_tag MBCCFR11;    /* offset: 0x015A size: 16 bit */
25105   
25106           /* Message Buffer Frame ID Register */
25107           FR_MBFIDR_16B_tag MBFIDR11;    /* offset: 0x015C size: 16 bit */
25108   
25109           /* Message Buffer Index Register */
25110           FR_MBIDXR_16B_tag MBIDXR11;    /* offset: 0x015E size: 16 bit */
25111   
25112           /* Message Buffer Configuration Control Status Register */
25113           FR_MBCCSR_16B_tag MBCCSR12;    /* offset: 0x0160 size: 16 bit */
25114   
25115           /* Message Buffer Cycle Counter Filter Register */
25116           FR_MBCCFR_16B_tag MBCCFR12;    /* offset: 0x0162 size: 16 bit */
25117   
25118           /* Message Buffer Frame ID Register */
25119           FR_MBFIDR_16B_tag MBFIDR12;    /* offset: 0x0164 size: 16 bit */
25120   
25121           /* Message Buffer Index Register */
25122           FR_MBIDXR_16B_tag MBIDXR12;    /* offset: 0x0166 size: 16 bit */
25123   
25124           /* Message Buffer Configuration Control Status Register */
25125           FR_MBCCSR_16B_tag MBCCSR13;    /* offset: 0x0168 size: 16 bit */
25126   
25127           /* Message Buffer Cycle Counter Filter Register */
25128           FR_MBCCFR_16B_tag MBCCFR13;    /* offset: 0x016A size: 16 bit */
25129   
25130           /* Message Buffer Frame ID Register */
25131           FR_MBFIDR_16B_tag MBFIDR13;    /* offset: 0x016C size: 16 bit */
25132   
25133           /* Message Buffer Index Register */
25134           FR_MBIDXR_16B_tag MBIDXR13;    /* offset: 0x016E size: 16 bit */
25135   
25136           /* Message Buffer Configuration Control Status Register */
25137           FR_MBCCSR_16B_tag MBCCSR14;    /* offset: 0x0170 size: 16 bit */
25138   
25139           /* Message Buffer Cycle Counter Filter Register */
25140           FR_MBCCFR_16B_tag MBCCFR14;    /* offset: 0x0172 size: 16 bit */
25141   
25142           /* Message Buffer Frame ID Register */
25143           FR_MBFIDR_16B_tag MBFIDR14;    /* offset: 0x0174 size: 16 bit */
25144   
25145           /* Message Buffer Index Register */
25146           FR_MBIDXR_16B_tag MBIDXR14;    /* offset: 0x0176 size: 16 bit */
25147   
25148           /* Message Buffer Configuration Control Status Register */
25149           FR_MBCCSR_16B_tag MBCCSR15;    /* offset: 0x0178 size: 16 bit */
25150   
25151           /* Message Buffer Cycle Counter Filter Register */
25152           FR_MBCCFR_16B_tag MBCCFR15;    /* offset: 0x017A size: 16 bit */
25153   
25154           /* Message Buffer Frame ID Register */
25155           FR_MBFIDR_16B_tag MBFIDR15;    /* offset: 0x017C size: 16 bit */
25156   
25157           /* Message Buffer Index Register */
25158           FR_MBIDXR_16B_tag MBIDXR15;    /* offset: 0x017E size: 16 bit */
25159   
25160           /* Message Buffer Configuration Control Status Register */
25161           FR_MBCCSR_16B_tag MBCCSR16;    /* offset: 0x0180 size: 16 bit */
25162   
25163           /* Message Buffer Cycle Counter Filter Register */
25164           FR_MBCCFR_16B_tag MBCCFR16;    /* offset: 0x0182 size: 16 bit */
25165   
25166           /* Message Buffer Frame ID Register */
25167           FR_MBFIDR_16B_tag MBFIDR16;    /* offset: 0x0184 size: 16 bit */
25168   
25169           /* Message Buffer Index Register */
25170           FR_MBIDXR_16B_tag MBIDXR16;    /* offset: 0x0186 size: 16 bit */
25171   
25172           /* Message Buffer Configuration Control Status Register */
25173           FR_MBCCSR_16B_tag MBCCSR17;    /* offset: 0x0188 size: 16 bit */
25174   
25175           /* Message Buffer Cycle Counter Filter Register */
25176           FR_MBCCFR_16B_tag MBCCFR17;    /* offset: 0x018A size: 16 bit */
25177   
25178           /* Message Buffer Frame ID Register */
25179           FR_MBFIDR_16B_tag MBFIDR17;    /* offset: 0x018C size: 16 bit */
25180   
25181           /* Message Buffer Index Register */
25182           FR_MBIDXR_16B_tag MBIDXR17;    /* offset: 0x018E size: 16 bit */
25183   
25184           /* Message Buffer Configuration Control Status Register */
25185           FR_MBCCSR_16B_tag MBCCSR18;    /* offset: 0x0190 size: 16 bit */
25186   
25187           /* Message Buffer Cycle Counter Filter Register */
25188           FR_MBCCFR_16B_tag MBCCFR18;    /* offset: 0x0192 size: 16 bit */
25189   
25190           /* Message Buffer Frame ID Register */
25191           FR_MBFIDR_16B_tag MBFIDR18;    /* offset: 0x0194 size: 16 bit */
25192   
25193           /* Message Buffer Index Register */
25194           FR_MBIDXR_16B_tag MBIDXR18;    /* offset: 0x0196 size: 16 bit */
25195   
25196           /* Message Buffer Configuration Control Status Register */
25197           FR_MBCCSR_16B_tag MBCCSR19;    /* offset: 0x0198 size: 16 bit */
25198   
25199           /* Message Buffer Cycle Counter Filter Register */
25200           FR_MBCCFR_16B_tag MBCCFR19;    /* offset: 0x019A size: 16 bit */
25201   
25202           /* Message Buffer Frame ID Register */
25203           FR_MBFIDR_16B_tag MBFIDR19;    /* offset: 0x019C size: 16 bit */
25204   
25205           /* Message Buffer Index Register */
25206           FR_MBIDXR_16B_tag MBIDXR19;    /* offset: 0x019E size: 16 bit */
25207   
25208           /* Message Buffer Configuration Control Status Register */
25209           FR_MBCCSR_16B_tag MBCCSR20;    /* offset: 0x01A0 size: 16 bit */
25210   
25211           /* Message Buffer Cycle Counter Filter Register */
25212           FR_MBCCFR_16B_tag MBCCFR20;    /* offset: 0x01A2 size: 16 bit */
25213   
25214           /* Message Buffer Frame ID Register */
25215           FR_MBFIDR_16B_tag MBFIDR20;    /* offset: 0x01A4 size: 16 bit */
25216   
25217           /* Message Buffer Index Register */
25218           FR_MBIDXR_16B_tag MBIDXR20;    /* offset: 0x01A6 size: 16 bit */
25219   
25220           /* Message Buffer Configuration Control Status Register */
25221           FR_MBCCSR_16B_tag MBCCSR21;    /* offset: 0x01A8 size: 16 bit */
25222   
25223           /* Message Buffer Cycle Counter Filter Register */
25224           FR_MBCCFR_16B_tag MBCCFR21;    /* offset: 0x01AA size: 16 bit */
25225   
25226           /* Message Buffer Frame ID Register */
25227           FR_MBFIDR_16B_tag MBFIDR21;    /* offset: 0x01AC size: 16 bit */
25228   
25229           /* Message Buffer Index Register */
25230           FR_MBIDXR_16B_tag MBIDXR21;    /* offset: 0x01AE size: 16 bit */
25231   
25232           /* Message Buffer Configuration Control Status Register */
25233           FR_MBCCSR_16B_tag MBCCSR22;    /* offset: 0x01B0 size: 16 bit */
25234   
25235           /* Message Buffer Cycle Counter Filter Register */
25236           FR_MBCCFR_16B_tag MBCCFR22;    /* offset: 0x01B2 size: 16 bit */
25237   
25238           /* Message Buffer Frame ID Register */
25239           FR_MBFIDR_16B_tag MBFIDR22;    /* offset: 0x01B4 size: 16 bit */
25240   
25241           /* Message Buffer Index Register */
25242           FR_MBIDXR_16B_tag MBIDXR22;    /* offset: 0x01B6 size: 16 bit */
25243   
25244           /* Message Buffer Configuration Control Status Register */
25245           FR_MBCCSR_16B_tag MBCCSR23;    /* offset: 0x01B8 size: 16 bit */
25246   
25247           /* Message Buffer Cycle Counter Filter Register */
25248           FR_MBCCFR_16B_tag MBCCFR23;    /* offset: 0x01BA size: 16 bit */
25249   
25250           /* Message Buffer Frame ID Register */
25251           FR_MBFIDR_16B_tag MBFIDR23;    /* offset: 0x01BC size: 16 bit */
25252   
25253           /* Message Buffer Index Register */
25254           FR_MBIDXR_16B_tag MBIDXR23;    /* offset: 0x01BE size: 16 bit */
25255   
25256           /* Message Buffer Configuration Control Status Register */
25257           FR_MBCCSR_16B_tag MBCCSR24;    /* offset: 0x01C0 size: 16 bit */
25258   
25259           /* Message Buffer Cycle Counter Filter Register */
25260           FR_MBCCFR_16B_tag MBCCFR24;    /* offset: 0x01C2 size: 16 bit */
25261   
25262           /* Message Buffer Frame ID Register */
25263           FR_MBFIDR_16B_tag MBFIDR24;    /* offset: 0x01C4 size: 16 bit */
25264   
25265           /* Message Buffer Index Register */
25266           FR_MBIDXR_16B_tag MBIDXR24;    /* offset: 0x01C6 size: 16 bit */
25267   
25268           /* Message Buffer Configuration Control Status Register */
25269           FR_MBCCSR_16B_tag MBCCSR25;    /* offset: 0x01C8 size: 16 bit */
25270   
25271           /* Message Buffer Cycle Counter Filter Register */
25272           FR_MBCCFR_16B_tag MBCCFR25;    /* offset: 0x01CA size: 16 bit */
25273   
25274           /* Message Buffer Frame ID Register */
25275           FR_MBFIDR_16B_tag MBFIDR25;    /* offset: 0x01CC size: 16 bit */
25276   
25277           /* Message Buffer Index Register */
25278           FR_MBIDXR_16B_tag MBIDXR25;    /* offset: 0x01CE size: 16 bit */
25279   
25280           /* Message Buffer Configuration Control Status Register */
25281           FR_MBCCSR_16B_tag MBCCSR26;    /* offset: 0x01D0 size: 16 bit */
25282   
25283           /* Message Buffer Cycle Counter Filter Register */
25284           FR_MBCCFR_16B_tag MBCCFR26;    /* offset: 0x01D2 size: 16 bit */
25285   
25286           /* Message Buffer Frame ID Register */
25287           FR_MBFIDR_16B_tag MBFIDR26;    /* offset: 0x01D4 size: 16 bit */
25288   
25289           /* Message Buffer Index Register */
25290           FR_MBIDXR_16B_tag MBIDXR26;    /* offset: 0x01D6 size: 16 bit */
25291   
25292           /* Message Buffer Configuration Control Status Register */
25293           FR_MBCCSR_16B_tag MBCCSR27;    /* offset: 0x01D8 size: 16 bit */
25294   
25295           /* Message Buffer Cycle Counter Filter Register */
25296           FR_MBCCFR_16B_tag MBCCFR27;    /* offset: 0x01DA size: 16 bit */
25297   
25298           /* Message Buffer Frame ID Register */
25299           FR_MBFIDR_16B_tag MBFIDR27;    /* offset: 0x01DC size: 16 bit */
25300   
25301           /* Message Buffer Index Register */
25302           FR_MBIDXR_16B_tag MBIDXR27;    /* offset: 0x01DE size: 16 bit */
25303   
25304           /* Message Buffer Configuration Control Status Register */
25305           FR_MBCCSR_16B_tag MBCCSR28;    /* offset: 0x01E0 size: 16 bit */
25306   
25307           /* Message Buffer Cycle Counter Filter Register */
25308           FR_MBCCFR_16B_tag MBCCFR28;    /* offset: 0x01E2 size: 16 bit */
25309   
25310           /* Message Buffer Frame ID Register */
25311           FR_MBFIDR_16B_tag MBFIDR28;    /* offset: 0x01E4 size: 16 bit */
25312   
25313           /* Message Buffer Index Register */
25314           FR_MBIDXR_16B_tag MBIDXR28;    /* offset: 0x01E6 size: 16 bit */
25315   
25316           /* Message Buffer Configuration Control Status Register */
25317           FR_MBCCSR_16B_tag MBCCSR29;    /* offset: 0x01E8 size: 16 bit */
25318   
25319           /* Message Buffer Cycle Counter Filter Register */
25320           FR_MBCCFR_16B_tag MBCCFR29;    /* offset: 0x01EA size: 16 bit */
25321   
25322           /* Message Buffer Frame ID Register */
25323           FR_MBFIDR_16B_tag MBFIDR29;    /* offset: 0x01EC size: 16 bit */
25324   
25325           /* Message Buffer Index Register */
25326           FR_MBIDXR_16B_tag MBIDXR29;    /* offset: 0x01EE size: 16 bit */
25327   
25328           /* Message Buffer Configuration Control Status Register */
25329           FR_MBCCSR_16B_tag MBCCSR30;    /* offset: 0x01F0 size: 16 bit */
25330   
25331           /* Message Buffer Cycle Counter Filter Register */
25332           FR_MBCCFR_16B_tag MBCCFR30;    /* offset: 0x01F2 size: 16 bit */
25333   
25334           /* Message Buffer Frame ID Register */
25335           FR_MBFIDR_16B_tag MBFIDR30;    /* offset: 0x01F4 size: 16 bit */
25336   
25337           /* Message Buffer Index Register */
25338           FR_MBIDXR_16B_tag MBIDXR30;    /* offset: 0x01F6 size: 16 bit */
25339   
25340           /* Message Buffer Configuration Control Status Register */
25341           FR_MBCCSR_16B_tag MBCCSR31;    /* offset: 0x01F8 size: 16 bit */
25342   
25343           /* Message Buffer Cycle Counter Filter Register */
25344           FR_MBCCFR_16B_tag MBCCFR31;    /* offset: 0x01FA size: 16 bit */
25345   
25346           /* Message Buffer Frame ID Register */
25347           FR_MBFIDR_16B_tag MBFIDR31;    /* offset: 0x01FC size: 16 bit */
25348   
25349           /* Message Buffer Index Register */
25350           FR_MBIDXR_16B_tag MBIDXR31;    /* offset: 0x01FE size: 16 bit */
25351   
25352           /* Message Buffer Configuration Control Status Register */
25353           FR_MBCCSR_16B_tag MBCCSR32;    /* offset: 0x0200 size: 16 bit */
25354   
25355           /* Message Buffer Cycle Counter Filter Register */
25356           FR_MBCCFR_16B_tag MBCCFR32;    /* offset: 0x0202 size: 16 bit */
25357   
25358           /* Message Buffer Frame ID Register */
25359           FR_MBFIDR_16B_tag MBFIDR32;    /* offset: 0x0204 size: 16 bit */
25360   
25361           /* Message Buffer Index Register */
25362           FR_MBIDXR_16B_tag MBIDXR32;    /* offset: 0x0206 size: 16 bit */
25363   
25364           /* Message Buffer Configuration Control Status Register */
25365           FR_MBCCSR_16B_tag MBCCSR33;    /* offset: 0x0208 size: 16 bit */
25366   
25367           /* Message Buffer Cycle Counter Filter Register */
25368           FR_MBCCFR_16B_tag MBCCFR33;    /* offset: 0x020A size: 16 bit */
25369   
25370           /* Message Buffer Frame ID Register */
25371           FR_MBFIDR_16B_tag MBFIDR33;    /* offset: 0x020C size: 16 bit */
25372   
25373           /* Message Buffer Index Register */
25374           FR_MBIDXR_16B_tag MBIDXR33;    /* offset: 0x020E size: 16 bit */
25375   
25376           /* Message Buffer Configuration Control Status Register */
25377           FR_MBCCSR_16B_tag MBCCSR34;    /* offset: 0x0210 size: 16 bit */
25378   
25379           /* Message Buffer Cycle Counter Filter Register */
25380           FR_MBCCFR_16B_tag MBCCFR34;    /* offset: 0x0212 size: 16 bit */
25381   
25382           /* Message Buffer Frame ID Register */
25383           FR_MBFIDR_16B_tag MBFIDR34;    /* offset: 0x0214 size: 16 bit */
25384   
25385           /* Message Buffer Index Register */
25386           FR_MBIDXR_16B_tag MBIDXR34;    /* offset: 0x0216 size: 16 bit */
25387   
25388           /* Message Buffer Configuration Control Status Register */
25389           FR_MBCCSR_16B_tag MBCCSR35;    /* offset: 0x0218 size: 16 bit */
25390   
25391           /* Message Buffer Cycle Counter Filter Register */
25392           FR_MBCCFR_16B_tag MBCCFR35;    /* offset: 0x021A size: 16 bit */
25393   
25394           /* Message Buffer Frame ID Register */
25395           FR_MBFIDR_16B_tag MBFIDR35;    /* offset: 0x021C size: 16 bit */
25396   
25397           /* Message Buffer Index Register */
25398           FR_MBIDXR_16B_tag MBIDXR35;    /* offset: 0x021E size: 16 bit */
25399   
25400           /* Message Buffer Configuration Control Status Register */
25401           FR_MBCCSR_16B_tag MBCCSR36;    /* offset: 0x0220 size: 16 bit */
25402   
25403           /* Message Buffer Cycle Counter Filter Register */
25404           FR_MBCCFR_16B_tag MBCCFR36;    /* offset: 0x0222 size: 16 bit */
25405   
25406           /* Message Buffer Frame ID Register */
25407           FR_MBFIDR_16B_tag MBFIDR36;    /* offset: 0x0224 size: 16 bit */
25408   
25409           /* Message Buffer Index Register */
25410           FR_MBIDXR_16B_tag MBIDXR36;    /* offset: 0x0226 size: 16 bit */
25411   
25412           /* Message Buffer Configuration Control Status Register */
25413           FR_MBCCSR_16B_tag MBCCSR37;    /* offset: 0x0228 size: 16 bit */
25414   
25415           /* Message Buffer Cycle Counter Filter Register */
25416           FR_MBCCFR_16B_tag MBCCFR37;    /* offset: 0x022A size: 16 bit */
25417   
25418           /* Message Buffer Frame ID Register */
25419           FR_MBFIDR_16B_tag MBFIDR37;    /* offset: 0x022C size: 16 bit */
25420   
25421           /* Message Buffer Index Register */
25422           FR_MBIDXR_16B_tag MBIDXR37;    /* offset: 0x022E size: 16 bit */
25423   
25424           /* Message Buffer Configuration Control Status Register */
25425           FR_MBCCSR_16B_tag MBCCSR38;    /* offset: 0x0230 size: 16 bit */
25426   
25427           /* Message Buffer Cycle Counter Filter Register */
25428           FR_MBCCFR_16B_tag MBCCFR38;    /* offset: 0x0232 size: 16 bit */
25429   
25430           /* Message Buffer Frame ID Register */
25431           FR_MBFIDR_16B_tag MBFIDR38;    /* offset: 0x0234 size: 16 bit */
25432   
25433           /* Message Buffer Index Register */
25434           FR_MBIDXR_16B_tag MBIDXR38;    /* offset: 0x0236 size: 16 bit */
25435   
25436           /* Message Buffer Configuration Control Status Register */
25437           FR_MBCCSR_16B_tag MBCCSR39;    /* offset: 0x0238 size: 16 bit */
25438   
25439           /* Message Buffer Cycle Counter Filter Register */
25440           FR_MBCCFR_16B_tag MBCCFR39;    /* offset: 0x023A size: 16 bit */
25441   
25442           /* Message Buffer Frame ID Register */
25443           FR_MBFIDR_16B_tag MBFIDR39;    /* offset: 0x023C size: 16 bit */
25444   
25445           /* Message Buffer Index Register */
25446           FR_MBIDXR_16B_tag MBIDXR39;    /* offset: 0x023E size: 16 bit */
25447   
25448           /* Message Buffer Configuration Control Status Register */
25449           FR_MBCCSR_16B_tag MBCCSR40;    /* offset: 0x0240 size: 16 bit */
25450   
25451           /* Message Buffer Cycle Counter Filter Register */
25452           FR_MBCCFR_16B_tag MBCCFR40;    /* offset: 0x0242 size: 16 bit */
25453   
25454           /* Message Buffer Frame ID Register */
25455           FR_MBFIDR_16B_tag MBFIDR40;    /* offset: 0x0244 size: 16 bit */
25456   
25457           /* Message Buffer Index Register */
25458           FR_MBIDXR_16B_tag MBIDXR40;    /* offset: 0x0246 size: 16 bit */
25459   
25460           /* Message Buffer Configuration Control Status Register */
25461           FR_MBCCSR_16B_tag MBCCSR41;    /* offset: 0x0248 size: 16 bit */
25462   
25463           /* Message Buffer Cycle Counter Filter Register */
25464           FR_MBCCFR_16B_tag MBCCFR41;    /* offset: 0x024A size: 16 bit */
25465   
25466           /* Message Buffer Frame ID Register */
25467           FR_MBFIDR_16B_tag MBFIDR41;    /* offset: 0x024C size: 16 bit */
25468   
25469           /* Message Buffer Index Register */
25470           FR_MBIDXR_16B_tag MBIDXR41;    /* offset: 0x024E size: 16 bit */
25471   
25472           /* Message Buffer Configuration Control Status Register */
25473           FR_MBCCSR_16B_tag MBCCSR42;    /* offset: 0x0250 size: 16 bit */
25474   
25475           /* Message Buffer Cycle Counter Filter Register */
25476           FR_MBCCFR_16B_tag MBCCFR42;    /* offset: 0x0252 size: 16 bit */
25477   
25478           /* Message Buffer Frame ID Register */
25479           FR_MBFIDR_16B_tag MBFIDR42;    /* offset: 0x0254 size: 16 bit */
25480   
25481           /* Message Buffer Index Register */
25482           FR_MBIDXR_16B_tag MBIDXR42;    /* offset: 0x0256 size: 16 bit */
25483   
25484           /* Message Buffer Configuration Control Status Register */
25485           FR_MBCCSR_16B_tag MBCCSR43;    /* offset: 0x0258 size: 16 bit */
25486   
25487           /* Message Buffer Cycle Counter Filter Register */
25488           FR_MBCCFR_16B_tag MBCCFR43;    /* offset: 0x025A size: 16 bit */
25489   
25490           /* Message Buffer Frame ID Register */
25491           FR_MBFIDR_16B_tag MBFIDR43;    /* offset: 0x025C size: 16 bit */
25492   
25493           /* Message Buffer Index Register */
25494           FR_MBIDXR_16B_tag MBIDXR43;    /* offset: 0x025E size: 16 bit */
25495   
25496           /* Message Buffer Configuration Control Status Register */
25497           FR_MBCCSR_16B_tag MBCCSR44;    /* offset: 0x0260 size: 16 bit */
25498   
25499           /* Message Buffer Cycle Counter Filter Register */
25500           FR_MBCCFR_16B_tag MBCCFR44;    /* offset: 0x0262 size: 16 bit */
25501   
25502           /* Message Buffer Frame ID Register */
25503           FR_MBFIDR_16B_tag MBFIDR44;    /* offset: 0x0264 size: 16 bit */
25504   
25505           /* Message Buffer Index Register */
25506           FR_MBIDXR_16B_tag MBIDXR44;    /* offset: 0x0266 size: 16 bit */
25507   
25508           /* Message Buffer Configuration Control Status Register */
25509           FR_MBCCSR_16B_tag MBCCSR45;    /* offset: 0x0268 size: 16 bit */
25510   
25511           /* Message Buffer Cycle Counter Filter Register */
25512           FR_MBCCFR_16B_tag MBCCFR45;    /* offset: 0x026A size: 16 bit */
25513   
25514           /* Message Buffer Frame ID Register */
25515           FR_MBFIDR_16B_tag MBFIDR45;    /* offset: 0x026C size: 16 bit */
25516   
25517           /* Message Buffer Index Register */
25518           FR_MBIDXR_16B_tag MBIDXR45;    /* offset: 0x026E size: 16 bit */
25519   
25520           /* Message Buffer Configuration Control Status Register */
25521           FR_MBCCSR_16B_tag MBCCSR46;    /* offset: 0x0270 size: 16 bit */
25522   
25523           /* Message Buffer Cycle Counter Filter Register */
25524           FR_MBCCFR_16B_tag MBCCFR46;    /* offset: 0x0272 size: 16 bit */
25525   
25526           /* Message Buffer Frame ID Register */
25527           FR_MBFIDR_16B_tag MBFIDR46;    /* offset: 0x0274 size: 16 bit */
25528   
25529           /* Message Buffer Index Register */
25530           FR_MBIDXR_16B_tag MBIDXR46;    /* offset: 0x0276 size: 16 bit */
25531   
25532           /* Message Buffer Configuration Control Status Register */
25533           FR_MBCCSR_16B_tag MBCCSR47;    /* offset: 0x0278 size: 16 bit */
25534   
25535           /* Message Buffer Cycle Counter Filter Register */
25536           FR_MBCCFR_16B_tag MBCCFR47;    /* offset: 0x027A size: 16 bit */
25537   
25538           /* Message Buffer Frame ID Register */
25539           FR_MBFIDR_16B_tag MBFIDR47;    /* offset: 0x027C size: 16 bit */
25540   
25541           /* Message Buffer Index Register */
25542           FR_MBIDXR_16B_tag MBIDXR47;    /* offset: 0x027E size: 16 bit */
25543   
25544           /* Message Buffer Configuration Control Status Register */
25545           FR_MBCCSR_16B_tag MBCCSR48;    /* offset: 0x0280 size: 16 bit */
25546   
25547           /* Message Buffer Cycle Counter Filter Register */
25548           FR_MBCCFR_16B_tag MBCCFR48;    /* offset: 0x0282 size: 16 bit */
25549   
25550           /* Message Buffer Frame ID Register */
25551           FR_MBFIDR_16B_tag MBFIDR48;    /* offset: 0x0284 size: 16 bit */
25552   
25553           /* Message Buffer Index Register */
25554           FR_MBIDXR_16B_tag MBIDXR48;    /* offset: 0x0286 size: 16 bit */
25555   
25556           /* Message Buffer Configuration Control Status Register */
25557           FR_MBCCSR_16B_tag MBCCSR49;    /* offset: 0x0288 size: 16 bit */
25558   
25559           /* Message Buffer Cycle Counter Filter Register */
25560           FR_MBCCFR_16B_tag MBCCFR49;    /* offset: 0x028A size: 16 bit */
25561   
25562           /* Message Buffer Frame ID Register */
25563           FR_MBFIDR_16B_tag MBFIDR49;    /* offset: 0x028C size: 16 bit */
25564   
25565           /* Message Buffer Index Register */
25566           FR_MBIDXR_16B_tag MBIDXR49;    /* offset: 0x028E size: 16 bit */
25567   
25568           /* Message Buffer Configuration Control Status Register */
25569           FR_MBCCSR_16B_tag MBCCSR50;    /* offset: 0x0290 size: 16 bit */
25570   
25571           /* Message Buffer Cycle Counter Filter Register */
25572           FR_MBCCFR_16B_tag MBCCFR50;    /* offset: 0x0292 size: 16 bit */
25573   
25574           /* Message Buffer Frame ID Register */
25575           FR_MBFIDR_16B_tag MBFIDR50;    /* offset: 0x0294 size: 16 bit */
25576   
25577           /* Message Buffer Index Register */
25578           FR_MBIDXR_16B_tag MBIDXR50;    /* offset: 0x0296 size: 16 bit */
25579   
25580           /* Message Buffer Configuration Control Status Register */
25581           FR_MBCCSR_16B_tag MBCCSR51;    /* offset: 0x0298 size: 16 bit */
25582   
25583           /* Message Buffer Cycle Counter Filter Register */
25584           FR_MBCCFR_16B_tag MBCCFR51;    /* offset: 0x029A size: 16 bit */
25585   
25586           /* Message Buffer Frame ID Register */
25587           FR_MBFIDR_16B_tag MBFIDR51;    /* offset: 0x029C size: 16 bit */
25588   
25589           /* Message Buffer Index Register */
25590           FR_MBIDXR_16B_tag MBIDXR51;    /* offset: 0x029E size: 16 bit */
25591   
25592           /* Message Buffer Configuration Control Status Register */
25593           FR_MBCCSR_16B_tag MBCCSR52;    /* offset: 0x02A0 size: 16 bit */
25594   
25595           /* Message Buffer Cycle Counter Filter Register */
25596           FR_MBCCFR_16B_tag MBCCFR52;    /* offset: 0x02A2 size: 16 bit */
25597   
25598           /* Message Buffer Frame ID Register */
25599           FR_MBFIDR_16B_tag MBFIDR52;    /* offset: 0x02A4 size: 16 bit */
25600   
25601           /* Message Buffer Index Register */
25602           FR_MBIDXR_16B_tag MBIDXR52;    /* offset: 0x02A6 size: 16 bit */
25603   
25604           /* Message Buffer Configuration Control Status Register */
25605           FR_MBCCSR_16B_tag MBCCSR53;    /* offset: 0x02A8 size: 16 bit */
25606   
25607           /* Message Buffer Cycle Counter Filter Register */
25608           FR_MBCCFR_16B_tag MBCCFR53;    /* offset: 0x02AA size: 16 bit */
25609   
25610           /* Message Buffer Frame ID Register */
25611           FR_MBFIDR_16B_tag MBFIDR53;    /* offset: 0x02AC size: 16 bit */
25612   
25613           /* Message Buffer Index Register */
25614           FR_MBIDXR_16B_tag MBIDXR53;    /* offset: 0x02AE size: 16 bit */
25615   
25616           /* Message Buffer Configuration Control Status Register */
25617           FR_MBCCSR_16B_tag MBCCSR54;    /* offset: 0x02B0 size: 16 bit */
25618   
25619           /* Message Buffer Cycle Counter Filter Register */
25620           FR_MBCCFR_16B_tag MBCCFR54;    /* offset: 0x02B2 size: 16 bit */
25621   
25622           /* Message Buffer Frame ID Register */
25623           FR_MBFIDR_16B_tag MBFIDR54;    /* offset: 0x02B4 size: 16 bit */
25624   
25625           /* Message Buffer Index Register */
25626           FR_MBIDXR_16B_tag MBIDXR54;    /* offset: 0x02B6 size: 16 bit */
25627   
25628           /* Message Buffer Configuration Control Status Register */
25629           FR_MBCCSR_16B_tag MBCCSR55;    /* offset: 0x02B8 size: 16 bit */
25630   
25631           /* Message Buffer Cycle Counter Filter Register */
25632           FR_MBCCFR_16B_tag MBCCFR55;    /* offset: 0x02BA size: 16 bit */
25633   
25634           /* Message Buffer Frame ID Register */
25635           FR_MBFIDR_16B_tag MBFIDR55;    /* offset: 0x02BC size: 16 bit */
25636   
25637           /* Message Buffer Index Register */
25638           FR_MBIDXR_16B_tag MBIDXR55;    /* offset: 0x02BE size: 16 bit */
25639   
25640           /* Message Buffer Configuration Control Status Register */
25641           FR_MBCCSR_16B_tag MBCCSR56;    /* offset: 0x02C0 size: 16 bit */
25642   
25643           /* Message Buffer Cycle Counter Filter Register */
25644           FR_MBCCFR_16B_tag MBCCFR56;    /* offset: 0x02C2 size: 16 bit */
25645   
25646           /* Message Buffer Frame ID Register */
25647           FR_MBFIDR_16B_tag MBFIDR56;    /* offset: 0x02C4 size: 16 bit */
25648   
25649           /* Message Buffer Index Register */
25650           FR_MBIDXR_16B_tag MBIDXR56;    /* offset: 0x02C6 size: 16 bit */
25651   
25652           /* Message Buffer Configuration Control Status Register */
25653           FR_MBCCSR_16B_tag MBCCSR57;    /* offset: 0x02C8 size: 16 bit */
25654   
25655           /* Message Buffer Cycle Counter Filter Register */
25656           FR_MBCCFR_16B_tag MBCCFR57;    /* offset: 0x02CA size: 16 bit */
25657   
25658           /* Message Buffer Frame ID Register */
25659           FR_MBFIDR_16B_tag MBFIDR57;    /* offset: 0x02CC size: 16 bit */
25660   
25661           /* Message Buffer Index Register */
25662           FR_MBIDXR_16B_tag MBIDXR57;    /* offset: 0x02CE size: 16 bit */
25663   
25664           /* Message Buffer Configuration Control Status Register */
25665           FR_MBCCSR_16B_tag MBCCSR58;    /* offset: 0x02D0 size: 16 bit */
25666   
25667           /* Message Buffer Cycle Counter Filter Register */
25668           FR_MBCCFR_16B_tag MBCCFR58;    /* offset: 0x02D2 size: 16 bit */
25669   
25670           /* Message Buffer Frame ID Register */
25671           FR_MBFIDR_16B_tag MBFIDR58;    /* offset: 0x02D4 size: 16 bit */
25672   
25673           /* Message Buffer Index Register */
25674           FR_MBIDXR_16B_tag MBIDXR58;    /* offset: 0x02D6 size: 16 bit */
25675   
25676           /* Message Buffer Configuration Control Status Register */
25677           FR_MBCCSR_16B_tag MBCCSR59;    /* offset: 0x02D8 size: 16 bit */
25678   
25679           /* Message Buffer Cycle Counter Filter Register */
25680           FR_MBCCFR_16B_tag MBCCFR59;    /* offset: 0x02DA size: 16 bit */
25681   
25682           /* Message Buffer Frame ID Register */
25683           FR_MBFIDR_16B_tag MBFIDR59;    /* offset: 0x02DC size: 16 bit */
25684   
25685           /* Message Buffer Index Register */
25686           FR_MBIDXR_16B_tag MBIDXR59;    /* offset: 0x02DE size: 16 bit */
25687   
25688           /* Message Buffer Configuration Control Status Register */
25689           FR_MBCCSR_16B_tag MBCCSR60;    /* offset: 0x02E0 size: 16 bit */
25690   
25691           /* Message Buffer Cycle Counter Filter Register */
25692           FR_MBCCFR_16B_tag MBCCFR60;    /* offset: 0x02E2 size: 16 bit */
25693   
25694           /* Message Buffer Frame ID Register */
25695           FR_MBFIDR_16B_tag MBFIDR60;    /* offset: 0x02E4 size: 16 bit */
25696   
25697           /* Message Buffer Index Register */
25698           FR_MBIDXR_16B_tag MBIDXR60;    /* offset: 0x02E6 size: 16 bit */
25699   
25700           /* Message Buffer Configuration Control Status Register */
25701           FR_MBCCSR_16B_tag MBCCSR61;    /* offset: 0x02E8 size: 16 bit */
25702   
25703           /* Message Buffer Cycle Counter Filter Register */
25704           FR_MBCCFR_16B_tag MBCCFR61;    /* offset: 0x02EA size: 16 bit */
25705   
25706           /* Message Buffer Frame ID Register */
25707           FR_MBFIDR_16B_tag MBFIDR61;    /* offset: 0x02EC size: 16 bit */
25708   
25709           /* Message Buffer Index Register */
25710           FR_MBIDXR_16B_tag MBIDXR61;    /* offset: 0x02EE size: 16 bit */
25711   
25712           /* Message Buffer Configuration Control Status Register */
25713           FR_MBCCSR_16B_tag MBCCSR62;    /* offset: 0x02F0 size: 16 bit */
25714   
25715           /* Message Buffer Cycle Counter Filter Register */
25716           FR_MBCCFR_16B_tag MBCCFR62;    /* offset: 0x02F2 size: 16 bit */
25717   
25718           /* Message Buffer Frame ID Register */
25719           FR_MBFIDR_16B_tag MBFIDR62;    /* offset: 0x02F4 size: 16 bit */
25720   
25721           /* Message Buffer Index Register */
25722           FR_MBIDXR_16B_tag MBIDXR62;    /* offset: 0x02F6 size: 16 bit */
25723   
25724           /* Message Buffer Configuration Control Status Register */
25725           FR_MBCCSR_16B_tag MBCCSR63;    /* offset: 0x02F8 size: 16 bit */
25726   
25727           /* Message Buffer Cycle Counter Filter Register */
25728           FR_MBCCFR_16B_tag MBCCFR63;    /* offset: 0x02FA size: 16 bit */
25729   
25730           /* Message Buffer Frame ID Register */
25731           FR_MBFIDR_16B_tag MBFIDR63;    /* offset: 0x02FC size: 16 bit */
25732   
25733           /* Message Buffer Index Register */
25734           FR_MBIDXR_16B_tag MBIDXR63;    /* offset: 0x02FE size: 16 bit */
25735         };
25736       };
25737   
25738       int8_t FR_reserved_0300[15616];
25739     } FR_tag;
25740   
25741     typedef union uF_HEADER              /* frame header */
25742     {
25743       struct {
25744        vuint16_t:
25745         1;
25746         vuint16_t PPI:1;                 /* Payload Preamble Indicator */
25747         vuint16_t NUF:1;                 /* Null Frame Indicator */
25748         vuint16_t SYF:1;                 /* Sync Frame Indicator */
25749         vuint16_t SUF:1;                 /* Startup Frame Indicator */
25750         vuint16_t FID:11;                /* Frame ID */
25751        vuint16_t:
25752         2;
25753         vuint16_t CYCCNT:6;              /* Cycle Count */
25754        vuint16_t:
25755         1;
25756         vuint16_t PLDLEN:7;              /* Payload Length */
25757        vuint16_t:
25758         5;
25759         vuint16_t HDCRC:11;              /* Header CRC */
25760       } B;
25761   
25762       vuint16_t WORDS[3];
25763     } F_HEADER_t;
25764   
25765     typedef union uS_STSTUS              /* slot status */
25766     {
25767       struct {
25768         vuint16_t VFB:1;                 /* Valid Frame on channel B */
25769         vuint16_t SYB:1;                 /* Sync Frame Indicator channel B */
25770         vuint16_t NFB:1;                 /* Null Frame Indicator channel B */
25771         vuint16_t SUB:1;                 /* Startup Frame Indicator channel B */
25772         vuint16_t SEB:1;                 /* Syntax Error on channel B */
25773         vuint16_t CEB:1;                 /* Content Error on channel B */
25774         vuint16_t BVB:1;                 /* Boundary Violation on channel B */
25775         vuint16_t CH:1;                  /* Channel */
25776         vuint16_t VFA:1;                 /* Valid Frame on channel A */
25777         vuint16_t SYA:1;                 /* Sync Frame Indicator channel A */
25778         vuint16_t NFA:1;                 /* Null Frame Indicator channel A */
25779         vuint16_t SUA:1;                 /* Startup Frame Indicator channel A */
25780         vuint16_t SEA:1;                 /* Syntax Error on channel A */
25781         vuint16_t CEA:1;                 /* Content Error on channel A */
25782         vuint16_t BVA:1;                 /* Boundary Violation on channel A */
25783        vuint16_t:
25784         1;
25785       } RX;
25786   
25787       struct {
25788         vuint16_t VFB:1;                 /* Valid Frame on channel B */
25789         vuint16_t SYB:1;                 /* Sync Frame Indicator channel B */
25790         vuint16_t NFB:1;                 /* Null Frame Indicator channel B */
25791         vuint16_t SUB:1;                 /* Startup Frame Indicator channel B */
25792         vuint16_t SEB:1;                 /* Syntax Error on channel B */
25793         vuint16_t CEB:1;                 /* Content Error on channel B */
25794         vuint16_t BVB:1;                 /* Boundary Violation on channel B */
25795         vuint16_t TCB:1;                 /* Tx Conflict on channel B */
25796         vuint16_t VFA:1;                 /* Valid Frame on channel A */
25797         vuint16_t SYA:1;                 /* Sync Frame Indicator channel A */
25798         vuint16_t NFA:1;                 /* Null Frame Indicator channel A */
25799         vuint16_t SUA:1;                 /* Startup Frame Indicator channel A */
25800         vuint16_t SEA:1;                 /* Syntax Error on channel A */
25801         vuint16_t CEA:1;                 /* Content Error on channel A */
25802         vuint16_t BVA:1;                 /* Boundary Violation on channel A */
25803         vuint16_t TCA:1;                 /* Tx Conflict on channel A */
25804       } TX;
25805   
25806       vuint16_t R;
25807     } S_STATUS_t;
25808   
25809     typedef struct uMB_HEADER            /* message buffer header */
25810     {
25811       F_HEADER_t FRAME_HEADER;
25812       vuint16_t DATA_OFFSET;
25813       S_STATUS_t SLOT_STATUS;
25814     } MB_HEADER_t;
25815   
25816   #define FR                             (*(volatile FR_tag *) 0xFFFE0000UL)
25817   #ifdef __MWERKS__
25818   
25819   #pragma pop
25820   
25821   #endif
25822   
25823   #ifdef __cplusplus
25824   
25825   }
25826   #endif
25827   #endif                                 /* _leopard_H_*/
25828   
25829   /* End of file */
25830